diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h | 127 |
1 files changed, 62 insertions, 65 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h index 98113519a5..2a438f1bbe 100644 --- a/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h @@ -10,20 +10,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _EFI_EHCI_REG_H_
#define _EFI_EHCI_REG_H_
-
-
//
// Capability register offset
//
-#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
-#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
-#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
+#define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset
+#define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h
+#define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset
//
// Capability register bit definition
//
-#define HCSP_NPORTS 0x0F // Number of root hub port
-#define HCCP_64BIT 0x01 // 64-bit addressing capability
+#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
// Operational register offset
@@ -38,61 +36,61 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset
#define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset
-#define EHC_FRAME_LEN 1024
+#define EHC_FRAME_LEN 1024
//
// Register bit definition
//
-#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
-
-#define USBCMD_RUN 0x01 // Run/stop
-#define USBCMD_RESET 0x02 // Start the host controller reset
-#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
-#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
-#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
-
-#define USBSTS_IAA 0x20 // Interrupt on async advance
-#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
-#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
-#define USBSTS_HALT 0x1000 // Host controller halted
-#define USBSTS_SYS_ERROR 0x10 // Host system error
-#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
+#define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC
+
+#define USBCMD_RUN 0x01 // Run/stop
+#define USBCMD_RESET 0x02 // Start the host controller reset
+#define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule
+#define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule
+#define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell
+
+#define USBSTS_IAA 0x20 // Interrupt on async advance
+#define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status
+#define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status
+#define USBSTS_HALT 0x1000 // Host controller halted
+#define USBSTS_SYS_ERROR 0x10 // Host system error
+#define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC
// (write clean) bits in USBSTS register
-#define PORTSC_CONN 0x01 // Current Connect Status
-#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
-#define PORTSC_ENABLED 0x04 // Port Enable / Disable
-#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
-#define PORTSC_OVERCUR 0x10 // Over current Active
-#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
-#define PORSTSC_RESUME 0x40 // Force Port Resume
-#define PORTSC_SUSPEND 0x80 // Port Suspend State
-#define PORTSC_RESET 0x100 // Port Reset
-#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
-#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
-#define PORTSC_POWER 0x1000 // Port Power
-#define PORTSC_OWNER 0x2000 // Port Owner
-#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
+#define PORTSC_CONN 0x01 // Current Connect Status
+#define PORTSC_CONN_CHANGE 0x02 // Connect Status Change
+#define PORTSC_ENABLED 0x04 // Port Enable / Disable
+#define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change
+#define PORTSC_OVERCUR 0x10 // Over current Active
+#define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change
+#define PORSTSC_RESUME 0x40 // Force Port Resume
+#define PORTSC_SUSPEND 0x80 // Port Suspend State
+#define PORTSC_RESET 0x100 // Port Reset
+#define PORTSC_LINESTATE_K 0x400 // Line Status K-state
+#define PORTSC_LINESTATE_J 0x800 // Line Status J-state
+#define PORTSC_POWER 0x1000 // Port Power
+#define PORTSC_OWNER 0x2000 // Port Owner
+#define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,
// they are WC (write clean)
//
// PCI Configuration Registers
//
-#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
+#define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10
-#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
+#define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
#define EHC_ADDR(High, QhHw32) \
((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
-#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
+#define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
//
// Structure to map the hardware port states to the
// UEFI's port states.
//
typedef struct {
- UINT16 HwState;
- UINT16 UefiState;
+ UINT16 HwState;
+ UINT16 UefiState;
} USB_PORT_STATE_MAP;
//
@@ -100,13 +98,12 @@ typedef struct { //
#pragma pack(1)
typedef struct {
- UINT8 Pi;
- UINT8 SubClassCode;
- UINT8 BaseCode;
+ UINT8 Pi;
+ UINT8 SubClassCode;
+ UINT8 BaseCode;
} USB_CLASSC;
#pragma pack()
-
/**
Read EHCI capability register.
@@ -118,8 +115,8 @@ typedef struct { **/
UINT32
EhcReadCapRegister (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -134,8 +131,8 @@ EhcReadCapRegister ( **/
UINT32
EhcReadOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset
)
;
@@ -149,9 +146,9 @@ EhcReadOpReg ( **/
VOID
EhcWriteOpReg (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
;
@@ -163,7 +160,7 @@ EhcWriteOpReg ( **/
VOID
EhcClearLegacySupport (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -180,8 +177,8 @@ EhcClearLegacySupport ( **/
EFI_STATUS
EhcSetAndWaitDoorBell (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -194,7 +191,7 @@ EhcSetAndWaitDoorBell ( **/
VOID
EhcAckAllInterrupt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -209,7 +206,7 @@ EhcAckAllInterrupt ( **/
BOOLEAN
EhcIsHalt (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -224,7 +221,7 @@ EhcIsHalt ( **/
BOOLEAN
EhcIsSysError (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
@@ -240,8 +237,8 @@ EhcIsSysError ( **/
EFI_STATUS
EhcResetHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -257,8 +254,8 @@ EhcResetHC ( **/
EFI_STATUS
EhcHaltHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -274,8 +271,8 @@ EhcHaltHC ( **/
EFI_STATUS
EhcRunHC (
- IN PEI_USB2_HC_DEV *Ehc,
- IN UINT32 Timeout
+ IN PEI_USB2_HC_DEV *Ehc,
+ IN UINT32 Timeout
)
;
@@ -296,7 +293,7 @@ EhcRunHC ( **/
EFI_STATUS
EhcInitHC (
- IN PEI_USB2_HC_DEV *Ehc
+ IN PEI_USB2_HC_DEV *Ehc
)
;
|