summaryrefslogtreecommitdiffstats
path: root/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
diff options
context:
space:
mode:
Diffstat (limited to 'MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c')
-rw-r--r--MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c204
1 files changed, 105 insertions, 99 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
index 1d7e3d26e0..ac956bdce4 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
@@ -22,14 +22,14 @@
**/
EFI_STATUS
NvmeMmioRead (
- IN OUT VOID *MemBuffer,
- IN UINTN MmioAddr,
- IN UINTN Size
+ IN OUT VOID *MemBuffer,
+ IN UINTN MmioAddr,
+ IN UINTN Size
)
{
- UINTN Offset;
- UINT8 Data;
- UINT8 *Ptr;
+ UINTN Offset;
+ UINT8 Data;
+ UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -52,9 +52,10 @@ NvmeMmioRead (
default:
Ptr = (UINT8 *)MemBuffer;
for (Offset = 0; Offset < Size; Offset += 1) {
- Data = MmioRead8 (MmioAddr + Offset);
+ Data = MmioRead8 (MmioAddr + Offset);
Ptr[Offset] = Data;
}
+
break;
}
@@ -73,14 +74,14 @@ NvmeMmioRead (
**/
EFI_STATUS
NvmeMmioWrite (
- IN OUT UINTN MmioAddr,
- IN VOID *MemBuffer,
- IN UINTN Size
+ IN OUT UINTN MmioAddr,
+ IN VOID *MemBuffer,
+ IN UINTN Size
)
{
- UINTN Offset;
- UINT8 Data;
- UINT8 *Ptr;
+ UINTN Offset;
+ UINT8 Data;
+ UINT8 *Ptr;
// priority has adjusted
switch (Size) {
@@ -106,6 +107,7 @@ NvmeMmioWrite (
Data = Ptr[Offset];
MmioWrite8 (MmioAddr + Offset, Data);
}
+
break;
}
@@ -122,18 +124,18 @@ NvmeMmioWrite (
**/
UINT32
NvmeBaseMemPageOffset (
- IN UINTN BaseMemIndex
+ IN UINTN BaseMemIndex
)
{
- UINT32 Pages;
- UINTN Index;
- UINT32 PageSizeList[5];
+ UINT32 Pages;
+ UINTN Index;
+ UINT32 PageSizeList[5];
- PageSizeList[0] = 1; /* ASQ */
- PageSizeList[1] = 1; /* ACQ */
- PageSizeList[2] = 1; /* SQs */
- PageSizeList[3] = 1; /* CQs */
- PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
+ PageSizeList[0] = 1; /* ASQ */
+ PageSizeList[1] = 1; /* ACQ */
+ PageSizeList[2] = 1; /* SQs */
+ PageSizeList[3] = 1; /* CQs */
+ PageSizeList[4] = NVME_PRP_SIZE; /* PRPs */
if (BaseMemIndex > MAX_BASEMEM_COUNT) {
DEBUG ((DEBUG_ERROR, "%a: The input BaseMem index is invalid.\n", __FUNCTION__));
@@ -161,14 +163,14 @@ NvmeBaseMemPageOffset (
**/
EFI_STATUS
NvmeWaitController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN BOOLEAN WaitReady
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN BOOLEAN WaitReady
)
{
- NVME_CSTS Csts;
- EFI_STATUS Status;
- UINT32 Index;
- UINT8 Timeout;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT8 Timeout;
//
// Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
@@ -181,19 +183,19 @@ NvmeWaitController (
}
Status = EFI_SUCCESS;
- for(Index = (Timeout * 500); Index != 0; --Index) {
+ for (Index = (Timeout * 500); Index != 0; --Index) {
MicroSecondDelay (1000);
//
// Check if the controller is initialized
//
Status = NVME_GET_CSTS (Private, &Csts);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NVME_GET_CSTS fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
- if ((BOOLEAN) Csts.Rdy == WaitReady) {
+ if ((BOOLEAN)Csts.Rdy == WaitReady) {
break;
}
}
@@ -216,12 +218,12 @@ NvmeWaitController (
**/
EFI_STATUS
NvmeDisableController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- NVME_CSTS Csts;
- EFI_STATUS Status;
+ NVME_CC Cc;
+ NVME_CSTS Csts;
+ EFI_STATUS Status;
Status = NVME_GET_CSTS (Private, &Csts);
@@ -271,11 +273,11 @@ ErrorExit:
**/
EFI_STATUS
NvmeEnableController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- NVME_CC Cc;
- EFI_STATUS Status;
+ NVME_CC Cc;
+ EFI_STATUS Status;
//
// Enable the controller
@@ -316,25 +318,25 @@ ErrorExit:
**/
EFI_STATUS
NvmeIdentifyController (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
//
// According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
// For the Identify command, the Namespace Identifier is only used for the Namespace Data structure.
//
- Command.Nsid = 0;
+ Command.Nsid = 0;
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
@@ -369,19 +371,19 @@ NvmeIdentifyController (
**/
EFI_STATUS
NvmeIdentifyNamespace (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_CMD;
Command.Nsid = NamespaceId;
@@ -414,11 +416,11 @@ NvmeIdentifyNamespace (
**/
VOID
NvmeDumpControllerData (
- IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
+ IN NVME_ADMIN_CONTROLLER_DATA *ControllerData
)
{
- UINT8 Sn[21];
- UINT8 Mn[41];
+ UINT8 Sn[21];
+ UINT8 Mn[41];
CopyMem (Sn, ControllerData->Sn, sizeof (ControllerData->Sn));
Sn[20] = 0;
@@ -428,11 +430,11 @@ NvmeDumpControllerData (
DEBUG ((DEBUG_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
DEBUG ((DEBUG_INFO, " PCI VID : 0x%x\n", ControllerData->Vid));
DEBUG ((DEBUG_INFO, " PCI SSVID : 0x%x\n", ControllerData->Ssvid));
- DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
- DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
- DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64*)ControllerData->Fr)));
+ DEBUG ((DEBUG_INFO, " SN : %a\n", Sn));
+ DEBUG ((DEBUG_INFO, " MN : %a\n", Mn));
+ DEBUG ((DEBUG_INFO, " FR : 0x%lx\n", *((UINT64 *)ControllerData->Fr)));
DEBUG ((DEBUG_INFO, " RAB : 0x%x\n", ControllerData->Rab));
- DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32*)ControllerData->Ieee_oui));
+ DEBUG ((DEBUG_INFO, " IEEE : 0x%x\n", *(UINT32 *)ControllerData->Ieee_oui));
DEBUG ((DEBUG_INFO, " AERL : 0x%x\n", ControllerData->Aerl));
DEBUG ((DEBUG_INFO, " SQES : 0x%x\n", ControllerData->Sqes));
DEBUG ((DEBUG_INFO, " CQES : 0x%x\n", ControllerData->Cqes));
@@ -451,24 +453,24 @@ NvmeDumpControllerData (
**/
EFI_STATUS
NvmeCreateIoCompletionQueue (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOCQ CrIoCq;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOCQ CrIoCq;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_CMD;
CommandPacket.TransferBuffer = Private->CqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -499,24 +501,24 @@ NvmeCreateIoCompletionQueue (
**/
EFI_STATUS
NvmeCreateIoSubmissionQueue (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
- EFI_NVM_EXPRESS_COMMAND Command;
- EFI_NVM_EXPRESS_COMPLETION Completion;
- EFI_STATUS Status;
- NVME_ADMIN_CRIOSQ CrIoSq;
+ EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
+ EFI_NVM_EXPRESS_COMMAND Command;
+ EFI_NVM_EXPRESS_COMPLETION Completion;
+ EFI_STATUS Status;
+ NVME_ADMIN_CRIOSQ CrIoSq;
- ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
- ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
- ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
- ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
+ ZeroMem (&CommandPacket, sizeof (EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
+ ZeroMem (&Command, sizeof (EFI_NVM_EXPRESS_COMMAND));
+ ZeroMem (&Completion, sizeof (EFI_NVM_EXPRESS_COMPLETION));
+ ZeroMem (&CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
CommandPacket.NvmeCmd = &Command;
CommandPacket.NvmeCompletion = &Completion;
- Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
+ Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_CMD;
CommandPacket.TransferBuffer = Private->SqBuffer[NVME_IO_QUEUE];
CommandPacket.TransferLength = EFI_PAGE_SIZE;
CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
@@ -549,15 +551,15 @@ NvmeCreateIoSubmissionQueue (
**/
EFI_STATUS
NvmeControllerInit (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
- EFI_STATUS Status;
- UINTN Index;
- NVME_AQA Aqa;
- NVME_ASQ Asq;
- NVME_ACQ Acq;
- NVME_VER Ver;
+ EFI_STATUS Status;
+ UINTN Index;
+ NVME_AQA Aqa;
+ NVME_ASQ Asq;
+ NVME_ACQ Acq;
+ NVME_VER Ver;
//
// Dump the NVME controller implementation version
@@ -589,6 +591,7 @@ NvmeControllerInit (
ZeroMem ((VOID *)(UINTN)(&Private->SqTdbl[Index]), sizeof (NVME_SQTDBL));
ZeroMem ((VOID *)(UINTN)(&Private->CqHdbl[Index]), sizeof (NVME_CQHDBL));
}
+
ZeroMem (Private->Buffer, EFI_PAGE_SIZE * NVME_MEM_MAX_PAGES);
//
@@ -657,11 +660,13 @@ NvmeControllerInit (
return EFI_OUT_OF_RESOURCES;
}
}
+
Status = NvmeIdentifyController (Private, Private->ControllerData);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: NvmeIdentifyController fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
+
NvmeDumpControllerData (Private->ControllerData);
//
@@ -684,6 +689,7 @@ NvmeControllerInit (
DEBUG ((DEBUG_ERROR, "%a: Create IO completion queue fail, Status - %r\n", __FUNCTION__, Status));
return Status;
}
+
Status = NvmeCreateIoSubmissionQueue (Private);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Create IO submission queue fail, Status - %r\n", __FUNCTION__, Status));
@@ -700,17 +706,17 @@ NvmeControllerInit (
**/
VOID
NvmeFreeDmaResource (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
)
{
ASSERT (Private != NULL);
if (Private->BufferMapping != NULL) {
IoMmuFreeBuffer (
- NVME_MEM_MAX_PAGES,
- Private->Buffer,
- Private->BufferMapping
- );
+ NVME_MEM_MAX_PAGES,
+ Private->Buffer,
+ Private->BufferMapping
+ );
}
return;