diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h index 89fee735fe..a6bec510f0 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h @@ -43,14 +43,13 @@ enum { //
// All of base memories are 4K(0x1000) alignment
//
-#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
-#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
-#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
-
+#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)
+#define NVME_MEM_BASE(Private) ((UINTN)(Private->Buffer))
+#define NVME_ASQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_ACQ_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_SQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_CQ_BASE(Private, Index) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
+#define NVME_PRP_BASE(Private) (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
/**
Transfer MMIO Data to memory.
@@ -64,9 +63,9 @@ enum { **/
EFI_STATUS
NvmeMmioRead (
- IN OUT VOID *MemBuffer,
- IN UINTN MmioAddr,
- IN UINTN Size
+ IN OUT VOID *MemBuffer,
+ IN UINTN MmioAddr,
+ IN UINTN Size
);
/**
@@ -81,9 +80,9 @@ NvmeMmioRead ( **/
EFI_STATUS
NvmeMmioWrite (
- IN OUT UINTN MmioAddr,
- IN VOID *MemBuffer,
- IN UINTN Size
+ IN OUT UINTN MmioAddr,
+ IN VOID *MemBuffer,
+ IN UINTN Size
);
/**
@@ -96,7 +95,7 @@ NvmeMmioWrite ( **/
UINT32
NvmeBaseMemPageOffset (
- IN UINTN BaseMemIndex
+ IN UINTN BaseMemIndex
);
/**
@@ -110,7 +109,7 @@ NvmeBaseMemPageOffset ( **/
EFI_STATUS
NvmeControllerInit (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
/**
@@ -126,9 +125,9 @@ NvmeControllerInit ( **/
EFI_STATUS
NvmeIdentifyNamespace (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
- IN UINT32 NamespaceId,
- IN VOID *Buffer
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private,
+ IN UINT32 NamespaceId,
+ IN VOID *Buffer
);
/**
@@ -139,7 +138,7 @@ NvmeIdentifyNamespace ( **/
VOID
NvmeFreeDmaResource (
- IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
+ IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private
);
#endif
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