diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 1268 |
1 files changed, 621 insertions, 647 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 5111bd513a..ed7f2d4ac6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -9,13 +9,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h"
-extern CHAR16 *mBarTypeStr[];
-extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
+extern CHAR16 *mBarTypeStr[];
+extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityProtocol;
-#define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
-#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
-#define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
-#define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
+#define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
+#define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
+#define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
+#define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
/**
This routine is used to check whether the pci device is present.
@@ -32,11 +32,11 @@ extern EDKII_DEVICE_SECURITY_PROTOCOL *mDeviceSecurityP **/
EFI_STATUS
PciDevicePresent (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
- OUT PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
+ OUT PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
UINT64 Address;
@@ -58,7 +58,7 @@ PciDevicePresent ( Pci
);
- if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {
+ if (!EFI_ERROR (Status) && ((Pci->Hdr).VendorId != 0xffff)) {
//
// Read the entire config header for the device
//
@@ -91,37 +91,35 @@ PciDevicePresent ( **/
EFI_STATUS
PciPciDeviceInfoCollector (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT8 Func;
- UINT8 SecBus;
- PCI_IO_DEVICE *PciIoDevice;
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT8 Func;
+ UINT8 SecBus;
+ PCI_IO_DEVICE *PciIoDevice;
+ EFI_PCI_IO_PROTOCOL *PciIo;
- Status = EFI_SUCCESS;
- SecBus = 0;
+ Status = EFI_SUCCESS;
+ SecBus = 0;
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
-
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether PCI device is present
//
Status = PciDevicePresent (
Bridge->PciRootBridgeIo,
&Pci,
- (UINT8) StartBusNumber,
- (UINT8) Device,
- (UINT8) Func
+ (UINT8)StartBusNumber,
+ (UINT8)Device,
+ (UINT8)Func
);
- if (EFI_ERROR (Status) && Func == 0) {
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -129,11 +127,10 @@ PciPciDeviceInfoCollector ( }
if (!EFI_ERROR (Status)) {
-
//
// Call back to host bridge function
//
- PreprocessController (Bridge, (UINT8) StartBusNumber, Device, Func, EfiPciBeforeResourceCollection);
+ PreprocessController (Bridge, (UINT8)StartBusNumber, Device, Func, EfiPciBeforeResourceCollection);
//
// Collect all the information about the PCI device discovered
@@ -141,7 +138,7 @@ PciPciDeviceInfoCollector ( Status = PciSearchDevice (
Bridge,
&Pci,
- (UINT8) StartBusNumber,
+ (UINT8)StartBusNumber,
Device,
Func,
&PciIoDevice
@@ -152,13 +149,12 @@ PciPciDeviceInfoCollector ( //
//
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
-
//
// If it is PPB, we need to get the secondary bus to continue the enumeration
//
- PciIo = &(PciIoDevice->PciIo);
+ PciIo = &(PciIoDevice->PciIo);
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
@@ -182,20 +178,17 @@ PciPciDeviceInfoCollector ( //
Status = PciPciDeviceInfoCollector (
PciIoDevice,
- (UINT8) (SecBus)
+ (UINT8)(SecBus)
);
-
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
-
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
Func = PCI_MAX_FUNC;
}
}
-
}
}
@@ -218,15 +211,15 @@ PciPciDeviceInfoCollector ( **/
EFI_STATUS
PciSearchDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func,
- OUT PCI_IO_DEVICE **PciDevice
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func,
+ OUT PCI_IO_DEVICE **PciDevice
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = NULL;
@@ -235,12 +228,13 @@ PciSearchDevice ( "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
IS_PCI_BRIDGE (Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (Pci) ? L"P2C" :
- L"PCI",
- Bus, Device, Func
+ L"PCI",
+ Bus,
+ Device,
+ Func
));
if (!IS_PCI_BRIDGE (Pci)) {
-
if (IS_CARDBUS_BRIDGE (Pci)) {
PciIoDevice = GatherP2CInfo (
Bridge,
@@ -253,7 +247,6 @@ PciSearchDevice ( InitializeP2C (PciIoDevice);
}
} else {
-
//
// Create private data for Pci Device
//
@@ -264,11 +257,8 @@ PciSearchDevice ( Device,
Func
);
-
}
-
} else {
-
//
// Create private data for PPB
//
@@ -305,15 +295,11 @@ PciSearchDevice ( // Detect this function has option rom
//
if (gFullEnumeration) {
-
if (!IS_CARDBUS_BRIDGE (Pci)) {
-
GetOpRomInfo (PciIoDevice);
-
}
ResetPowerManagementFeature (PciIoDevice);
-
}
//
@@ -341,28 +327,26 @@ PciSearchDevice ( **/
VOID
DumpPpbPaddingResource (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN PCI_BAR_TYPE ResourceType
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN PCI_BAR_TYPE ResourceType
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- PCI_BAR_TYPE Type;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ PCI_BAR_TYPE Type;
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {
return;
}
- if (ResourceType == PciBarTypeIo16 || ResourceType == PciBarTypeIo32) {
+ if ((ResourceType == PciBarTypeIo16) || (ResourceType == PciBarTypeIo32)) {
ResourceType = PciBarTypeIo;
}
for (Descriptor = PciIoDevice->ResourcePaddingDescriptors; Descriptor->Desc != ACPI_END_TAG_DESCRIPTOR; Descriptor++) {
-
Type = PciBarTypeUnknown;
- if (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {
+ if ((Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_IO)) {
Type = PciBarTypeIo;
- } else if (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
-
+ } else if ((Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM)) {
if (Descriptor->AddrSpaceGranularity == 32) {
//
// prefetchable
@@ -400,11 +384,12 @@ DumpPpbPaddingResource ( DEBUG ((
DEBUG_INFO,
" Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
- mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen
+ mBarTypeStr[Type],
+ Descriptor->AddrRangeMax,
+ Descriptor->AddrLen
));
}
}
-
}
/**
@@ -414,10 +399,10 @@ DumpPpbPaddingResource ( **/
VOID
DumpPciBars (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
if (PciIoDevice->PciBar[Index].BarType == PciBarTypeUnknown) {
@@ -427,8 +412,11 @@ DumpPciBars ( DEBUG ((
DEBUG_INFO,
" BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
- Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
- PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Length, PciIoDevice->PciBar[Index].Offset
+ Index,
+ mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTypeMaxType)],
+ PciIoDevice->PciBar[Index].Alignment,
+ PciIoDevice->PciBar[Index].Length,
+ PciIoDevice->PciBar[Index].Offset
));
}
@@ -440,10 +428,14 @@ DumpPciBars ( DEBUG ((
DEBUG_INFO,
" VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
- Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
- PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index].Length, PciIoDevice->VfPciBar[Index].Offset
+ Index,
+ mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBarTypeMaxType)],
+ PciIoDevice->VfPciBar[Index].Alignment,
+ PciIoDevice->VfPciBar[Index].Length,
+ PciIoDevice->VfPciBar[Index].Offset
));
}
+
DEBUG ((DEBUG_INFO, "\n"));
}
@@ -461,16 +453,16 @@ DumpPciBars ( **/
PCI_IO_DEVICE *
GatherDeviceInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- UINTN Offset;
- UINTN BarIndex;
- PCI_IO_DEVICE *PciIoDevice;
+ UINTN Offset;
+ UINTN BarIndex;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -488,9 +480,7 @@ GatherDeviceInfo ( // If it is a full enumeration, disconnect the device in advance
//
if (gFullEnumeration) {
-
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
-
}
//
@@ -503,17 +493,19 @@ GatherDeviceInfo ( //
// Parse the SR-IOV VF bars
//
- if (PcdGetBool (PcdSrIovSupport) && PciIoDevice->SrIovCapabilityOffset != 0) {
+ if (PcdGetBool (PcdSrIovSupport) && (PciIoDevice->SrIovCapabilityOffset != 0)) {
for (Offset = PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0, BarIndex = 0;
Offset <= PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5;
- BarIndex++) {
-
+ BarIndex++)
+ {
ASSERT (BarIndex < PCI_MAX_BAR);
Offset = PciIovParseVfBar (PciIoDevice, Offset, BarIndex);
}
}
- DEBUG_CODE (DumpPciBars (PciIoDevice););
+ DEBUG_CODE (
+ DumpPciBars (PciIoDevice);
+ );
return PciIoDevice;
}
@@ -531,21 +523,21 @@ GatherDeviceInfo ( **/
PCI_IO_DEVICE *
GatherPpbInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- PCI_IO_DEVICE *PciIoDevice;
- EFI_STATUS Status;
- UINT8 Value;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 Temp;
- UINT32 PMemBaseLimit;
- UINT16 PrefetchableMemoryBase;
- UINT16 PrefetchableMemoryLimit;
+ PCI_IO_DEVICE *PciIoDevice;
+ EFI_STATUS Status;
+ UINT8 Value;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Temp;
+ UINT32 PMemBaseLimit;
+ UINT16 PrefetchableMemoryBase;
+ UINT16 PrefetchableMemoryLimit;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -566,7 +558,6 @@ GatherPpbInfo ( // Initialize the bridge control register
//
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
-
}
//
@@ -628,11 +619,11 @@ GatherPpbInfo ( }
Status = BarExisted (
- PciIoDevice,
- 0x24,
- NULL,
- &PMemBaseLimit
- );
+ PciIoDevice,
+ 0x24,
+ NULL,
+ &PMemBaseLimit
+ );
//
// Test if it supports 64 memory or not
@@ -642,17 +633,18 @@ GatherPpbInfo ( // 0 - the bridge supports only 32 bit addresses.
// 1 - the bridge supports 64-bit addresses.
//
- PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);
+ PrefetchableMemoryBase = (UINT16)(PMemBaseLimit & 0xffff);
PrefetchableMemoryLimit = (UINT16)(PMemBaseLimit >> 16);
if (!EFI_ERROR (Status) &&
- (PrefetchableMemoryBase & 0x000f) == 0x0001 &&
- (PrefetchableMemoryLimit & 0x000f) == 0x0001) {
+ ((PrefetchableMemoryBase & 0x000f) == 0x0001) &&
+ ((PrefetchableMemoryLimit & 0x000f) == 0x0001))
+ {
Status = BarExisted (
- PciIoDevice,
- 0x28,
- NULL,
- NULL
- );
+ PciIoDevice,
+ 0x28,
+ NULL,
+ NULL
+ );
if (!EFI_ERROR (Status)) {
PciIoDevice->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
@@ -672,12 +664,11 @@ GatherPpbInfo ( DEBUG_CODE (
DumpPpbPaddingResource (PciIoDevice, PciBarTypeUnknown);
DumpPciBars (PciIoDevice);
- );
+ );
return PciIoDevice;
}
-
/**
Create PCI device instance for PCI Card bridge device.
@@ -692,14 +683,14 @@ GatherPpbInfo ( **/
PCI_IO_DEVICE *
GatherP2CInfo (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
- PCI_IO_DEVICE *PciIoDevice;
+ PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = CreatePciIoDevice (
Bridge,
@@ -735,7 +726,9 @@ GatherP2CInfo ( EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
EFI_BRIDGE_IO32_DECODE_SUPPORTED;
- DEBUG_CODE (DumpPciBars (PciIoDevice););
+ DEBUG_CODE (
+ DumpPciBars (PciIoDevice);
+ );
return PciIoDevice;
}
@@ -751,18 +744,17 @@ GatherP2CInfo ( **/
EFI_DEVICE_PATH_PROTOCOL *
CreatePciDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
-
- PCI_DEVICE_PATH PciNode;
+ PCI_DEVICE_PATH PciNode;
//
// Create PCI device path
//
- PciNode.Header.Type = HARDWARE_DEVICE_PATH;
- PciNode.Header.SubType = HW_PCI_DP;
+ PciNode.Header.Type = HARDWARE_DEVICE_PATH;
+ PciNode.Header.SubType = HW_PCI_DP;
SetDevicePathNodeLength (&PciNode.Header, sizeof (PciNode));
PciNode.Device = PciIoDevice->DeviceNumber;
@@ -786,16 +778,16 @@ CreatePciDevicePath ( **/
EFI_STATUS
VfBarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 OriginalValue;
- UINT32 Value;
- EFI_TPL OldTpl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 OriginalValue;
+ UINT32 Value;
+ EFI_TPL OldTpl;
//
// Ensure it is called properly
@@ -860,36 +852,36 @@ VfBarExisted ( **/
EFI_STATUS
BarExisted (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINTN Offset,
- OUT UINT32 *BarLengthValue,
- OUT UINT32 *OriginalBarValue
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINTN Offset,
+ OUT UINT32 *BarLengthValue,
+ OUT UINT32 *OriginalBarValue
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT32 OriginalValue;
- UINT32 Value;
- EFI_TPL OldTpl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 OriginalValue;
+ UINT32 Value;
+ EFI_TPL OldTpl;
PciIo = &PciIoDevice->PciIo;
//
// Preserve the original value
//
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &OriginalValue);
//
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
- PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &gAllOne);
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &Value);
//
// Write back the original value
//
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8)Offset, 1, &OriginalValue);
//
// Restore TPL to its original level
@@ -925,15 +917,15 @@ BarExisted ( **/
VOID
PciTestSupportedAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN OUT UINT16 *Command,
- IN OUT UINT16 *BridgeControl,
- OUT UINT16 *OldCommand,
- OUT UINT16 *OldBridgeControl
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN OUT UINT16 *Command,
+ IN OUT UINT16 *BridgeControl,
+ OUT UINT16 *OldCommand,
+ OUT UINT16 *OldBridgeControl
)
{
- EFI_TPL OldTpl;
- UINT16 CommandValue;
+ EFI_TPL OldTpl;
+ UINT16 CommandValue;
//
// Preserve the original value
@@ -943,7 +935,7 @@ PciTestSupportedAttribute ( //
// Raise TPL to high level to disable timer interrupt while the BAR is probed
//
- OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
CommandValue = *Command | *OldCommand;
PCI_SET_COMMAND_REGISTER (PciIoDevice, CommandValue);
@@ -961,7 +953,6 @@ PciTestSupportedAttribute ( gBS->RestoreTPL (OldTpl);
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
-
//
// Preserve the original value
//
@@ -984,7 +975,6 @@ PciTestSupportedAttribute ( // Restore TPL to its original level
//
gBS->RestoreTPL (OldTpl);
-
} else {
*OldBridgeControl = 0;
*BridgeControl = 0;
@@ -1002,10 +992,10 @@ PciTestSupportedAttribute ( **/
VOID
PciSetDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT16 Command,
- IN UINT16 BridgeControl,
- IN UINTN Option
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT16 Command,
+ IN UINT16 BridgeControl,
+ IN UINTN Option
)
{
UINT64 Attributes;
@@ -1044,18 +1034,17 @@ PciSetDeviceAttribute ( }
if (Option == EFI_SET_SUPPORTS) {
-
- Attributes |= (UINT64) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
- EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
- EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
+ Attributes |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE |
+ EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED |
+ EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE |
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
if (IS_PCI_LPC (&PciIoDevice->Pci)) {
- Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
- Attributes |= (mReserveIsaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
- (UINT64) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
+ Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
+ Attributes |= (mReserveIsaAliases ? (UINT64)EFI_PCI_IO_ATTRIBUTE_ISA_IO : \
+ (UINT64)EFI_PCI_IO_ATTRIBUTE_ISA_IO_16);
}
if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
@@ -1073,7 +1062,6 @@ PciSetDeviceAttribute ( EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
}
} else {
-
if (IS_PCI_IDE (&PciIoDevice->Pci)) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO;
Attributes |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO;
@@ -1081,16 +1069,15 @@ PciSetDeviceAttribute ( if (IS_PCI_VGA (&PciIoDevice->Pci)) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
- Attributes |= (mReserveVgaAliases ? (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
- (UINT64) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
+ Attributes |= (mReserveVgaAliases ? (UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO : \
+ (UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);
}
}
- PciIoDevice->Supports = Attributes;
- PciIoDevice->Supports &= ( (PciIoDevice->Parent->Supports) | \
- EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | \
- EFI_PCI_IO_ATTRIBUTE_BUS_MASTER );
-
+ PciIoDevice->Supports = Attributes;
+ PciIoDevice->Supports &= ((PciIoDevice->Parent->Supports) | \
+ EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | \
+ EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
} else {
//
// When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
@@ -1101,6 +1088,7 @@ PciSetDeviceAttribute ( if (!PciIoDevice->EmbeddedRom) {
Attributes |= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM;
}
+
PciIoDevice->Attributes = Attributes;
}
}
@@ -1117,19 +1105,19 @@ PciSetDeviceAttribute ( **/
EFI_STATUS
GetFastBackToBackSupport (
- IN PCI_IO_DEVICE *PciIoDevice,
- IN UINT8 StatusIndex
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN UINT8 StatusIndex
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_STATUS Status;
- UINT32 StatusRegister;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_STATUS Status;
+ UINT32 StatusRegister;
//
// Read the status register
//
- PciIo = &PciIoDevice->PciIo;
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
+ PciIo = &PciIoDevice->PciIo;
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
@@ -1153,18 +1141,17 @@ GetFastBackToBackSupport ( **/
VOID
ProcessOptionRomLight (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
//
// For RootBridge, PPB , P2C, go recursively to traverse all its children
//
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (!IsListEmpty (&Temp->ChildList)) {
@@ -1185,17 +1172,17 @@ ProcessOptionRomLight ( **/
EFI_STATUS
DetermineDeviceAttribute (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- UINT16 Command;
- UINT16 BridgeControl;
- UINT16 OldCommand;
- UINT16 OldBridgeControl;
- BOOLEAN FastB2BSupport;
- PCI_IO_DEVICE *Temp;
- LIST_ENTRY *CurrentLink;
- EFI_STATUS Status;
+ UINT16 Command;
+ UINT16 BridgeControl;
+ UINT16 OldCommand;
+ UINT16 OldBridgeControl;
+ BOOLEAN FastB2BSupport;
+ PCI_IO_DEVICE *Temp;
+ LIST_ENTRY *CurrentLink;
+ EFI_STATUS Status;
//
// For Root Bridge, just copy it by RootBridgeIo protocol
@@ -1203,22 +1190,21 @@ DetermineDeviceAttribute ( //
if (PciIoDevice->Parent == NULL) {
Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
- PciIoDevice->PciRootBridgeIo,
- &PciIoDevice->Supports,
- &PciIoDevice->Attributes
- );
+ PciIoDevice->PciRootBridgeIo,
+ &PciIoDevice->Supports,
+ &PciIoDevice->Attributes
+ );
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Assume the PCI Root Bridge supports DAC
//
PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
- EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
-
+ EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
} else {
-
//
// Set the attributes to be checked for common PCI devices and PPB or P2C
// Since some devices only support part of them, it is better to set the
@@ -1268,12 +1254,12 @@ DetermineDeviceAttribute ( //
CurrentLink = PciIoDevice->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {
-
- Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
- Status = DetermineDeviceAttribute (Temp);
+ Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
+ Status = DetermineDeviceAttribute (Temp);
if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Detect Fast Back to Back support for the device under the bridge
//
@@ -1284,13 +1270,12 @@ DetermineDeviceAttribute ( CurrentLink = CurrentLink->ForwardLink;
}
+
//
// Set or clear Fast Back to Back bit for the whole bridge
//
if (!IsListEmpty (&PciIoDevice->ChildList)) {
-
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
-
Status = GetFastBackToBackSupport (PciIoDevice, PCI_BRIDGE_STATUS_REGISTER_OFFSET);
if (EFI_ERROR (Status) || (!FastB2BSupport)) {
@@ -1313,6 +1298,7 @@ DetermineDeviceAttribute ( CurrentLink = CurrentLink->ForwardLink;
}
}
+
//
// End for IsListEmpty
//
@@ -1331,14 +1317,14 @@ DetermineDeviceAttribute ( **/
EFI_STATUS
UpdatePciInfo (
- IN OUT PCI_IO_DEVICE *PciIoDevice
+ IN OUT PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_STATUS Status;
- UINTN BarIndex;
- BOOLEAN SetFlag;
- VOID *Configuration;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ EFI_STATUS Status;
+ UINTN BarIndex;
+ BOOLEAN SetFlag;
+ VOID *Configuration;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
Configuration = NULL;
Status = EFI_SUCCESS;
@@ -1351,37 +1337,36 @@ UpdatePciInfo ( Status = gBS->LocateProtocol (
&gEfiIncompatiblePciDeviceSupportProtocolGuid,
NULL,
- (VOID **) &gIncompatiblePciDeviceSupport
+ (VOID **)&gIncompatiblePciDeviceSupport
);
}
- if (Status == EFI_SUCCESS) {
- //
- // Check whether the device belongs to incompatible devices from protocol or not
- // If it is , then get its special requirement in the ACPI table
- //
- Status = gIncompatiblePciDeviceSupport->CheckDevice (
- gIncompatiblePciDeviceSupport,
- PciIoDevice->Pci.Hdr.VendorId,
- PciIoDevice->Pci.Hdr.DeviceId,
- PciIoDevice->Pci.Hdr.RevisionID,
- PciIoDevice->Pci.Device.SubsystemVendorID,
- PciIoDevice->Pci.Device.SubsystemID,
- &Configuration
- );
+ if (Status == EFI_SUCCESS) {
+ //
+ // Check whether the device belongs to incompatible devices from protocol or not
+ // If it is , then get its special requirement in the ACPI table
+ //
+ Status = gIncompatiblePciDeviceSupport->CheckDevice (
+ gIncompatiblePciDeviceSupport,
+ PciIoDevice->Pci.Hdr.VendorId,
+ PciIoDevice->Pci.Hdr.DeviceId,
+ PciIoDevice->Pci.Hdr.RevisionID,
+ PciIoDevice->Pci.Device.SubsystemVendorID,
+ PciIoDevice->Pci.Device.SubsystemID,
+ &Configuration
+ );
}
- if (EFI_ERROR (Status) || Configuration == NULL ) {
+ if (EFI_ERROR (Status) || (Configuration == NULL)) {
return EFI_UNSUPPORTED;
}
//
// Update PCI device information from the ACPI table
//
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
while (Ptr->Desc != ACPI_END_TAG_DESCRIPTOR) {
-
if (Ptr->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
//
// The format is not support
@@ -1393,7 +1378,8 @@ UpdatePciInfo ( if ((Ptr->AddrTranslationOffset != MAX_UINT64) &&
(Ptr->AddrTranslationOffset != MAX_UINT8) &&
(Ptr->AddrTranslationOffset != BarIndex)
- ) {
+ )
+ {
//
// Skip updating when AddrTranslationOffset is not MAX_UINT64 or MAX_UINT8 (wide match).
// Skip updating when current BarIndex doesn't equal to AddrTranslationOffset.
@@ -1404,61 +1390,62 @@ UpdatePciInfo ( SetFlag = FALSE;
switch (Ptr->ResType) {
- case ACPI_ADDRESS_SPACE_TYPE_MEM:
-
- //
- // Make sure the bar is memory type
- //
- if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeMem)) {
- SetFlag = TRUE;
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:
//
- // Ignored if granularity is 0.
- // Ignored if PCI BAR is I/O or 32-bit memory.
- // If PCI BAR is 64-bit memory and granularity is 32, then
- // the PCI BAR resource is allocated below 4GB.
- // If PCI BAR is 64-bit memory and granularity is 64, then
- // the PCI BAR resource is allocated above 4GB.
+ // Make sure the bar is memory type
//
- if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeMem64) {
- switch (Ptr->AddrSpaceGranularity) {
- case 32:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
- case 64:
- PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
- break;
- default:
- break;
+ if (CheckBarType (PciIoDevice, (UINT8)BarIndex, PciBarTypeMem)) {
+ SetFlag = TRUE;
+
+ //
+ // Ignored if granularity is 0.
+ // Ignored if PCI BAR is I/O or 32-bit memory.
+ // If PCI BAR is 64-bit memory and granularity is 32, then
+ // the PCI BAR resource is allocated below 4GB.
+ // If PCI BAR is 64-bit memory and granularity is 64, then
+ // the PCI BAR resource is allocated above 4GB.
+ //
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
}
- }
- if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypePMem64) {
- switch (Ptr->AddrSpaceGranularity) {
- case 32:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
- case 64:
- PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
- break;
- default:
- break;
+ if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypePMem64) {
+ switch (Ptr->AddrSpaceGranularity) {
+ case 32:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+ case 64:
+ PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
+ break;
+ default:
+ break;
+ }
}
}
- }
- break;
- case ACPI_ADDRESS_SPACE_TYPE_IO:
+ break;
- //
- // Make sure the bar is IO type
- //
- if (CheckBarType (PciIoDevice, (UINT8) BarIndex, PciBarTypeIo)) {
- SetFlag = TRUE;
- }
- break;
+ case ACPI_ADDRESS_SPACE_TYPE_IO:
+
+ //
+ // Make sure the bar is IO type
+ //
+ if (CheckBarType (PciIoDevice, (UINT8)BarIndex, PciBarTypeIo)) {
+ SetFlag = TRUE;
+ }
+
+ break;
}
if (SetFlag) {
-
//
// Update the new alignment for the device
//
@@ -1492,8 +1479,8 @@ UpdatePciInfo ( **/
VOID
SetNewAlign (
- IN OUT UINT64 *Alignment,
- IN UINT64 NewAlignment
+ IN OUT UINT64 *Alignment,
+ IN UINT64 NewAlignment
)
{
UINT64 OldAlignment;
@@ -1504,27 +1491,29 @@ SetNewAlign ( // so skip it
//
if ((NewAlignment == 0) || (NewAlignment == OLD_ALIGN)) {
- return ;
+ return;
}
+
//
// Check the validity of the parameter
//
- if (NewAlignment != EVEN_ALIGN &&
- NewAlignment != SQUAD_ALIGN &&
- NewAlignment != DQUAD_ALIGN ) {
+ if ((NewAlignment != EVEN_ALIGN) &&
+ (NewAlignment != SQUAD_ALIGN) &&
+ (NewAlignment != DQUAD_ALIGN))
+ {
*Alignment = NewAlignment;
- return ;
+ return;
}
- OldAlignment = (*Alignment) + 1;
- ShiftBit = 0;
+ OldAlignment = (*Alignment) + 1;
+ ShiftBit = 0;
//
// Get the first non-zero hex value of the length
//
while ((OldAlignment & 0x0F) == 0x00) {
OldAlignment = RShiftU64 (OldAlignment, 4);
- ShiftBit += 4;
+ ShiftBit += 4;
}
//
@@ -1547,10 +1536,10 @@ SetNewAlign ( //
// Update the old value
//
- NewAlignment = LShiftU64 (OldAlignment, ShiftBit) - 1;
- *Alignment = NewAlignment;
+ NewAlignment = LShiftU64 (OldAlignment, ShiftBit) - 1;
+ *Alignment = NewAlignment;
- return ;
+ return;
}
/**
@@ -1587,11 +1576,11 @@ PciIovParseVfBar ( Value = 0;
Status = VfBarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
if (EFI_ERROR (Status)) {
PciIoDevice->VfPciBar[BarIndex].BaseAddress = 0;
@@ -1601,133 +1590,130 @@ PciIovParseVfBar ( //
// Scan all the BARs anyway
//
- PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
+ PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16)Offset;
return Offset + 4;
}
- PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16) Offset;
+ PciIoDevice->VfPciBar[BarIndex].Offset = (UINT16)Offset;
if ((Value & 0x01) != 0) {
//
// Device I/Os. Impossible
//
ASSERT (FALSE);
return Offset + 4;
-
} else {
-
- Mask = 0xfffffff0;
+ Mask = 0xfffffff0;
PciIoDevice->VfPciBar[BarIndex].BaseAddress = OriginalValue & Mask;
switch (Value & 0x07) {
+ //
+ // memory space; anywhere in 32 bit address space
+ //
+ case 0x00:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem32;
+ } else {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem32;
+ }
- //
- //memory space; anywhere in 32 bit address space
- //
- case 0x00:
- if ((Value & 0x08) != 0) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem32;
- } else {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem32;
- }
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+
+ //
+ // Adjust Length
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ //
+ // Adjust Alignment
+ //
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ break;
//
- // Adjust Length
- //
- PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ // memory space; anywhere in 64 bit address space
//
- // Adjust Alignment
- //
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ case 0x04:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem64;
+ } else {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem64;
+ }
- break;
+ //
+ // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
+ // is regarded as an extension for the first bar. As a result
+ // the sizing will be conducted on combined 64 bit value
+ // Here just store the masked first 32bit value for future size
+ // calculation
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = Value & Mask;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // memory space; anywhere in 64 bit address space
- //
- case 0x04:
- if ((Value & 0x08) != 0) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypePMem64;
- } else {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeMem64;
- }
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- //
- // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
- // is regarded as an extension for the first bar. As a result
- // the sizing will be conducted on combined 64 bit value
- // Here just store the masked first 32bit value for future size
- // calculation
- //
- PciIoDevice->VfPciBar[BarIndex].Length = Value & Mask;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ //
+ // Increment the offset to point to next DWORD
+ //
+ Offset += 4;
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ Status = VfBarExisted (
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
- //
- // Increment the offset to point to next DWORD
- //
- Offset += 4;
+ if (EFI_ERROR (Status)) {
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
+ return Offset + 4;
+ }
- Status = VfBarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ //
+ // Fix the length to support some special 64 bit BAR
+ //
+ Value |= ((UINT32)-1 << HighBitSet32 (Value));
- if (EFI_ERROR (Status)) {
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
- return Offset + 4;
- }
+ //
+ // Calculate the size of 64bit bar
+ //
+ PciIoDevice->VfPciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64)OriginalValue, 32);
- //
- // Fix the length to support some special 64 bit BAR
- //
- Value |= ((UINT32) -1 << HighBitSet32 (Value));
+ PciIoDevice->VfPciBar[BarIndex].Length = PciIoDevice->VfPciBar[BarIndex].Length | LShiftU64 ((UINT64)Value, 32);
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(PciIoDevice->VfPciBar[BarIndex].Length)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // Calculate the size of 64bit bar
- //
- PciIoDevice->VfPciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
+ //
+ // Adjust Length
+ //
+ PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
+ //
+ // Adjust Alignment
+ //
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- PciIoDevice->VfPciBar[BarIndex].Length = PciIoDevice->VfPciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
- PciIoDevice->VfPciBar[BarIndex].Length = (~(PciIoDevice->VfPciBar[BarIndex].Length)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
+ break;
//
- // Adjust Length
- //
- PciIoDevice->VfPciBar[BarIndex].Length = MultU64x32 (PciIoDevice->VfPciBar[BarIndex].Length, PciIoDevice->InitialVFs);
- //
- // Adjust Alignment
+ // reserved
//
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
-
- break;
+ default:
+ PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
+ PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
- //
- // reserved
- //
- default:
- PciIoDevice->VfPciBar[BarIndex].BarType = PciBarTypeUnknown;
- PciIoDevice->VfPciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->VfPciBar[BarIndex].Length - 1;
-
- if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
- PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
- }
+ if (PciIoDevice->VfPciBar[BarIndex].Alignment < PciIoDevice->SystemPageSize - 1) {
+ PciIoDevice->VfPciBar[BarIndex].Alignment = PciIoDevice->SystemPageSize - 1;
+ }
- break;
+ break;
}
}
@@ -1786,12 +1772,12 @@ PciParseBar ( //
// Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
//
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
+ PciIoDevice->PciBar[BarIndex].Offset = (UINT8)Offset;
return Offset + 4;
}
PciIoDevice->PciBar[BarIndex].BarTypeFixed = FALSE;
- PciIoDevice->PciBar[BarIndex].Offset = (UINT8) Offset;
+ PciIoDevice->PciBar[BarIndex].Offset = (UINT8)Offset;
if ((Value & 0x01) != 0) {
//
// Device I/Os
@@ -1805,7 +1791,6 @@ PciParseBar ( PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo32;
PciIoDevice->PciBar[BarIndex].Length = ((~(Value & Mask)) + 1);
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
-
} else {
//
// It is a IO16 bar
@@ -1813,135 +1798,134 @@ PciParseBar ( PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeIo16;
PciIoDevice->PciBar[BarIndex].Length = 0x0000FFFF & ((~(Value & Mask)) + 1);
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
-
}
+
//
// Workaround. Some platforms implement IO bar with 0 length
// Need to treat it as no-bar
//
if (PciIoDevice->PciBar[BarIndex].Length == 0) {
- PciIoDevice->PciBar[BarIndex].BarType = (PCI_BAR_TYPE) 0;
+ PciIoDevice->PciBar[BarIndex].BarType = (PCI_BAR_TYPE)0;
}
- PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
-
+ PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
} else {
-
- Mask = 0xfffffff0;
+ Mask = 0xfffffff0;
PciIoDevice->PciBar[BarIndex].BaseAddress = OriginalValue & Mask;
switch (Value & 0x07) {
+ //
+ // memory space; anywhere in 32 bit address space
+ //
+ case 0x00:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+ } else {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+ }
- //
- //memory space; anywhere in 32 bit address space
- //
- case 0x00:
- if ((Value & 0x08) != 0) {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
- } else {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
- }
+ PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
+ //
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ //
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ }
+
+ break;
+
+ //
+ // memory space; anywhere in 64 bit address space
+ //
+ case 0x04:
+ if ((Value & 0x08) != 0) {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
+ } else {
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
+ }
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
//
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
+ // is regarded as an extension for the first bar. As a result
+ // the sizing will be conducted on combined 64 bit value
+ // Here just store the masked first 32bit value for future size
+ // calculation
//
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
+ PciIoDevice->PciBar[BarIndex].Length = Value & Mask;
PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
- break;
- //
- // memory space; anywhere in 64 bit address space
- //
- case 0x04:
- if ((Value & 0x08) != 0) {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem64;
- } else {
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem64;
- }
+ //
+ // Increment the offset to point to next DWORD
+ //
+ Offset += 4;
- //
- // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
- // is regarded as an extension for the first bar. As a result
- // the sizing will be conducted on combined 64 bit value
- // Here just store the masked first 32bit value for future size
- // calculation
- //
- PciIoDevice->PciBar[BarIndex].Length = Value & Mask;
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ Status = BarExisted (
+ PciIoDevice,
+ Offset,
+ &Value,
+ &OriginalValue
+ );
- //
- // Increment the offset to point to next DWORD
- //
- Offset += 4;
+ if (EFI_ERROR (Status)) {
+ //
+ // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
+ //
+ if (PciIoDevice->PciBar[BarIndex].Length == 0) {
+ //
+ // some device implement MMIO bar with 0 length, need to treat it as no-bar
+ //
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
+ return Offset + 4;
+ }
+ }
- Status = BarExisted (
- PciIoDevice,
- Offset,
- &Value,
- &OriginalValue
- );
+ //
+ // Fix the length to support some special 64 bit BAR
+ //
+ if (Value == 0) {
+ DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
+ Value = (UINT32)-1;
+ } else {
+ Value |= ((UINT32)(-1) << HighBitSet32 (Value));
+ }
- if (EFI_ERROR (Status)) {
//
- // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
+ // Calculate the size of 64bit bar
//
- if (PciIoDevice->PciBar[BarIndex].Length == 0) {
+ PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64)OriginalValue, 32);
+
+ PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64)Value, 32);
+ PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
//
- // some device implement MMIO bar with 0 length, need to treat it as no-bar
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
//
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
- return Offset + 4;
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
}
- }
- //
- // Fix the length to support some special 64 bit BAR
- //
- if (Value == 0) {
- DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
- Value = (UINT32) -1;
- } else {
- Value |= ((UINT32)(-1) << HighBitSet32 (Value));
- }
+ break;
//
- // Calculate the size of 64bit bar
+ // reserved
//
- PciIoDevice->PciBar[BarIndex].BaseAddress |= LShiftU64 ((UINT64) OriginalValue, 32);
-
- PciIoDevice->PciBar[BarIndex].Length = PciIoDevice->PciBar[BarIndex].Length | LShiftU64 ((UINT64) Value, 32);
- PciIoDevice->PciBar[BarIndex].Length = (~(PciIoDevice->PciBar[BarIndex].Length)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
- //
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
- //
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
-
- break;
+ default:
+ PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
+ PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
+ if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
+ //
+ // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
+ //
+ PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
+ } else {
+ PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
+ }
- //
- // reserved
- //
- default:
- PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeUnknown;
- PciIoDevice->PciBar[BarIndex].Length = (~(Value & Mask)) + 1;
- if (PciIoDevice->PciBar[BarIndex].Length < (SIZE_4KB)) {
- //
- // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
- //
- PciIoDevice->PciBar[BarIndex].Alignment = (SIZE_4KB - 1);
- } else {
- PciIoDevice->PciBar[BarIndex].Alignment = PciIoDevice->PciBar[BarIndex].Length - 1;
- }
- break;
+ break;
}
}
@@ -1970,11 +1954,11 @@ PciParseBar ( **/
VOID
InitializePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT8 Offset;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Offset;
PciIo = &(PciIoDevice->PciIo);
@@ -1996,10 +1980,10 @@ InitializePciDevice ( **/
VOID
InitializePpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &(PciIoDevice->PciIo);
@@ -2040,10 +2024,10 @@ InitializePpb ( **/
VOID
InitializeP2C (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_PCI_IO_PROTOCOL *PciIo;
PciIo = &(PciIoDevice->PciIo);
@@ -2081,7 +2065,7 @@ InitializeP2C ( **/
EFI_STATUS
AuthenticatePciDevice (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
EDKII_DEVICE_IDENTIFIER DeviceIdentifier;
@@ -2094,15 +2078,15 @@ AuthenticatePciDevice ( DeviceIdentifier.Version = EDKII_DEVICE_IDENTIFIER_REVISION;
CopyGuid (&DeviceIdentifier.DeviceType, &gEdkiiDeviceIdentifierTypePciGuid);
DeviceIdentifier.DeviceHandle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces (
- &DeviceIdentifier.DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- PciIoDevice->DevicePath,
- &gEdkiiDeviceIdentifierTypePciGuid,
- &PciIoDevice->PciIo,
- NULL
- );
- if (EFI_ERROR(Status)) {
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &DeviceIdentifier.DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ PciIoDevice->DevicePath,
+ &gEdkiiDeviceIdentifierTypePciGuid,
+ &PciIoDevice->PciIo,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
return Status;
}
@@ -2115,13 +2099,13 @@ AuthenticatePciDevice ( // No need to check return Status.
//
gBS->UninstallMultipleProtocolInterfaces (
- DeviceIdentifier.DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- PciIoDevice->DevicePath,
- &gEdkiiDeviceIdentifierTypePciGuid,
- &PciIoDevice->PciIo,
- NULL
- );
+ DeviceIdentifier.DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ PciIoDevice->DevicePath,
+ &gEdkiiDeviceIdentifierTypePciGuid,
+ &PciIoDevice->PciIo,
+ NULL
+ );
return Status;
}
@@ -2146,11 +2130,11 @@ AuthenticatePciDevice ( **/
PCI_IO_DEVICE *
CreatePciIoDevice (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_TYPE00 *Pci,
- IN UINT8 Bus,
- IN UINT8 Device,
- IN UINT8 Func
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_TYPE00 *Pci,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Func
)
{
PCI_IO_DEVICE *PciIoDevice;
@@ -2162,14 +2146,14 @@ CreatePciIoDevice ( return NULL;
}
- PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
- PciIoDevice->Handle = NULL;
- PciIoDevice->PciRootBridgeIo = Bridge->PciRootBridgeIo;
- PciIoDevice->DevicePath = NULL;
- PciIoDevice->BusNumber = Bus;
- PciIoDevice->DeviceNumber = Device;
- PciIoDevice->FunctionNumber = Func;
- PciIoDevice->Decodes = 0;
+ PciIoDevice->Signature = PCI_IO_DEVICE_SIGNATURE;
+ PciIoDevice->Handle = NULL;
+ PciIoDevice->PciRootBridgeIo = Bridge->PciRootBridgeIo;
+ PciIoDevice->DevicePath = NULL;
+ PciIoDevice->BusNumber = Bus;
+ PciIoDevice->DeviceNumber = Device;
+ PciIoDevice->FunctionNumber = Func;
+ PciIoDevice->Decodes = 0;
if (gFullEnumeration) {
PciIoDevice->Allocated = FALSE;
@@ -2177,13 +2161,13 @@ CreatePciIoDevice ( PciIoDevice->Allocated = TRUE;
}
- PciIoDevice->Registered = FALSE;
- PciIoDevice->Attributes = 0;
- PciIoDevice->Supports = 0;
- PciIoDevice->BusOverride = FALSE;
- PciIoDevice->AllOpRomProcessed = FALSE;
+ PciIoDevice->Registered = FALSE;
+ PciIoDevice->Attributes = 0;
+ PciIoDevice->Supports = 0;
+ PciIoDevice->BusOverride = FALSE;
+ PciIoDevice->AllOpRomProcessed = FALSE;
- PciIoDevice->IsPciExp = FALSE;
+ PciIoDevice->IsPciExp = FALSE;
CopyMem (&(PciIoDevice->Pci), Pci, sizeof (PCI_TYPE01));
@@ -2207,12 +2191,12 @@ CreatePciIoDevice ( // Detect if PCI Express Device
//
PciIoDevice->PciExpressCapabilityOffset = 0;
- Status = LocateCapabilityRegBlock (
- PciIoDevice,
- EFI_PCI_CAPABILITY_ID_PCIEXP,
- &PciIoDevice->PciExpressCapabilityOffset,
- NULL
- );
+ Status = LocateCapabilityRegBlock (
+ PciIoDevice,
+ EFI_PCI_CAPABILITY_ID_PCIEXP,
+ &PciIoDevice->PciExpressCapabilityOffset,
+ NULL
+ );
if (!EFI_ERROR (Status)) {
PciIoDevice->IsPciExp = TRUE;
}
@@ -2224,10 +2208,11 @@ CreatePciIoDevice ( //
// If authentication fails, skip this device.
//
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
if (PciIoDevice->DevicePath != NULL) {
FreePool (PciIoDevice->DevicePath);
}
+
FreePool (PciIoDevice);
return NULL;
}
@@ -2255,32 +2240,32 @@ CreatePciIoDevice ( //
ParentPciIo = &Bridge->PciIo;
ParentPciIo->Pci.Read (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET,
+ 1,
+ &Data32
+ );
if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
//
// ARI forward support in bridge, so enable it.
//
ParentPciIo->Pci.Read (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
+ 1,
+ &Data32
+ );
if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING) == 0) {
Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
ParentPciIo->Pci.Write (
- ParentPciIo,
- EfiPciIoWidthUint32,
- Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
- 1,
- &Data32
- );
+ ParentPciIo,
+ EfiPciIoWidthUint32,
+ Bridge->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET,
+ 1,
+ &Data32
+ );
DEBUG ((
DEBUG_INFO,
" ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
@@ -2307,17 +2292,17 @@ CreatePciIoDevice ( NULL
);
if (!EFI_ERROR (Status)) {
- UINT32 SupportedPageSize;
- UINT16 VFStride;
- UINT16 FirstVFOffset;
- UINT16 Data16;
- UINT32 PFRid;
- UINT32 LastVF;
+ UINT32 SupportedPageSize;
+ UINT16 VFStride;
+ UINT16 FirstVFOffset;
+ UINT16 Data16;
+ UINT32 PFRid;
+ UINT32 LastVF;
//
// If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
//
- if (PcdGetBool (PcdAriSupport) && PciIoDevice->AriCapabilityOffset != 0) {
+ if (PcdGetBool (PcdAriSupport) && (PciIoDevice->AriCapabilityOffset != 0)) {
PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -2392,7 +2377,7 @@ CreatePciIoDevice ( //
// Calculate LastVF
//
- PFRid = EFI_PCI_RID(Bus, Device, Func);
+ PFRid = EFI_PCI_RID (Bus, Device, Func);
LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
//
@@ -2403,12 +2388,16 @@ CreatePciIoDevice ( DEBUG ((
DEBUG_INFO,
" SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
- SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset
+ SupportedPageSize,
+ PciIoDevice->SystemPageSize >> 12,
+ FirstVFOffset
));
DEBUG ((
DEBUG_INFO,
" InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
- PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice->SrIovCapabilityOffset
+ PciIoDevice->InitialVFs,
+ PciIoDevice->ReservedBusNum,
+ PciIoDevice->SrIovCapabilityOffset
));
}
}
@@ -2434,17 +2423,17 @@ CreatePciIoDevice ( NULL
);
if (!EFI_ERROR (Status)) {
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
- UINT32 Offset;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
+ UINT32 Offset;
Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)
- + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),
+ + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),
PciIo->Pci.Read (
- PciIo,
- EfiPciIoWidthUint8,
- Offset,
- sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),
- &ResizableBarControl
- );
+ PciIo,
+ EfiPciIoWidthUint8,
+ Offset,
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),
+ &ResizableBarControl
+ );
PciIoDevice->ResizableBarNumber = ResizableBarControl.Bits.ResizableBarNumber;
PciProgramResizableBar (PciIoDevice, PciResizableBarMax);
}
@@ -2482,16 +2471,15 @@ CreatePciIoDevice ( **/
EFI_STATUS
PciEnumeratorLight (
- IN EFI_HANDLE Controller
+ IN EFI_HANDLE Controller
)
{
-
- EFI_STATUS Status;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
- PCI_IO_DEVICE *RootBridgeDev;
- UINT16 MinBus;
- UINT16 MaxBus;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ PCI_IO_DEVICE *RootBridgeDev;
+ UINT16 MinBus;
+ UINT16 MaxBus;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
MinBus = 0;
MaxBus = PCI_MAX_BUS;
@@ -2510,23 +2498,22 @@ PciEnumeratorLight ( Status = gBS->OpenProtocol (
Controller,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
+ Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **)&Descriptors);
if (EFI_ERROR (Status)) {
return Status;
}
while (PciGetBusRange (&Descriptors, &MinBus, &MaxBus, NULL) == EFI_SUCCESS) {
-
//
// Create a device node for root bridge device with a NULL host bridge controller handle
//
@@ -2544,11 +2531,10 @@ PciEnumeratorLight ( Status = PciPciDeviceInfoCollector (
RootBridgeDev,
- (UINT8) MinBus
+ (UINT8)MinBus
);
if (!EFI_ERROR (Status)) {
-
//
// Remove those PCI devices which are rejected when full enumeration
//
@@ -2569,7 +2555,6 @@ PciEnumeratorLight ( //
InsertRootBridge (RootBridgeDev);
} else {
-
//
// If unsuccessfully, destroy the entire node
//
@@ -2605,15 +2590,15 @@ PciGetBusRange ( while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
if (MinBus != NULL) {
- *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
+ *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;
}
if (MaxBus != NULL) {
- *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
+ *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;
}
if (BusRange != NULL) {
- *BusRange = (UINT16) (*Descriptors)->AddrLen;
+ *BusRange = (UINT16)(*Descriptors)->AddrLen;
}
return EFI_SUCCESS;
@@ -2636,12 +2621,12 @@ PciGetBusRange ( **/
EFI_STATUS
StartManagingRootBridge (
- IN PCI_IO_DEVICE *RootBridgeDev
+ IN PCI_IO_DEVICE *RootBridgeDev
)
{
- EFI_HANDLE RootBridgeHandle;
- EFI_STATUS Status;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_HANDLE RootBridgeHandle;
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
//
// Get the root bridge handle
@@ -2655,13 +2640,13 @@ StartManagingRootBridge ( Status = gBS->OpenProtocol (
RootBridgeHandle,
&gEfiPciRootBridgeIoProtocolGuid,
- (VOID **) &PciRootBridgeIo,
+ (VOID **)&PciRootBridgeIo,
gPciBusDriverBinding.DriverBindingHandle,
RootBridgeHandle,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
- if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
+ if (EFI_ERROR (Status) && (Status != EFI_ALREADY_STARTED)) {
return Status;
}
@@ -2671,7 +2656,6 @@ StartManagingRootBridge ( RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
return EFI_SUCCESS;
-
}
/**
@@ -2685,7 +2669,7 @@ StartManagingRootBridge ( **/
BOOLEAN
IsPciDeviceRejected (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
EFI_STATUS Status;
@@ -2706,9 +2690,8 @@ IsPciDeviceRejected ( // Only test base registers for P2C
//
for (BarOffset = 0x1C; BarOffset <= 0x38; BarOffset += 2 * sizeof (UINT32)) {
-
- Mask = (BarOffset < 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
- Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
+ Mask = (BarOffset < 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
+ Status = BarExisted (PciIoDevice, BarOffset, &TestValue, &OldValue);
if (EFI_ERROR (Status)) {
continue;
}
@@ -2735,7 +2718,6 @@ IsPciDeviceRejected ( }
if ((TestValue & 0x01) != 0) {
-
//
// IO Bar
//
@@ -2744,9 +2726,7 @@ IsPciDeviceRejected ( if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
return TRUE;
}
-
} else {
-
//
// Mem Bar
//
@@ -2754,13 +2734,11 @@ IsPciDeviceRejected ( TestValue = TestValue & Mask;
if ((TestValue & 0x07) == 0x04) {
-
//
// Mem64 or PMem64
//
BarOffset += sizeof (UINT32);
if ((TestValue != 0) && (TestValue == (OldValue & Mask))) {
-
//
// Test its high 32-Bit BAR
//
@@ -2769,9 +2747,7 @@ IsPciDeviceRejected ( return TRUE;
}
}
-
} else {
-
//
// Mem32 or PMem32
//
@@ -2794,24 +2770,23 @@ IsPciDeviceRejected ( **/
VOID
ResetAllPpbBusNumber (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT8 StartBusNumber
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT8 StartBusNumber
)
{
- EFI_STATUS Status;
- PCI_TYPE00 Pci;
- UINT8 Device;
- UINT32 Register;
- UINT8 Func;
- UINT64 Address;
- UINT8 SecondaryBus;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_STATUS Status;
+ PCI_TYPE00 Pci;
+ UINT8 Device;
+ UINT32 Register;
+ UINT8 Func;
+ UINT64 Address;
+ UINT8 SecondaryBus;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
PciRootBridgeIo = Bridge->PciRootBridgeIo;
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
-
//
// Check to see whether a pci device is present
//
@@ -2823,7 +2798,7 @@ ResetAllPpbBusNumber ( Func
);
- if (EFI_ERROR (Status) && Func == 0) {
+ if (EFI_ERROR (Status) && (Func == 0)) {
//
// go to next device if there is no Function 0
//
@@ -2831,16 +2806,15 @@ ResetAllPpbBusNumber ( }
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {
-
- Register = 0;
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
- Status = PciRootBridgeIo->Pci.Read (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- Address,
- 1,
- &Register
- );
+ Register = 0;
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
+ Status = PciRootBridgeIo->Pci.Read (
+ PciRootBridgeIo,
+ EfiPciWidthUint32,
+ Address,
+ 1,
+ &Register
+ );
SecondaryBus = (UINT8)(Register >> 8);
if (SecondaryBus != 0) {
@@ -2851,16 +2825,16 @@ ResetAllPpbBusNumber ( // Reset register 18h, 19h, 1Ah on PCI Bridge
//
Register &= 0xFF000000;
- Status = PciRootBridgeIo->Pci.Write (
- PciRootBridgeIo,
- EfiPciWidthUint32,
- Address,
- 1,
- &Register
- );
+ Status = PciRootBridgeIo->Pci.Write (
+ PciRootBridgeIo,
+ EfiPciWidthUint32,
+ Address,
+ 1,
+ &Register
+ );
}
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
+ if ((Func == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
|