diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 1519 |
1 files changed, 751 insertions, 768 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 4969ee0f64..8ffd05f327 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -11,9 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// The default policy for the PCI bus driver is NOT to reserve I/O ranges for both ISA aliases and VGA aliases.
//
-BOOLEAN mReserveIsaAliases = FALSE;
-BOOLEAN mReserveVgaAliases = FALSE;
-BOOLEAN mPolicyDetermined = FALSE;
+BOOLEAN mReserveIsaAliases = FALSE;
+BOOLEAN mReserveVgaAliases = FALSE;
+BOOLEAN mPolicyDetermined = FALSE;
/**
The function is used to skip VGA range.
@@ -24,8 +24,8 @@ BOOLEAN mPolicyDetermined = FALSE; **/
VOID
SkipVGAAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
)
{
UINT64 Original;
@@ -37,7 +37,7 @@ SkipVGAAperture ( //
// For legacy VGA, bit 10 to bit 15 is not decoded
//
- Mask = 0x3FF;
+ Mask = 0x3FF;
Original = *Start;
StartOffset = Original & Mask;
@@ -56,11 +56,10 @@ SkipVGAAperture ( **/
VOID
SkipIsaAliasAperture (
- OUT UINT64 *Start,
- IN UINT64 Length
+ OUT UINT64 *Start,
+ IN UINT64 Length
)
{
-
UINT64 Original;
UINT64 Mask;
UINT64 StartOffset;
@@ -71,7 +70,7 @@ SkipIsaAliasAperture ( //
// For legacy ISA, bit 10 to bit 15 is not decoded
//
- Mask = 0x3FF;
+ Mask = 0x3FF;
Original = *Start;
StartOffset = Original & Mask;
@@ -92,14 +91,14 @@ SkipIsaAliasAperture ( **/
VOID
InsertResourceNode (
- IN OUT PCI_RESOURCE_NODE *Bridge,
- IN PCI_RESOURCE_NODE *ResNode
+ IN OUT PCI_RESOURCE_NODE *Bridge,
+ IN PCI_RESOURCE_NODE *ResNode
)
{
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Temp;
- UINT64 ResNodeAlignRest;
- UINT64 TempAlignRest;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
+ UINT64 ResNodeAlignRest;
+ UINT64 TempAlignRest;
ASSERT (Bridge != NULL);
ASSERT (ResNode != NULL);
@@ -113,8 +112,8 @@ InsertResourceNode ( if (ResNode->Alignment > Temp->Alignment) {
break;
} else if (ResNode->Alignment == Temp->Alignment) {
- ResNodeAlignRest = ResNode->Length & ResNode->Alignment;
- TempAlignRest = Temp->Length & Temp->Alignment;
+ ResNodeAlignRest = ResNode->Length & ResNode->Alignment;
+ TempAlignRest = Temp->Length & Temp->Alignment;
if ((ResNodeAlignRest == 0) || (ResNodeAlignRest >= TempAlignRest)) {
break;
}
@@ -146,14 +145,13 @@ InsertResourceNode ( **/
VOID
MergeResourceTree (
- IN PCI_RESOURCE_NODE *Dst,
- IN PCI_RESOURCE_NODE *Res,
- IN BOOLEAN TypeMerge
+ IN PCI_RESOURCE_NODE *Dst,
+ IN PCI_RESOURCE_NODE *Res,
+ IN BOOLEAN TypeMerge
)
{
-
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Temp;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
ASSERT (Dst != NULL);
ASSERT (Res != NULL);
@@ -161,7 +159,7 @@ MergeResourceTree ( while (!IsListEmpty (&Res->ChildList)) {
CurrentLink = Res->ChildList.ForwardLink;
- Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
+ Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (TypeMerge) {
Temp->ResType = Dst->ResType;
@@ -181,22 +179,22 @@ MergeResourceTree ( **/
VOID
CalculateApertureIo16 (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- EFI_STATUS Status;
- UINT64 Aperture;
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
- UINT64 Offset;
- EFI_PCI_PLATFORM_POLICY PciPolicy;
- UINT64 PaddingAperture;
+ EFI_STATUS Status;
+ UINT64 Aperture;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
+ UINT64 Offset;
+ EFI_PCI_PLATFORM_POLICY PciPolicy;
+ UINT64 PaddingAperture;
if (!mPolicyDetermined) {
//
// Check PciPlatform policy
//
- Status = EFI_NOT_FOUND;
+ Status = EFI_NOT_FOUND;
PciPolicy = 0;
if (gPciPlatformProtocol != NULL) {
Status = gPciPlatformProtocol->GetPlatformPolicy (
@@ -205,7 +203,7 @@ CalculateApertureIo16 ( );
}
- if (EFI_ERROR (Status) && gPciOverrideProtocol != NULL) {
+ if (EFI_ERROR (Status) && (gPciOverrideProtocol != NULL)) {
Status = gPciOverrideProtocol->GetPlatformPolicy (
gPciOverrideProtocol,
&PciPolicy
@@ -216,10 +214,12 @@ CalculateApertureIo16 ( if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {
mReserveIsaAliases = TRUE;
}
+
if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {
mReserveVgaAliases = TRUE;
}
}
+
mPolicyDetermined = TRUE;
}
@@ -227,32 +227,31 @@ CalculateApertureIo16 ( PaddingAperture = 0;
if (Bridge == NULL) {
- return ;
+ return;
}
//
// Assume the bridge is aligned
//
for ( CurrentLink = GetFirstNode (&Bridge->ChildList)
- ; !IsNull (&Bridge->ChildList, CurrentLink)
- ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
- ) {
-
+ ; !IsNull (&Bridge->ChildList, CurrentLink)
+ ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
+ )
+ {
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (Node->ResourceUsage == PciResUsagePadding) {
ASSERT (PaddingAperture == 0);
PaddingAperture = Node->Length;
continue;
}
+
//
// Consider the aperture alignment
//
Offset = Aperture & (Node->Alignment);
if (Offset != 0) {
-
Aperture = Aperture + (Node->Alignment + 1) - Offset;
-
}
//
@@ -334,21 +333,20 @@ CalculateApertureIo16 ( **/
VOID
CalculateResourceAperture (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- UINT64 Aperture[2];
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
+ UINT64 Aperture[2];
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
if (Bridge == NULL) {
- return ;
+ return;
}
if (Bridge->ResType == PciBarTypeIo16) {
-
CalculateApertureIo16 (Bridge);
- return ;
+ return;
}
Aperture[PciResUsageTypical] = 0;
@@ -357,17 +355,20 @@ CalculateResourceAperture ( // Assume the bridge is aligned
//
for ( CurrentLink = GetFirstNode (&Bridge->ChildList)
- ; !IsNull (&Bridge->ChildList, CurrentLink)
- ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
- ) {
+ ; !IsNull (&Bridge->ChildList, CurrentLink)
+ ; CurrentLink = GetNextNode (&Bridge->ChildList, CurrentLink)
+ )
+ {
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
//
// It's possible for a bridge to contain multiple padding resource
// nodes due to DegradeResource().
//
- ASSERT ((Node->ResourceUsage == PciResUsageTypical) ||
- (Node->ResourceUsage == PciResUsagePadding));
+ ASSERT (
+ (Node->ResourceUsage == PciResUsageTypical) ||
+ (Node->ResourceUsage == PciResUsagePadding)
+ );
ASSERT (Node->ResourceUsage < ARRAY_SIZE (Aperture));
//
// Recode current aperture as a offset
@@ -419,126 +420,123 @@ CalculateResourceAperture ( **/
VOID
GetResourceFromDevice (
- IN PCI_IO_DEVICE *PciDev,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
-
- UINT8 Index;
- PCI_RESOURCE_NODE *Node;
- BOOLEAN ResourceRequested;
+ UINT8 Index;
+ PCI_RESOURCE_NODE *Node;
+ BOOLEAN ResourceRequested;
Node = NULL;
ResourceRequested = FALSE;
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
-
switch ((PciDev->PciBar)[Index].BarType) {
+ case PciBarTypeMem32:
+ case PciBarTypeOpRom:
- case PciBarTypeMem32:
- case PciBarTypeOpRom:
-
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- (PciDev->PciBar)[Index].BarType,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ (PciDev->PciBar)[Index].BarType,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem32Node,
- Node
- );
+ InsertResourceNode (
+ Mem32Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeMem64:
+ case PciBarTypeMem64:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypeMem64,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem64Node,
- Node
- );
+ InsertResourceNode (
+ Mem64Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypePMem64:
+ case PciBarTypePMem64:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypePMem64,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem64Node,
- Node
- );
+ InsertResourceNode (
+ PMem64Node,
+ Node
+ );
- ResourceRequested = TRUE;
- break;
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypePMem32:
+ case PciBarTypePMem32:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypePMem32,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem32Node,
- Node
- );
- ResourceRequested = TRUE;
- break;
+ InsertResourceNode (
+ PMem32Node,
+ Node
+ );
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
- Node = CreateResourceNode (
- PciDev,
- (PciDev->PciBar)[Index].Length,
- (PciDev->PciBar)[Index].Alignment,
- Index,
- PciBarTypeIo16,
- PciResUsageTypical
- );
+ Node = CreateResourceNode (
+ PciDev,
+ (PciDev->PciBar)[Index].Length,
+ (PciDev->PciBar)[Index].Alignment,
+ Index,
+ PciBarTypeIo16,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- IoNode,
- Node
- );
- ResourceRequested = TRUE;
- break;
+ InsertResourceNode (
+ IoNode,
+ Node
+ );
+ ResourceRequested = TRUE;
+ break;
- case PciBarTypeUnknown:
- break;
+ case PciBarTypeUnknown:
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -546,91 +544,90 @@ GetResourceFromDevice ( // Add VF resource
//
for (Index = 0; Index < PCI_MAX_BAR; Index++) {
-
switch ((PciDev->VfPciBar)[Index].BarType) {
+ case PciBarTypeMem32:
- case PciBarTypeMem32:
-
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypeMem32,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem32Node,
- Node
- );
+ InsertResourceNode (
+ Mem32Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypeMem64:
+ case PciBarTypeMem64:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypeMem64,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypeMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- Mem64Node,
- Node
- );
+ InsertResourceNode (
+ Mem64Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypePMem64:
+ case PciBarTypePMem64:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypePMem64,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem64,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem64Node,
- Node
- );
+ InsertResourceNode (
+ PMem64Node,
+ Node
+ );
- break;
+ break;
- case PciBarTypePMem32:
+ case PciBarTypePMem32:
- Node = CreateVfResourceNode (
- PciDev,
- (PciDev->VfPciBar)[Index].Length,
- (PciDev->VfPciBar)[Index].Alignment,
- Index,
- PciBarTypePMem32,
- PciResUsageTypical
- );
+ Node = CreateVfResourceNode (
+ PciDev,
+ (PciDev->VfPciBar)[Index].Length,
+ (PciDev->VfPciBar)[Index].Alignment,
+ Index,
+ PciBarTypePMem32,
+ PciResUsageTypical
+ );
- InsertResourceNode (
- PMem32Node,
- Node
- );
- break;
+ InsertResourceNode (
+ PMem32Node,
+ Node
+ );
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- break;
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ break;
- case PciBarTypeUnknown:
- break;
+ case PciBarTypeUnknown:
+ break;
- default:
- break;
+ default:
+ break;
}
}
+
// If there is no resource requested from this device,
// then we indicate this device has been allocated naturally.
//
@@ -655,19 +652,19 @@ GetResourceFromDevice ( **/
PCI_RESOURCE_NODE *
CreateResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
- Node = NULL;
+ Node = NULL;
- Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
+ Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));
ASSERT (Node != NULL);
if (Node == NULL) {
return NULL;
@@ -702,15 +699,15 @@ CreateResourceNode ( **/
PCI_RESOURCE_NODE *
CreateVfResourceNode (
- IN PCI_IO_DEVICE *PciDev,
- IN UINT64 Length,
- IN UINT64 Alignment,
- IN UINT8 Bar,
- IN PCI_BAR_TYPE ResType,
- IN PCI_RESOURCE_USAGE ResUsage
+ IN PCI_IO_DEVICE *PciDev,
+ IN UINT64 Length,
+ IN UINT64 Alignment,
+ IN UINT8 Bar,
+ IN PCI_BAR_TYPE ResType,
+ IN PCI_RESOURCE_USAGE ResUsage
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
Node = CreateResourceNode (PciDev, Length, Alignment, Bar, ResType, ResUsage);
if (Node == NULL) {
@@ -736,26 +733,25 @@ CreateVfResourceNode ( **/
VOID
CreateResourceMap (
- IN PCI_IO_DEVICE *Bridge,
- IN OUT PCI_RESOURCE_NODE *IoNode,
- IN OUT PCI_RESOURCE_NODE *Mem32Node,
- IN OUT PCI_RESOURCE_NODE *PMem32Node,
- IN OUT PCI_RESOURCE_NODE *Mem64Node,
- IN OUT PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN OUT PCI_RESOURCE_NODE *IoNode,
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,
+ IN OUT PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_IO_DEVICE *Temp;
- PCI_RESOURCE_NODE *IoBridge;
- PCI_RESOURCE_NODE *Mem32Bridge;
- PCI_RESOURCE_NODE *PMem32Bridge;
- PCI_RESOURCE_NODE *Mem64Bridge;
- PCI_RESOURCE_NODE *PMem64Bridge;
- LIST_ENTRY *CurrentLink;
+ PCI_IO_DEVICE *Temp;
+ PCI_RESOURCE_NODE *IoBridge;
+ PCI_RESOURCE_NODE *Mem32Bridge;
+ PCI_RESOURCE_NODE *PMem32Bridge;
+ PCI_RESOURCE_NODE *Mem64Bridge;
+ PCI_RESOURCE_NODE *PMem64Bridge;
+ LIST_ENTRY *CurrentLink;
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
-
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
//
@@ -774,7 +770,6 @@ CreateResourceMap ( );
if (IS_PCI_BRIDGE (&Temp->Pci)) {
-
//
// If the device has children, create a bridge resource node for this PPB
// Note: For PPB, memory aperture is aligned with 1MB and IO aperture
@@ -910,7 +905,6 @@ CreateResourceMap ( FreePool (PMem64Bridge);
PMem64Bridge = NULL;
}
-
}
//
@@ -976,12 +970,12 @@ CreateResourceMap ( **/
VOID
ResourcePaddingPolicy (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
//
@@ -1015,18 +1009,18 @@ ResourcePaddingPolicy ( **/
VOID
DegradeResource (
- IN PCI_IO_DEVICE *Bridge,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *Bridge,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_IO_DEVICE *PciIoDevice;
- LIST_ENTRY *ChildDeviceLink;
- LIST_ENTRY *ChildNodeLink;
- LIST_ENTRY *NextChildNodeLink;
- PCI_RESOURCE_NODE *ResourceNode;
+ PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *ChildDeviceLink;
+ LIST_ENTRY *ChildNodeLink;
+ LIST_ENTRY *NextChildNodeLink;
+ PCI_RESOURCE_NODE *ResourceNode;
if (FeaturePcdGet (PcdPciDegradeResourceForOptionRom)) {
//
@@ -1040,15 +1034,17 @@ DegradeResource ( if (!IsListEmpty (&Mem64Node->ChildList)) {
ChildNodeLink = Mem64Node->ChildList.ForwardLink;
while (ChildNodeLink != &Mem64Node->ChildList) {
- ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
+ ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
if ((ResourceNode->PciDev == PciIoDevice) &&
(ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
- ) {
+ )
+ {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (Mem32Node, ResourceNode);
}
+
ChildNodeLink = NextChildNodeLink;
}
}
@@ -1056,20 +1052,22 @@ DegradeResource ( if (!IsListEmpty (&PMem64Node->ChildList)) {
ChildNodeLink = PMem64Node->ChildList.ForwardLink;
while (ChildNodeLink != &PMem64Node->ChildList) {
- ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
+ ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink);
NextChildNodeLink = ChildNodeLink->ForwardLink;
if ((ResourceNode->PciDev == PciIoDevice) &&
(ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed)
- ) {
+ )
+ {
RemoveEntryList (ChildNodeLink);
InsertResourceNode (PMem32Node, ResourceNode);
}
+
ChildNodeLink = NextChildNodeLink;
}
}
-
}
+
ChildDeviceLink = ChildDeviceLink->ForwardLink;
}
}
@@ -1095,11 +1093,11 @@ DegradeResource ( // if the bridge does not support MEM64, degrade MEM64 to MEM32
//
if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPPORTED)) {
- MergeResourceTree (
- Mem32Node,
- Mem64Node,
- TRUE
- );
+ MergeResourceTree (
+ Mem32Node,
+ Mem64Node,
+ TRUE
+ );
}
//
@@ -1117,7 +1115,7 @@ DegradeResource ( // if both PMEM64 and PMEM32 requests from child devices, which can not be satisfied
// by a P2P bridge simultaneously, keep PMEM64 and degrade PMEM32 to MEM32.
//
- if (!IsListEmpty (&PMem64Node->ChildList) && Bridge->Parent != NULL) {
+ if (!IsListEmpty (&PMem64Node->ChildList) && (Bridge->Parent != NULL)) {
MergeResourceTree (
Mem32Node,
PMem32Node,
@@ -1174,8 +1172,8 @@ DegradeResource ( **/
BOOLEAN
BridgeSupportResourceDecode (
- IN PCI_IO_DEVICE *Bridge,
- IN UINT32 Decode
+ IN PCI_IO_DEVICE *Bridge,
+ IN UINT32 Decode
)
{
if (((Bridge->Decodes) & Decode) != 0) {
@@ -1199,13 +1197,13 @@ BridgeSupportResourceDecode ( **/
EFI_STATUS
ProgramResource (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Bridge
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- LIST_ENTRY *CurrentLink;
- PCI_RESOURCE_NODE *Node;
- EFI_STATUS Status;
+ LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Node;
+ EFI_STATUS Status;
if (Base == gAllOne) {
return EFI_OUT_OF_RESOURCES;
@@ -1214,11 +1212,9 @@ ProgramResource ( CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != &Bridge->ChildList) {
-
Node = RESOURCE_NODE_FROM_LINK (CurrentLink);
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {
-
if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {
//
// Program the PCI Card Bus device
@@ -1257,13 +1253,13 @@ ProgramResource ( **/
VOID
ProgramBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
ASSERT (Node->Bar < PCI_MAX_BAR);
@@ -1289,59 +1285,58 @@ ProgramBar ( Node->PciDev->Allocated = TRUE;
switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
-
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
- //
- // Continue to the case PciBarTypeOpRom to set the BaseAddress.
- // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture
- // the MEM32 resource requirement for Option ROM shadow.
- //
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
+ //
+ // Continue to the case PciBarTypeOpRom to set the BaseAddress.
+ // PciBarTypeOpRom is a virtual BAR only in root bridge, to capture
+ // the MEM32 resource requirement for Option ROM shadow.
+ //
- case PciBarTypeOpRom:
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ case PciBarTypeOpRom:
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- break;
+ break;
- case PciBarTypeMem64:
- case PciBarTypePMem64:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- break;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -1354,13 +1349,13 @@ ProgramBar ( **/
EFI_STATUS
ProgramVfBar (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
ASSERT (Node->Bar < PCI_MAX_BAR);
ASSERT (Node->Virtual);
@@ -1379,53 +1374,52 @@ ProgramVfBar ( Node->PciDev->Allocated = TRUE;
switch ((Node->PciDev->VfPciBar[Node->Bar]).BarType) {
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
-
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->VfPciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->VfPciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
- Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
- break;
+ Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
+ break;
- case PciBarTypeMem64:
- case PciBarTypePMem64:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->VfPciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->VfPciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ ((Node->PciDev->VfPciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
- break;
+ Node->PciDev->VfPciBar[Node->Bar].BaseAddress = Address;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- break;
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ break;
- default:
- break;
+ default:
+ break;
}
return EFI_SUCCESS;
@@ -1440,24 +1434,24 @@ ProgramVfBar ( **/
VOID
ProgramPpbApperture (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT32 Address32;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT32 Address32;
Address = 0;
//
// If no device resource of this PPB, return anyway
// Aperture is set default in the initialization code
//
- if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {
+ if ((Node->Length == 0) || (Node->ResourceUsage == PciResUsagePadding)) {
//
// For padding resource node, just ignore when programming
//
- return ;
+ return;
}
PciIo = &(Node->PciDev->PciIo);
@@ -1469,174 +1463,173 @@ ProgramPpbApperture ( Node->PciDev->Allocated = TRUE;
switch (Node->Bar) {
+ case PPB_BAR_0:
+ case PPB_BAR_1:
+ switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ case PciBarTypeIo16:
+ case PciBarTypeIo32:
+ case PciBarTypeMem32:
+ case PciBarTypePMem32:
+
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address
+ );
- case PPB_BAR_0:
- case PPB_BAR_1:
- switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PciBarTypeIo16:
- case PciBarTypeIo32:
- case PciBarTypeMem32:
- case PciBarTypePMem32:
+ case PciBarTypeMem64:
+ case PciBarTypePMem64:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Address32 = (UINT32)(Address & 0x00000000FFFFFFFF);
- case PciBarTypeMem64:
- case PciBarTypePMem64:
-
- Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
+ 1,
+ &Address32
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 (Address, 32);
- Address32 = (UINT32) RShiftU64 (Address, 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ (UINT8)((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
+ 1,
+ &Address32
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),
- 1,
- &Address32
- );
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ default:
+ break;
+ }
- default:
- break;
- }
- break;
+ break;
- case PPB_IO_RANGE:
+ case PPB_IO_RANGE:
- Address32 = ((UINT32) (Address)) >> 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint8,
- 0x1C,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ 0x1C,
+ 1,
+ &Address32
+ );
- Address32 >>= 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x30,
- 1,
- &Address32
- );
+ Address32 >>= 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x30,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint8,
- 0x1D,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ 0x1D,
+ 1,
+ &Address32
+ );
- Address32 >>= 8;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x32,
- 1,
- &Address32
- );
+ Address32 >>= 8;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x32,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PPB_MEM32_RANGE:
+ case PPB_MEM32_RANGE:
- Address32 = ((UINT32) (Address)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x20,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x20,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x22,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x22,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- case PPB_PMEM32_RANGE:
- case PPB_PMEM64_RANGE:
+ case PPB_PMEM32_RANGE:
+ case PPB_PMEM64_RANGE:
- Address32 = ((UINT32) (Address)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x24,
- 1,
- &Address32
- );
+ Address32 = ((UINT32)(Address)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x24,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) (Address + Node->Length - 1);
- Address32 = ((UINT32) (Address32)) >> 16;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint16,
- 0x26,
- 1,
- &Address32
- );
+ Address32 = (UINT32)(Address + Node->Length - 1);
+ Address32 = ((UINT32)(Address32)) >> 16;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ 0x26,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 (Address, 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- 0x28,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 (Address, 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x28,
+ 1,
+ &Address32
+ );
- Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- 0x2C,
- 1,
- &Address32
- );
+ Address32 = (UINT32)RShiftU64 ((Address + Node->Length - 1), 32);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x2C,
+ 1,
+ &Address32
+ );
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -1650,15 +1643,16 @@ ProgramPpbApperture ( **/
VOID
ProgramUpstreamBridgeForRom (
- IN PCI_IO_DEVICE *PciDevice,
- IN UINT32 OptionRomBase,
- IN BOOLEAN Enable
+ IN PCI_IO_DEVICE *PciDevice,
+ IN UINT32 OptionRomBase,
+ IN BOOLEAN Enable
)
{
- PCI_IO_DEVICE *Parent;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 Base;
- UINT16 Limit;
+ PCI_IO_DEVICE *Parent;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 Base;
+ UINT16 Limit;
+
//
// For root bridge, just return.
//
@@ -1677,9 +1671,9 @@ ProgramUpstreamBridgeForRom ( //
// Only cover MMIO for Option ROM.
//
- Base = (UINT16) (OptionRomBase >> 16);
- Limit = (UINT16) ((OptionRomBase + PciDevice->RomSize - 1) >> 16);
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
+ Base = (UINT16)(OptionRomBase >> 16);
+ Limit = (UINT16)((OptionRomBase + PciDevice->RomSize - 1) >> 16);
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);
PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
@@ -1691,14 +1685,15 @@ ProgramUpstreamBridgeForRom ( //
// When devices under the bridge contains Option ROM and doesn't require 32bit MMIO.
//
- Base = (UINT16) gAllOne;
- Limit = (UINT16) gAllZero;
+ Base = (UINT16)gAllOne;
+ Limit = (UINT16)gAllZero;
} else {
- Base = (UINT16) ((UINT32) Parent->PciBar[PPB_MEM32_RANGE].BaseAddress >> 16);
- Limit = (UINT16) ((UINT32) (Parent->PciBar[PPB_MEM32_RANGE].BaseAddress
- + Parent->PciBar[PPB_MEM32_RANGE].Length - 1) >> 16);
+ Base = (UINT16)((UINT32)Parent->PciBar[PPB_MEM32_RANGE].BaseAddress >> 16);
+ Limit = (UINT16)((UINT32)(Parent->PciBar[PPB_MEM32_RANGE].BaseAddress
+ + Parent->PciBar[PPB_MEM32_RANGE].Length - 1) >> 16);
}
- PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
+
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), 1, &Base);
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), 1, &Limit);
PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
@@ -1719,11 +1714,11 @@ ProgramUpstreamBridgeForRom ( **/
BOOLEAN
ResourceRequestExisted (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
if (Bridge != NULL) {
- if (!IsListEmpty (&Bridge->ChildList) || Bridge->Length != 0) {
+ if (!IsListEmpty (&Bridge->ChildList) || (Bridge->Length != 0)) {
return TRUE;
}
}
@@ -1741,8 +1736,8 @@ ResourceRequestExisted ( **/
VOID
InitializeResourcePool (
- IN OUT PCI_RESOURCE_NODE *ResourcePool,
- IN PCI_BAR_TYPE ResourceType
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,
+ IN PCI_BAR_TYPE ResourceType
)
{
ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));
@@ -1759,17 +1754,16 @@ InitializeResourcePool ( **/
VOID
DestroyResourceTree (
- IN PCI_RESOURCE_NODE *Bridge
+ IN PCI_RESOURCE_NODE *Bridge
)
{
- PCI_RESOURCE_NODE *Temp;
- LIST_ENTRY *CurrentLink;
+ PCI_RESOURCE_NODE *Temp;
+ LIST_ENTRY *CurrentLink;
while (!IsListEmpty (&Bridge->ChildList)) {
-
CurrentLink = Bridge->ChildList.ForwardLink;
- Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
+ Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
ASSERT (Temp);
RemoveEntryList (CurrentLink);
@@ -1795,15 +1789,15 @@ DestroyResourceTree ( **/
VOID
ResourcePaddingForCardBusBridge (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- PCI_RESOURCE_NODE *Node;
+ PCI_RESOURCE_NODE *Node;
Node = NULL;
@@ -1889,14 +1883,14 @@ ResourcePaddingForCardBusBridge ( **/
VOID
ProgramP2C (
- IN UINT64 Base,
- IN PCI_RESOURCE_NODE *Node
+ IN UINT64 Base,
+ IN PCI_RESOURCE_NODE *Node
)
{
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT64 Address;
- UINT64 TempAddress;
- UINT16 BridgeControl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Address;
+ UINT64 TempAddress;
+ UINT16 BridgeControl;
Address = 0;
PciIo = &(Node->PciDev->PciIo);
@@ -1912,205 +1906,200 @@ ProgramP2C ( Node->PciDev->Allocated = TRUE;
switch (Node->Bar) {
-
- case P2C_BAR_0:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- (Node->PciDev->PciBar[Node->Bar]).Offset,
- 1,
- &Address
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- break;
-
- case P2C_MEM_1:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_0,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_LIMIT_0,
- 1,
- &TempAddress
- );
-
- if (Node->ResType == PciBarTypeMem32) {
- //
- // Set non-prefetchable bit
- //
- PciIo->Pci.Read (
+ case P2C_BAR_0:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ (Node->PciDev->PciBar[Node->Bar]).Offset,
1,
- &BridgeControl
+ &Address
);
- BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ break;
+
+ case P2C_MEM_1:
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_0,
1,
- &BridgeControl
+ &Address
);
- } else {
- //
- // Set prefetchable bit
- //
- PciIo->Pci.Read (
+ TempAddress = Address + Node->Length - 1;
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_LIMIT_0,
1,
- &BridgeControl
+ &TempAddress
);
- BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ if (Node->ResType == PciBarTypeMem32) {
+ //
+ // Set non-prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ } else {
+ //
+ // Set prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ }
+
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+
+ break;
+
+ case P2C_MEM_2:
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_BASE_1,
1,
- &BridgeControl
+ &Address
);
- }
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
+ TempAddress = Address + Node->Length - 1;
- case P2C_MEM_2:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_BASE_1,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ PCI_CARD_MEMORY_LIMIT_1,
+ 1,
+ &TempAddress
+ );
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_MEMORY_LIMIT_1,
- 1,
- &TempAddress
- );
+ if (Node->ResType == PciBarTypeMem32) {
+ //
+ // Set non-prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ } else {
+ //
+ // Set prefetchable bit
+ //
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint16,
+ PCI_CARD_BRIDGE_CONTROL,
+ 1,
+ &BridgeControl
+ );
+ }
- if (Node->ResType == PciBarTypeMem32) {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+ break;
- //
- // Set non-prefetchable bit
- //
- PciIo->Pci.Read (
+ case P2C_IO_1:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_0_LOWER,
1,
- &BridgeControl
+ &Address
);
- BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);
+ TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_LIMIT_0_LOWER,
1,
- &BridgeControl
+ &TempAddress
);
- } else {
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- //
- // Set prefetchable bit
- //
- PciIo->Pci.Read (
+ break;
+
+ case P2C_IO_2:
+ PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_BASE_1_LOWER,
1,
- &BridgeControl
+ &Address
);
- BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;
+ TempAddress = Address + Node->Length - 1;
PciIo->Pci.Write (
PciIo,
- EfiPciIoWidthUint16,
- PCI_CARD_BRIDGE_CONTROL,
+ EfiPciIoWidthUint32,
+ PCI_CARD_IO_LIMIT_1_LOWER,
1,
- &BridgeControl
+ &TempAddress
);
- }
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
-
- case P2C_IO_1:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_0_LOWER,
- 1,
- &Address
- );
-
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_LIMIT_0_LOWER,
- 1,
- &TempAddress
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
-
- break;
-
- case P2C_IO_2:
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_BASE_1_LOWER,
- 1,
- &Address
- );
- TempAddress = Address + Node->Length - 1;
- PciIo->Pci.Write (
- PciIo,
- EfiPciIoWidthUint32,
- PCI_CARD_IO_LIMIT_1_LOWER,
- 1,
- &TempAddress
- );
-
- Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
- Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
- Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
- break;
+ Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
+ Node->PciDev->PciBar[Node->Bar].Length = Node->Length;
+ Node->PciDev->PciBar[Node->Bar].BarType = Node->ResType;
+ break;
- default:
- break;
+ default:
+ break;
}
}
@@ -2127,34 +2116,32 @@ ProgramP2C ( **/
VOID
ApplyResourcePadding (
- IN PCI_IO_DEVICE *PciDev,
- IN PCI_RESOURCE_NODE *IoNode,
- IN PCI_RESOURCE_NODE *Mem32Node,
- IN PCI_RESOURCE_NODE *PMem32Node,
- IN PCI_RESOURCE_NODE *Mem64Node,
- IN PCI_RESOURCE_NODE *PMem64Node
+ IN PCI_IO_DEVICE *PciDev,
+ IN PCI_RESOURCE_NODE *IoNode,
+ IN PCI_RESOURCE_NODE *Mem32Node,
+ IN PCI_RESOURCE_NODE *PMem32Node,
+ IN PCI_RESOURCE_NODE *Mem64Node,
+ IN PCI_RESOURCE_NODE *PMem64Node
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- PCI_RESOURCE_NODE *Node;
- UINT8 DummyBarIndex;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
+ PCI_RESOURCE_NODE *Node;
+ UINT8 DummyBarIndex;
DummyBarIndex = 0;
Ptr = PciDev->ResourcePaddingDescriptors;
- while (((EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {
-
- if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO) {
+ while (((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc != ACPI_END_TAG_DESCRIPTOR) {
+ if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_IO)) {
if (Ptr->AddrLen != 0) {
-
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeIo16,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeIo16,
+ PciResUsagePadding
+ );
InsertResourceNode (
IoNode,
Node
@@ -2165,23 +2152,21 @@ ApplyResourcePadding ( continue;
}
- if (Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
-
+ if ((Ptr->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) && (Ptr->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM)) {
if (Ptr->AddrSpaceGranularity == 32) {
-
//
// prefetchable
//
if (Ptr->SpecificFlag == 0x6) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypePMem32,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypePMem32,
+ PciResUsagePadding
+ );
InsertResourceNode (
PMem32Node,
Node
@@ -2198,13 +2183,13 @@ ApplyResourcePadding ( if (Ptr->SpecificFlag == 0) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeMem32,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeMem32,
+ PciResUsagePadding
+ );
InsertResourceNode (
Mem32Node,
Node
@@ -2217,20 +2202,19 @@ ApplyResourcePadding ( }
if (Ptr->AddrSpaceGranularity == 64) {
-
//
// prefetchable
//
if (Ptr->SpecificFlag == 0x6) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypePMem64,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypePMem64,
+ PciResUsagePadding
+ );
InsertResourceNode (
PMem64Node,
Node
@@ -2247,13 +2231,13 @@ ApplyResourcePadding ( if (Ptr->SpecificFlag == 0) {
if (Ptr->AddrLen != 0) {
Node = CreateResourceNode (
- PciDev,
- Ptr->AddrLen,
- Ptr->AddrRangeMax,
- DummyBarIndex,
- PciBarTypeMem64,
- PciResUsagePadding
- );
+ PciDev,
+ Ptr->AddrLen,
+ Ptr->AddrRangeMax,
+ DummyBarIndex,
+ PciBarTypeMem64,
+ PciResUsagePadding
+ );
InsertResourceNode (
Mem64Node,
Node
@@ -2280,13 +2264,12 @@ ApplyResourcePadding ( **/
VOID
GetResourcePaddingPpb (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
)
{
- if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
+ if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {
GetResourcePaddingForHpb (PciIoDevice);
}
}
}
-
|