diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 197 |
1 files changed, 96 insertions, 101 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 70102a7fcf..80be3311d4 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -21,18 +21,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
UINT8
XhcReadCapReg8 (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT8 Data;
- EFI_STATUS Status;
+ UINT8 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint8,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -57,18 +57,18 @@ XhcReadCapReg8 ( **/
UINT32
XhcReadCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
Status = Xhc->PciIo->Mem.Read (
Xhc->PciIo,
EfiPciIoWidthUint32,
XHC_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -93,12 +93,12 @@ XhcReadCapReg ( **/
UINT32
XhcReadOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -129,12 +129,12 @@ XhcReadOpReg ( **/
VOID
XhcWriteOpReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->CapLength != 0);
@@ -152,10 +152,6 @@ XhcWriteOpReg ( }
}
-
-
-
-
/**
Write the data to the XHCI door bell register.
@@ -166,12 +162,12 @@ XhcWriteOpReg ( **/
VOID
XhcWriteDoorBellReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->DBOff != 0);
@@ -200,12 +196,12 @@ XhcWriteDoorBellReg ( **/
UINT32
XhcReadRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -236,12 +232,12 @@ XhcReadRuntimeReg ( **/
VOID
XhcWriteRuntimeReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->RTSOff != 0);
@@ -270,12 +266,12 @@ XhcWriteRuntimeReg ( **/
UINT32
XhcReadExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset
)
{
- UINT32 Data;
- EFI_STATUS Status;
+ UINT32 Data;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -306,12 +302,12 @@ XhcReadExtCapReg ( **/
VOID
XhcWriteExtCapReg (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Data
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Data
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Xhc->ExtCapRegBase != 0);
@@ -329,7 +325,6 @@ XhcWriteExtCapReg ( }
}
-
/**
Set one bit of the runtime register while keeping other bits.
@@ -340,12 +335,12 @@ XhcWriteExtCapReg ( **/
VOID
XhcSetRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data |= Bit;
@@ -362,12 +357,12 @@ XhcSetRuntimeRegBit ( **/
VOID
XhcClearRuntimeRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadRuntimeReg (Xhc, Offset);
Data &= ~Bit;
@@ -384,19 +379,18 @@ XhcClearRuntimeRegBit ( **/
VOID
XhcSetOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data |= Bit;
XhcWriteOpReg (Xhc, Offset, Data);
}
-
/**
Clear one bit of the operational register while keeping other bits.
@@ -407,12 +401,12 @@ XhcSetOpRegBit ( **/
VOID
XhcClearOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit
)
{
- UINT32 Data;
+ UINT32 Data;
Data = XhcReadOpReg (Xhc, Offset);
Data &= ~Bit;
@@ -436,15 +430,15 @@ XhcClearOpRegBit ( **/
EFI_STATUS
XhcWaitOpRegBit (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Offset,
- IN UINT32 Bit,
- IN BOOLEAN WaitToSet,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Offset,
+ IN UINT32 Bit,
+ IN BOOLEAN WaitToSet,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
- EFI_EVENT TimeoutEvent;
+ EFI_STATUS Status;
+ EFI_EVENT TimeoutEvent;
TimeoutEvent = NULL;
@@ -460,15 +454,17 @@ XhcWaitOpRegBit ( &TimeoutEvent
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
- Status = gBS->SetTimer (TimeoutEvent,
- TimerRelative,
- EFI_TIMER_PERIOD_MILLISECONDS(Timeout));
+ Status = gBS->SetTimer (
+ TimeoutEvent,
+ TimerRelative,
+ EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
+ );
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto DONE;
}
@@ -479,7 +475,7 @@ XhcWaitOpRegBit ( }
gBS->Stall (XHC_1_MICROSECOND);
- } while (EFI_ERROR(gBS->CheckEvent (TimeoutEvent)));
+ } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
Status = EFI_TIMEOUT;
@@ -499,10 +495,10 @@ DONE: **/
VOID
XhcSetBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -523,10 +519,10 @@ XhcSetBiosOwnership ( **/
VOID
XhcClearBiosOwnership (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
- UINT32 Buffer;
+ UINT32 Buffer;
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
return;
@@ -550,13 +546,13 @@ XhcClearBiosOwnership ( **/
UINT32
XhcGetCapabilityAddr (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT8 CapId
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT8 CapId
)
{
- UINT32 ExtCapOffset;
- UINT8 NextExtCapReg;
- UINT32 Data;
+ UINT32 ExtCapOffset;
+ UINT8 NextExtCapReg;
+ UINT32 Data;
ExtCapOffset = 0;
@@ -568,6 +564,7 @@ XhcGetCapabilityAddr ( if ((Data & 0xFF) == CapId) {
return ExtCapOffset;
}
+
//
// If not, then traverse all of the ext capability registers till finding out it.
//
@@ -589,13 +586,12 @@ XhcGetCapabilityAddr ( **/
BOOLEAN
XhcIsHalt (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
}
-
/**
Whether system error occurred.
@@ -607,7 +603,7 @@ XhcIsHalt ( **/
BOOLEAN
XhcIsSysError (
- IN USB_XHCI_INSTANCE *Xhc
+ IN USB_XHCI_INSTANCE *Xhc
)
{
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
@@ -627,11 +623,11 @@ XhcSetHsee ( IN USB_XHCI_INSTANCE *Xhc
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- UINT16 XhciCmd;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 XhciCmd;
- PciIo = Xhc->PciIo;
+ PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
@@ -658,11 +654,11 @@ XhcSetHsee ( **/
EFI_STATUS
XhcResetHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
@@ -679,7 +675,8 @@ XhcResetHC ( }
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
+ {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
//
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
@@ -701,7 +698,6 @@ XhcResetHC ( return Status;
}
-
/**
Halt the XHCI host controller.
@@ -714,18 +710,17 @@ XhcResetHC ( **/
EFI_STATUS
XhcHaltHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
return Status;
}
-
/**
Set the XHCI host controller to run.
@@ -738,11 +733,11 @@ XhcHaltHC ( **/
EFI_STATUS
XhcRunHC (
- IN USB_XHCI_INSTANCE *Xhc,
- IN UINT32 Timeout
+ IN USB_XHCI_INSTANCE *Xhc,
+ IN UINT32 Timeout
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
|