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-rw-r--r--MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h135
1 files changed, 67 insertions, 68 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
index 03a55f3eb6..0800b15c72 100644
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
@@ -25,33 +25,33 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
-typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
-typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
+typedef struct _PEI_XHC_DEV PEI_XHC_DEV;
+typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
#include "UsbHcMem.h"
#include "XhciReg.h"
#include "XhciSched.h"
-#define CMD_RING_TRB_NUMBER 0x100
-#define TR_RING_TRB_NUMBER 0x100
-#define ERST_NUMBER 0x01
-#define EVENT_RING_TRB_NUMBER 0x200
+#define CMD_RING_TRB_NUMBER 0x100
+#define TR_RING_TRB_NUMBER 0x100
+#define ERST_NUMBER 0x01
+#define EVENT_RING_TRB_NUMBER 0x200
-#define XHC_1_MICROSECOND 1
-#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
-#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
+#define XHC_1_MICROSECOND 1
+#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
+#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
//
// XHC reset timeout experience values.
// The unit is millisecond, setting it as 1s.
//
-#define XHC_RESET_TIMEOUT (1000)
+#define XHC_RESET_TIMEOUT (1000)
//
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
// The unit is microsecond, setting it as 10ms.
//
-#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
+#define XHC_RESET_RECOVERY_DELAY (10 * 1000)
//
// Wait for root port state stable.
@@ -62,11 +62,11 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
-#define XHC_GENERIC_TIMEOUT (10 * 1000)
+#define XHC_GENERIC_TIMEOUT (10 * 1000)
-#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
-#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
-#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
+#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
+#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
+#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \
(XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))
@@ -86,23 +86,23 @@ struct _USB_DEV_CONTEXT {
//
// Whether this entry in UsbDevContext array is used or not.
//
- BOOLEAN Enabled;
+ BOOLEAN Enabled;
//
// The slot id assigned to the new device through XHCI's Enable_Slot cmd.
//
- UINT8 SlotId;
+ UINT8 SlotId;
//
// The route string presented an attached usb device.
//
- USB_DEV_ROUTE RouteString;
+ USB_DEV_ROUTE RouteString;
//
// The route string of parent device if it exists. Otherwise it's zero.
//
- USB_DEV_ROUTE ParentRouteString;
+ USB_DEV_ROUTE ParentRouteString;
//
// The actual device address assigned by XHCI through Address_Device command.
//
- UINT8 XhciDevAddr;
+ UINT8 XhciDevAddr;
//
// The requested device address from UsbBus driver through Set_Address standard usb request.
// As XHCI spec replaces this request with Address_Device command, we have to record the
@@ -111,23 +111,23 @@ struct _USB_DEV_CONTEXT {
// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
// device address and access the actual device.
//
- UINT8 BusDevAddr;
+ UINT8 BusDevAddr;
//
// The pointer to the input device context.
//
- VOID *InputContext;
+ VOID *InputContext;
//
// The pointer to the output device context.
//
- VOID *OutputContext;
+ VOID *OutputContext;
//
// The transfer queue for every endpoint.
//
- VOID *EndpointTransferRing[31];
+ VOID *EndpointTransferRing[31];
//
// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
//
- EFI_USB_DEVICE_DESCRIPTOR DevDesc;
+ EFI_USB_DEVICE_DESCRIPTOR DevDesc;
//
// As a usb device may include multiple configuration descriptors, we dynamically allocate an array
// to store them.
@@ -135,59 +135,59 @@ struct _USB_DEV_CONTEXT {
// such as Interface descriptor, Endpoint descriptor, and so on.
// These information is used to support XHCI's Config_Endpoint cmd.
//
- EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
+ EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;
};
-#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
+#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
struct _PEI_XHC_DEV {
- UINTN Signature;
- PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
- UINT32 UsbHostControllerBaseAddress;
- USBHC_MEM_POOL *MemPool;
+ UINTN Signature;
+ PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ UINT32 UsbHostControllerBaseAddress;
+ USBHC_MEM_POOL *MemPool;
//
// EndOfPei callback is used to stop the XHC DMA operation
// after exit PEI phase.
//
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
//
// XHCI configuration data
//
- UINT8 CapLength; ///< Capability Register Length
- XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
- XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
- XHC_HCCPARAMS HcCParams; ///< Capability Parameters
- UINT32 DBOff; ///< Doorbell Offset
- UINT32 RTSOff; ///< Runtime Register Space Offset
- UINT32 PageSize;
- UINT32 MaxScratchpadBufs;
- UINT64 *ScratchBuf;
- VOID *ScratchMap;
- UINT64 *ScratchEntry;
- UINTN *ScratchEntryMap;
- UINT64 *DCBAA;
- UINT32 MaxSlotsEn;
+ UINT8 CapLength; ///< Capability Register Length
+ XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1
+ XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2
+ XHC_HCCPARAMS HcCParams; ///< Capability Parameters
+ UINT32 DBOff; ///< Doorbell Offset
+ UINT32 RTSOff; ///< Runtime Register Space Offset
+ UINT32 PageSize;
+ UINT32 MaxScratchpadBufs;
+ UINT64 *ScratchBuf;
+ VOID *ScratchMap;
+ UINT64 *ScratchEntry;
+ UINTN *ScratchEntryMap;
+ UINT64 *DCBAA;
+ UINT32 MaxSlotsEn;
//
// Cmd Transfer Ring
//
- TRANSFER_RING CmdRing;
+ TRANSFER_RING CmdRing;
//
// EventRing
//
- EVENT_RING EventRing;
+ EVENT_RING EventRing;
//
// Store device contexts managed by XHCI device
// The array supports up to 255 devices, entry 0 is reserved and should not be used.
//
- USB_DEV_CONTEXT UsbDevContext[256];
+ USB_DEV_CONTEXT UsbDevContext[256];
};
-#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
-#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
+#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
/**
Initialize the memory management pool for the host controller.
@@ -209,7 +209,7 @@ UsbHcInitMemPool (
**/
VOID
UsbHcFreeMemPool (
- IN USBHC_MEM_POOL *Pool
+ IN USBHC_MEM_POOL *Pool
)
;
@@ -225,8 +225,8 @@ UsbHcFreeMemPool (
**/
VOID *
UsbHcAllocateMem (
- IN USBHC_MEM_POOL *Pool,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN UINTN Size
)
;
@@ -240,13 +240,12 @@ UsbHcAllocateMem (
**/
VOID
UsbHcFreeMem (
- IN USBHC_MEM_POOL *Pool,
- IN VOID *Mem,
- IN UINTN Size
+ IN USBHC_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
)
;
-
/**
Initialize IOMMU.
**/
@@ -276,11 +275,11 @@ IoMmuInit (
**/
EFI_STATUS
IoMmuMap (
- IN EDKII_IOMMU_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
);
/**
@@ -294,7 +293,7 @@ IoMmuMap (
**/
EFI_STATUS
IoMmuUnmap (
- IN VOID *Mapping
+ IN VOID *Mapping
);
/**
@@ -337,9 +336,9 @@ IoMmuAllocateBuffer (
**/
EFI_STATUS
IoMmuFreeBuffer (
- IN UINTN Pages,
- IN VOID *HostAddress,
- IN VOID *Mapping
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
);
/**