diff options
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 1038 |
1 files changed, 543 insertions, 495 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c index 1fc06aaa61..cc597a4371 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -19,25 +19,25 @@ SPDX-License-Identifier: BSD-2-Clause-Patent @return Created URB or NULL.
**/
-URB*
+URB *
XhcPeiCreateCmdTrb (
- IN PEI_XHC_DEV *Xhc,
- IN TRB_TEMPLATE *CmdTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN TRB_TEMPLATE *CmdTrb
)
{
- URB *Urb;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
return NULL;
}
- Urb->Signature = XHC_URB_SIG;
+ Urb->Signature = XHC_URB_SIG;
- Urb->Ring = &Xhc->CmdRing;
+ Urb->Ring = &Xhc->CmdRing;
XhcPeiSyncTrsRing (Xhc, Urb->Ring);
- Urb->TrbNum = 1;
- Urb->TrbStart = Urb->Ring->RingEnqueue;
+ Urb->TrbNum = 1;
+ Urb->TrbStart = Urb->Ring->RingEnqueue;
CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
Urb->TrbEnd = Urb->TrbStart;
@@ -62,14 +62,14 @@ XhcPeiCreateCmdTrb ( **/
EFI_STATUS
XhcPeiCmdTransfer (
- IN PEI_XHC_DEV *Xhc,
- IN TRB_TEMPLATE *CmdTrb,
- IN UINTN Timeout,
- OUT TRB_TEMPLATE **EvtTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN TRB_TEMPLATE *CmdTrb,
+ IN UINTN Timeout,
+ OUT TRB_TEMPLATE **EvtTrb
)
{
- EFI_STATUS Status;
- URB *Urb;
+ EFI_STATUS Status;
+ URB *Urb;
//
// Validate the parameters
@@ -126,24 +126,24 @@ ON_EXIT: @return Created URB or NULL
**/
-URB*
+URB *
XhcPeiCreateUrb (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 BusAddr,
- IN UINT8 EpAddr,
- IN UINT8 DevSpeed,
- IN UINTN MaxPacket,
- IN UINTN Type,
- IN EFI_USB_DEVICE_REQUEST *Request,
- IN VOID *Data,
- IN UINTN DataLen,
- IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
- IN VOID *Context
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 BusAddr,
+ IN UINT8 EpAddr,
+ IN UINT8 DevSpeed,
+ IN UINTN MaxPacket,
+ IN UINTN Type,
+ IN EFI_USB_DEVICE_REQUEST *Request,
+ IN VOID *Data,
+ IN UINTN DataLen,
+ IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
+ IN VOID *Context
)
{
- USB_ENDPOINT *Ep;
- EFI_STATUS Status;
- URB *Urb;
+ USB_ENDPOINT *Ep;
+ EFI_STATUS Status;
+ URB *Urb;
Urb = AllocateZeroPool (sizeof (URB));
if (Urb == NULL) {
@@ -154,7 +154,7 @@ XhcPeiCreateUrb ( Ep = &Urb->Ep;
Ep->BusAddr = BusAddr;
- Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
+ Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
Ep->DevSpeed = DevSpeed;
Ep->MaxPacket = MaxPacket;
@@ -185,8 +185,8 @@ XhcPeiCreateUrb ( **/
VOID
XhcPeiFreeUrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
if ((Xhc == NULL) || (Urb == NULL)) {
@@ -209,23 +209,23 @@ XhcPeiFreeUrb ( **/
EFI_STATUS
XhcPeiCreateTransferTrb (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- VOID *OutputContext;
- TRANSFER_RING *EPRing;
- UINT8 EPType;
- UINT8 SlotId;
- UINT8 Dci;
- TRB *TrbStart;
- UINTN TotalLen;
- UINTN Len;
- UINTN TrbNum;
- EDKII_IOMMU_OPERATION MapOp;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- EFI_STATUS Status;
+ VOID *OutputContext;
+ TRANSFER_RING *EPRing;
+ UINT8 EPType;
+ UINT8 SlotId;
+ UINT8 Dci;
+ TRB *TrbStart;
+ UINTN TotalLen;
+ UINTN Len;
+ UINTN TrbNum;
+ EDKII_IOMMU_OPERATION MapOp;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ EFI_STATUS Status;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
@@ -238,27 +238,27 @@ XhcPeiCreateTransferTrb ( Urb->Completed = 0;
Urb->Result = EFI_USB_NOERROR;
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
- EPRing = (TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
- Urb->Ring = EPRing;
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+ EPRing = (TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
+ Urb->Ring = EPRing;
OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
if (Xhc->HcCParams.Data.Csz == 0) {
- EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
} else {
- EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
+ EPType = (UINT8)((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
//
// No need to remap.
//
if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
- if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
+ if (((UINT8)(Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EdkiiIoMmuOperationBusMasterWrite;
} else {
MapOp = EdkiiIoMmuOperationBusMasterRead;
}
- Len = Urb->DataLen;
+ Len = Urb->DataLen;
Status = IoMmuMap (MapOp, Urb->Data, &Len, &PhyAddr, &Map);
if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
@@ -266,8 +266,8 @@ XhcPeiCreateTransferTrb ( return EFI_OUT_OF_RESOURCES;
}
- Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
- Urb->DataMap = Map;
+ Urb->DataPhy = (VOID *)((UINTN)PhyAddr);
+ Urb->DataMap = Map;
}
//
@@ -280,7 +280,7 @@ XhcPeiCreateTransferTrb ( //
// For control transfer, create SETUP_STAGE_TRB first.
//
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
@@ -303,6 +303,7 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrSetup.TRT = 0;
}
+
//
// Update the cycle bit
//
@@ -314,10 +315,10 @@ XhcPeiCreateTransferTrb ( //
if (Urb->DataLen > 0) {
XhcPeiSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
- TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
+ TrbStart->TrbCtrData.Length = (UINT32)Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1;
@@ -332,18 +333,20 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrData.DIR = 0;
}
+
//
// Update the cycle bit
//
TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
Urb->TrbNum++;
}
+
//
// For control transfer, create STATUS_STAGE_TRB.
// Get the pointer to next TRB for status stage use
//
XhcPeiSyncTrsRing (Xhc, EPRing);
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrStatus.IntTarget = 0;
TrbStart->TrbCtrStatus.IOC = 1;
TrbStart->TrbCtrStatus.CH = 0;
@@ -355,6 +358,7 @@ XhcPeiCreateTransferTrb ( } else {
TrbStart->TrbCtrStatus.DIR = 0;
}
+
//
// Update the cycle bit
//
@@ -364,7 +368,7 @@ XhcPeiCreateTransferTrb ( //
XhcPeiSyncTrsRing (Xhc, EPRing);
Urb->TrbNum++;
- Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;
+ Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
break;
@@ -373,17 +377,18 @@ XhcPeiCreateTransferTrb ( TotalLen = 0;
Len = 0;
TrbNum = 0;
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
while (TotalLen < Urb->DataLen) {
if ((TotalLen + 0x10000) >= Urb->DataLen) {
Len = Urb->DataLen - TotalLen;
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -408,17 +413,18 @@ XhcPeiCreateTransferTrb ( TotalLen = 0;
Len = 0;
TrbNum = 0;
- TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
while (TotalLen < Urb->DataLen) {
if ((TotalLen + 0x10000) >= Urb->DataLen) {
Len = Urb->DataLen - TotalLen;
} else {
Len = 0x10000;
}
- TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
- TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
- TrbStart->TrbNormal.Length = (UINT32) Len;
+
+ TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
+ TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT ((UINT8 *)Urb->DataPhy + TotalLen);
+ TrbStart->TrbNormal.Length = (UINT32)Len;
TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1;
@@ -439,7 +445,7 @@ XhcPeiCreateTransferTrb ( break;
default:
- DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n",EPType));
+ DEBUG ((DEBUG_INFO, "Not supported EPType 0x%x!\n", EPType));
ASSERT (FALSE);
break;
}
@@ -463,20 +469,21 @@ XhcPeiCreateTransferTrb ( **/
EFI_STATUS
XhcPeiRecoverHaltedEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
DEBUG ((DEBUG_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));
@@ -484,7 +491,7 @@ XhcPeiRecoverHaltedEndpoint ( // 1) Send Reset endpoint command to transit from halt to stop state
//
Status = XhcPeiResetEndpoint (Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -493,7 +500,7 @@ XhcPeiRecoverHaltedEndpoint ( // 2) Set dequeue pointer
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -522,20 +529,21 @@ Done: **/
EFI_STATUS
XhcPeiDequeueTrbFromEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EFI_STATUS Status;
- UINT8 Dci;
- UINT8 SlotId;
+ EFI_STATUS Status;
+ UINT8 Dci;
+ UINT8 SlotId;
Status = EFI_SUCCESS;
SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
DEBUG ((DEBUG_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));
@@ -543,7 +551,7 @@ XhcPeiDequeueTrbFromEndpoint ( // 1) Send Stop endpoint command to stop endpoint.
//
Status = XhcPeiStopEndpoint (Xhc, SlotId, Dci);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
goto Done;
}
@@ -552,7 +560,7 @@ XhcPeiDequeueTrbFromEndpoint ( // 2) Set dequeue pointer
//
Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
goto Done;
}
@@ -578,8 +586,8 @@ Done: **/
BOOLEAN
XhcPeiIsTransferRingTrb (
- IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ IN TRB_TEMPLATE *Trb,
+ IN URB *Urb
)
{
TRB_TEMPLATE *CheckedTrb;
@@ -593,6 +601,7 @@ XhcPeiIsTransferRingTrb ( if (Trb == CheckedTrb) {
return TRUE;
}
+
CheckedTrb++;
}
@@ -611,20 +620,20 @@ XhcPeiIsTransferRingTrb ( **/
BOOLEAN
XhcPeiCheckUrbResult (
- IN PEI_XHC_DEV *Xhc,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN URB *Urb
)
{
- EVT_TRB_TRANSFER *EvtTrb;
- TRB_TEMPLATE *TRBPtr;
- UINTN Index;
- UINT8 TRBType;
- EFI_STATUS Status;
- URB *CheckedUrb;
- UINT64 XhcDequeue;
- UINT32 High;
- UINT32 Low;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EVT_TRB_TRANSFER *EvtTrb;
+ TRB_TEMPLATE *TRBPtr;
+ UINTN Index;
+ UINT8 TRBType;
+ EFI_STATUS Status;
+ URB *CheckedUrb;
+ UINT64 XhcDequeue;
+ UINT32 High;
+ UINT32 Low;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT ((Xhc != NULL) && (Urb != NULL));
@@ -646,7 +655,7 @@ XhcPeiCheckUrbResult ( //
XhcPeiSyncEventRing (Xhc, &Xhc->EventRing);
for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
- Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **) &EvtTrb));
+ Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
if (Status == EFI_NOT_READY) {
//
// All new events are handled, return directly.
@@ -664,8 +673,8 @@ XhcPeiCheckUrbResult ( //
// Need convert pci device address to host address
//
- PhyAddr = (EFI_PHYSICAL_ADDRESS) (EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
- TRBPtr = (TRB_TEMPLATE *) (UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *) (UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
+ TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
//
// Update the status of Urb according to the finished event regardless of whether
@@ -710,11 +719,12 @@ XhcPeiCheckUrbResult ( DEBUG ((DEBUG_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));
}
- TRBType = (UINT8) (TRBPtr->Type);
+ TRBType = (UINT8)(TRBPtr->Type);
if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) ||
- (TRBType == TRB_TYPE_ISOCH)) {
- CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
+ (TRBType == TRB_TYPE_ISOCH))
+ {
+ CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL *)TRBPtr)->Length - EvtTrb->Length);
}
break;
@@ -739,7 +749,7 @@ XhcPeiCheckUrbResult ( if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
CheckedUrb->Finished = TRUE;
- CheckedUrb->EvtTrb = (TRB_TEMPLATE *) EvtTrb;
+ CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;
}
}
@@ -751,9 +761,9 @@ EXIT: // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
- Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
- High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
- XhcDequeue = (UINT64) (LShiftU64((UINT64) High, 32) | Low);
+ Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
+ High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
+ XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
@@ -784,18 +794,18 @@ EXIT: **/
EFI_STATUS
XhcPeiExecTransfer (
- IN PEI_XHC_DEV *Xhc,
- IN BOOLEAN CmdTransfer,
- IN URB *Urb,
- IN UINTN Timeout
+ IN PEI_XHC_DEV *Xhc,
+ IN BOOLEAN CmdTransfer,
+ IN URB *Urb,
+ IN UINTN Timeout
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINT64 Loop;
- UINT8 SlotId;
- UINT8 Dci;
- BOOLEAN Finished;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT64 Loop;
+ UINT8 SlotId;
+ UINT8 Dci;
+ BOOLEAN Finished;
if (CmdTransfer) {
SlotId = 0;
@@ -805,7 +815,8 @@ XhcPeiExecTransfer ( if (SlotId == 0) {
return EFI_DEVICE_ERROR;
}
- Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
+
+ Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
}
Status = EFI_SUCCESS;
@@ -821,6 +832,7 @@ XhcPeiExecTransfer ( if (Finished) {
break;
}
+
MicroSecondDelay (XHC_1_MICROSECOND);
}
@@ -828,7 +840,7 @@ XhcPeiExecTransfer ( Urb->Result = EFI_USB_ERR_TIMEOUT;
Status = EFI_TIMEOUT;
} else if (Urb->Result != EFI_USB_NOERROR) {
- Status = EFI_DEVICE_ERROR;
+ Status = EFI_DEVICE_ERROR;
}
return Status;
@@ -848,16 +860,16 @@ XhcPeiExecTransfer ( **/
EFI_STATUS
XhcPeiPollPortStatusChange (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT8 Port,
- IN EFI_USB_PORT_STATUS *PortState
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT8 Port,
+ IN EFI_USB_PORT_STATUS *PortState
)
{
- EFI_STATUS Status;
- UINT8 Speed;
- UINT8 SlotId;
- USB_DEV_ROUTE RouteChart;
+ EFI_STATUS Status;
+ UINT8 Speed;
+ UINT8 SlotId;
+ USB_DEV_ROUTE RouteChart;
DEBUG ((DEBUG_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));
@@ -872,13 +884,14 @@ XhcPeiPollPortStatusChange ( RouteChart.Route.RootPortNum = Port + 1;
RouteChart.Route.TierNum = 1;
} else {
- if(Port < 14) {
+ if (Port < 14) {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
} else {
RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
}
- RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
- RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
+
+ RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
+ RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
}
SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);
@@ -891,7 +904,8 @@ XhcPeiPollPortStatusChange ( }
if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
- ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
+ ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0))
+ {
//
// Has a device attached, Identify device speed after port is enabled.
//
@@ -903,6 +917,7 @@ XhcPeiPollPortStatusChange ( } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
Speed = EFI_USB_SPEED_SUPER;
}
+
//
// Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
//
@@ -930,21 +945,22 @@ XhcPeiPollPortStatusChange ( **/
UINT8
XhcPeiEndpointToDci (
- IN UINT8 EpAddr,
- IN EFI_USB_DATA_DIRECTION Direction
+ IN UINT8 EpAddr,
+ IN EFI_USB_DATA_DIRECTION Direction
)
{
- UINT8 Index;
+ UINT8 Index;
ASSERT (EpAddr <= 15);
if (EpAddr == 0) {
return 1;
} else {
- Index = (UINT8) (2 * EpAddr);
+ Index = (UINT8)(2 * EpAddr);
if (Direction == EfiUsbDataIn) {
Index += 1;
}
+
return Index;
}
}
@@ -960,16 +976,17 @@ XhcPeiEndpointToDci ( **/
UINT8
XhcPeiBusDevAddrToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 BusDevAddr
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 BusDevAddr
)
{
- UINT8 Index;
+ UINT8 Index;
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr))
+ {
break;
}
}
@@ -992,16 +1009,17 @@ XhcPeiBusDevAddrToSlotId ( **/
UINT8
XhcPeiRouteStringToSlotId (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE RouteString
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE RouteString
)
{
- UINT8 Index;
+ UINT8 Index;
for (Index = 0; Index < 255; Index++) {
if (Xhc->UsbDevContext[Index + 1].Enabled &&
(Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
- (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword))
+ {
break;
}
}
@@ -1023,9 +1041,9 @@ XhcPeiRouteStringToSlotId ( **/
VOID
XhcPeiRingDoorBell (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
if (SlotId == 0) {
@@ -1050,25 +1068,25 @@ XhcPeiRingDoorBell ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
- UINT8 DeviceAddress;
- CMD_TRB_ENABLE_SLOT CmdTrb;
- UINT8 SlotId;
- UINT8 ParentSlotId;
- DEVICE_CONTEXT *ParentDeviceContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
+ UINT8 DeviceAddress;
+ CMD_TRB_ENABLE_SLOT CmdTrb;
+ UINT8 SlotId;
+ UINT8 ParentSlotId;
+ DEVICE_CONTEXT *ParentDeviceContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1;
@@ -1076,17 +1094,18 @@ XhcPeiInitializeDeviceSlot ( Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
- SlotId = (UINT8) EvtTrb->SlotId;
+ SlotId = (UINT8)EvtTrb->SlotId;
ASSERT (SlotId != 0);
ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
@@ -1101,10 +1120,10 @@ XhcPeiInitializeDeviceSlot ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -1130,9 +1149,10 @@ XhcPeiInitializeDeviceSlot ( //
// If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context
//
- ParentDeviceContext = (DEVICE_CONTEXT *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
+ ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -1159,9 +1179,9 @@ XhcPeiInitializeDeviceSlot ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -1174,6 +1194,7 @@ XhcPeiInitializeDeviceSlot ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -1190,7 +1211,7 @@ XhcPeiInitializeDeviceSlot ( //
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
@@ -1201,7 +1222,7 @@ XhcPeiInitializeDeviceSlot ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -1213,7 +1234,7 @@ XhcPeiInitializeDeviceSlot ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -1224,20 +1245,20 @@ XhcPeiInitializeDeviceSlot ( //
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
@@ -1261,25 +1282,25 @@ XhcPeiInitializeDeviceSlot ( **/
EFI_STATUS
XhcPeiInitializeDeviceSlot64 (
- IN PEI_XHC_DEV *Xhc,
- IN USB_DEV_ROUTE ParentRouteChart,
- IN UINT16 ParentPort,
- IN USB_DEV_ROUTE RouteChart,
- IN UINT8 DeviceSpeed
+ IN PEI_XHC_DEV *Xhc,
+ IN USB_DEV_ROUTE ParentRouteChart,
+ IN UINT16 ParentPort,
+ IN USB_DEV_ROUTE RouteChart,
+ IN UINT8 DeviceSpeed
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
- UINT8 DeviceAddress;
- CMD_TRB_ENABLE_SLOT CmdTrb;
- UINT8 SlotId;
- UINT8 ParentSlotId;
- DEVICE_CONTEXT_64 *ParentDeviceContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
+ UINT8 DeviceAddress;
+ CMD_TRB_ENABLE_SLOT CmdTrb;
+ UINT8 SlotId;
+ UINT8 ParentSlotId;
+ DEVICE_CONTEXT_64 *ParentDeviceContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
CmdTrb.CycleBit = 1;
@@ -1287,14 +1308,15 @@ XhcPeiInitializeDeviceSlot64 ( Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrb,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrb,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
return Status;
}
+
ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
SlotId = (UINT8)EvtTrb->SlotId;
@@ -1312,10 +1334,10 @@ XhcPeiInitializeDeviceSlot64 ( //
InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
ASSERT (InputContext != NULL);
- ASSERT (((UINTN) InputContext & 0x3F) == 0);
+ ASSERT (((UINTN)InputContext & 0x3F) == 0);
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
- Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
+ Xhc->UsbDevContext[SlotId].InputContext = (VOID *)InputContext;
//
// 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
@@ -1339,11 +1361,12 @@ XhcPeiInitializeDeviceSlot64 ( ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);
ASSERT (ParentSlotId != 0);
//
- //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
+ // if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
//
- ParentDeviceContext = (DEVICE_CONTEXT_64 *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
+ ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
- (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
+ (ParentDeviceContext->Slot.TTHubSlotId == 0))
+ {
if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
//
// Full/Low device attached to High speed hub port that isolates the high speed signaling
@@ -1370,9 +1393,9 @@ XhcPeiInitializeDeviceSlot64 ( //
// 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
//
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
- XhcPeiCreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
//
// 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
//
@@ -1385,6 +1408,7 @@ XhcPeiInitializeDeviceSlot64 ( } else {
InputContext->EP[0].MaxPacketSize = 8;
}
+
//
// Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
// 1KB, and Bulk and Isoch endpoints 3KB.
@@ -1401,7 +1425,7 @@ XhcPeiInitializeDeviceSlot64 ( //
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
@@ -1412,7 +1436,7 @@ XhcPeiInitializeDeviceSlot64 ( //
OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
ASSERT (OutputContext != NULL);
- ASSERT (((UINTN) OutputContext & 0x3F) == 0);
+ ASSERT (((UINTN)OutputContext & 0x3F) == 0);
ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
@@ -1424,7 +1448,7 @@ XhcPeiInitializeDeviceSlot64 ( //
// Fill DCBAA with PCI device address
//
- Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
+ Xhc->DCBAA[SlotId] = (UINT64)(UINTN)PhyAddr;
//
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
@@ -1435,20 +1459,20 @@ XhcPeiInitializeDeviceSlot64 ( //
MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbAddr,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (!EFI_ERROR (Status)) {
- DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
+ DeviceAddress = (UINT8)OutputContext->Slot.DeviceAddress;
DEBUG ((DEBUG_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
}
@@ -1457,7 +1481,6 @@ XhcPeiInitializeDeviceSlot64 ( return Status;
}
-
/**
Disable the specified device slot.
@@ -1469,8 +1492,8 @@ XhcPeiInitializeDeviceSlot64 ( **/
EFI_STATUS
XhcPeiDisableSlotCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -1486,7 +1509,8 @@ XhcPeiDisableSlotCmd ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -1507,16 +1531,17 @@ XhcPeiDisableSlotCmd ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -1527,10 +1552,11 @@ XhcPeiDisableSlotCmd ( //
for (Index = 0; Index < 31; Index++) {
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -1549,6 +1575,7 @@ XhcPeiDisableSlotCmd ( if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -1572,8 +1599,8 @@ XhcPeiDisableSlotCmd ( **/
EFI_STATUS
XhcPeiDisableSlotCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId
)
{
EFI_STATUS Status;
@@ -1589,7 +1616,8 @@ XhcPeiDisableSlotCmd64 ( for (Index = 0; Index < 255; Index++) {
if (!Xhc->UsbDevContext[Index + 1].Enabled ||
(Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
- (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
+ (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword))
+ {
continue;
}
@@ -1610,16 +1638,17 @@ XhcPeiDisableSlotCmd64 ( CmdTrbDisSlot.CycleBit = 1;
CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
CmdTrbDisSlot.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbDisSlot,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));
return Status;
}
+
//
// Free the slot's device context entry
//
@@ -1630,10 +1659,11 @@ XhcPeiDisableSlotCmd64 ( //
for (Index = 0; Index < 31; Index++) {
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
- RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
+ RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
if (RingSeg != NULL) {
UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
}
+
FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
}
@@ -1650,8 +1680,9 @@ XhcPeiDisableSlotCmd64 ( }
if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
- UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
+ UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
}
+
//
// Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
// asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
@@ -1677,30 +1708,31 @@ XhcPeiDisableSlotCmd64 ( **/
EFI_STATUS
XhcPeiSetConfigCmd (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINT8 Index;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
-
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINT8 Index;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -1713,22 +1745,22 @@ XhcPeiSetConfigCmd ( MaxDci = 0;
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
NumEp = IfDesc->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcPeiEndpointToDci (EpAddr, Direction);
if (Dci > MaxDci) {
@@ -1759,9 +1791,9 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
break;
@@ -1773,6 +1805,7 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -1801,6 +1834,7 @@ XhcPeiSetConfigCmd ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -1812,7 +1846,7 @@ XhcPeiSetConfigCmd ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -1823,10 +1857,11 @@ XhcPeiSetConfigCmd ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -1842,17 +1877,18 @@ XhcPeiSetConfigCmd ( PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
- PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
InputContext->InputControlContext.Dword2 |= BIT0;
@@ -1861,7 +1897,7 @@ XhcPeiSetConfigCmd ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -1870,13 +1906,14 @@ XhcPeiSetConfigCmd ( DEBUG ((DEBUG_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -1893,30 +1930,31 @@ XhcPeiSetConfigCmd ( **/
EFI_STATUS
XhcPeiSetConfigCmd64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 DeviceSpeed,
- IN USB_CONFIG_DESCRIPTOR *ConfigDesc
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 DeviceSpeed,
+ IN USB_CONFIG_DESCRIPTOR *ConfigDesc
)
{
- EFI_STATUS Status;
- USB_INTERFACE_DESCRIPTOR *IfDesc;
- USB_ENDPOINT_DESCRIPTOR *EpDesc;
- UINT8 Index;
- UINTN NumEp;
- UINTN EpIndex;
- UINT8 EpAddr;
- EFI_USB_DATA_DIRECTION Direction;
- UINT8 Dci;
- UINT8 MaxDci;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- UINT8 Interval;
-
- TRANSFER_RING *EndpointTransferRing;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ EFI_STATUS Status;
+ USB_INTERFACE_DESCRIPTOR *IfDesc;
+ USB_ENDPOINT_DESCRIPTOR *EpDesc;
+ UINT8 Index;
+ UINTN NumEp;
+ UINTN EpIndex;
+ UINT8 EpAddr;
+ EFI_USB_DATA_DIRECTION Direction;
+ UINT8 Dci;
+ UINT8 MaxDci;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ UINT8 Interval;
+
+ TRANSFER_RING *EndpointTransferRing;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+
//
// 4.6.6 Configure Endpoint
//
@@ -1929,22 +1967,22 @@ XhcPeiSetConfigCmd64 ( MaxDci = 0;
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
NumEp = IfDesc->NumEndpoints;
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
- Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
+ EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
+ Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
Dci = XhcPeiEndpointToDci (EpAddr, Direction);
ASSERT (Dci < 32);
@@ -1976,9 +2014,9 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
break;
@@ -1990,6 +2028,7 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+
//
// Get the bInterval from descriptor and init the the interval field of endpoint context.
// Refer to XHCI 1.1 spec section 6.2.3.6.
@@ -2018,6 +2057,7 @@ XhcPeiSetConfigCmd64 ( InputContext->EP[Dci-1].CErr = 3;
InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
}
+
InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
//
@@ -2029,7 +2069,7 @@ XhcPeiSetConfigCmd64 ( // Calculate through the bInterval field of Endpoint descriptor.
//
ASSERT (Interval != 0);
- InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;
+ InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32 ((UINT32)Interval) + 3;
} else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
Interval = EpDesc->Interval;
ASSERT (Interval >= 1 && Interval <= 16);
@@ -2040,10 +2080,11 @@ XhcPeiSetConfigCmd64 ( }
if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
- EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
- Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
- XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
+ Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *)EndpointTransferRing;
+ XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
}
+
break;
case USB_ENDPOINT_CONTROL:
@@ -2059,19 +2100,20 @@ XhcPeiSetConfigCmd64 ( PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
- ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
+ ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
);
PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
- PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
+ PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
- EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN)EpDesc + EpDesc->Length);
+ EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
}
- IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN)IfDesc + IfDesc->Length);
+
+ IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
}
InputContext->InputControlContext.Dword2 |= BIT0;
@@ -2080,7 +2122,7 @@ XhcPeiSetConfigCmd64 ( // configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2089,9 +2131,9 @@ XhcPeiSetConfigCmd64 ( DEBUG ((DEBUG_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
@@ -2100,7 +2142,6 @@ XhcPeiSetConfigCmd64 ( return Status;
}
-
/**
Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
@@ -2113,16 +2154,16 @@ XhcPeiSetConfigCmd64 ( **/
EFI_STATUS
XhcPeiEvaluateContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
- EFI_STATUS Status;
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -2136,7 +2177,7 @@ XhcPeiEvaluateContext ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -2145,13 +2186,14 @@ XhcPeiEvaluateContext ( DEBUG ((DEBUG_INFO, "XhcEvaluateContext: Evaluate context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2167,16 +2209,16 @@ XhcPeiEvaluateContext ( **/
EFI_STATUS
XhcPeiEvaluateContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT32 MaxPacketSize
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT32 MaxPacketSize
)
{
- EFI_STATUS Status;
- CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -2190,7 +2232,7 @@ XhcPeiEvaluateContext64 ( InputContext->EP[0].MaxPacketSize = MaxPacketSize;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -2199,13 +2241,14 @@ XhcPeiEvaluateContext64 ( DEBUG ((DEBUG_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbEvalu,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2223,19 +2266,19 @@ XhcPeiEvaluateContext64 ( **/
EFI_STATUS
XhcPeiConfigHubContext (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT *InputContext;
- DEVICE_CONTEXT *OutputContext;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@@ -2251,14 +2294,14 @@ XhcPeiConfigHubContext ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2267,13 +2310,14 @@ XhcPeiConfigHubContext ( DEBUG ((DEBUG_INFO, "Configure Hub Slot Context\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2291,19 +2335,19 @@ XhcPeiConfigHubContext ( **/
EFI_STATUS
XhcPeiConfigHubContext64 (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 PortNum,
- IN UINT8 TTT,
- IN UINT8 MTT
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 PortNum,
+ IN UINT8 TTT,
+ IN UINT8 MTT
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- INPUT_CONTEXT_64 *InputContext;
- DEVICE_CONTEXT_64 *OutputContext;
- CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
- EFI_PHYSICAL_ADDRESS PhyAddr;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
+ CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
InputContext = Xhc->UsbDevContext[SlotId].InputContext;
@@ -2319,14 +2363,14 @@ XhcPeiConfigHubContext64 ( //
// Copy the slot context from OutputContext to Input context
//
- CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
+ CopyMem (&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
InputContext->Slot.Hub = 1;
InputContext->Slot.PortNum = PortNum;
InputContext->Slot.TTT = TTT;
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -2335,13 +2379,14 @@ XhcPeiConfigHubContext64 ( DEBUG ((DEBUG_INFO, "Configure Hub Slot Context 64\n"));
Status = XhcPeiCmdTransfer (
Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbCfgEP,
XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
}
+
return Status;
}
@@ -2359,14 +2404,14 @@ XhcPeiConfigHubContext64 ( EFI_STATUS
EFIAPI
XhcPeiStopEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
- EFI_STATUS Status;
- EVT_TRB_COMMAND_COMPLETION *EvtTrb;
- CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
+ EFI_STATUS Status;
+ EVT_TRB_COMMAND_COMPLETION *EvtTrb;
+ CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
DEBUG ((DEBUG_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
@@ -2378,13 +2423,13 @@ XhcPeiStopEndpoint ( CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
CmdTrbStopED.EDID = Dci;
CmdTrbStopED.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbStopED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
}
@@ -2405,9 +2450,9 @@ XhcPeiStopEndpoint ( EFI_STATUS
EFIAPI
XhcPeiResetEndpoint (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci
)
{
EFI_STATUS Status;
@@ -2424,13 +2469,13 @@ XhcPeiResetEndpoint ( CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
CmdTrbResetED.EDID = Dci;
CmdTrbResetED.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdTrbResetED,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
}
@@ -2453,10 +2498,10 @@ XhcPeiResetEndpoint ( EFI_STATUS
EFIAPI
XhcPeiSetTrDequeuePointer (
- IN PEI_XHC_DEV *Xhc,
- IN UINT8 SlotId,
- IN UINT8 Dci,
- IN URB *Urb
+ IN PEI_XHC_DEV *Xhc,
+ IN UINT8 SlotId,
+ IN UINT8 Dci,
+ IN URB *Urb
)
{
EFI_STATUS Status;
@@ -2470,20 +2515,20 @@ XhcPeiSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
CmdSetTRDeq.Endpoint = Dci;
CmdSetTRDeq.SlotId = SlotId;
- Status = XhcPeiCmdTransfer (
- Xhc,
- (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
- XHC_GENERIC_TIMEOUT,
- (TRB_TEMPLATE **) (UINTN) &EvtTrb
- );
- if (EFI_ERROR(Status)) {
+ Status = XhcPeiCmdTransfer (
+ Xhc,
+ (TRB_TEMPLATE *)(UINTN)&CmdSetTRDeq,
+ XHC_GENERIC_TIMEOUT,
+ (TRB_TEMPLATE **)(UINTN)&EvtTrb
+ );
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
}
@@ -2503,9 +2548,9 @@ XhcPeiSetTrDequeuePointer ( **/
EFI_STATUS
XhcPeiCheckNewEvent (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing,
- OUT TRB_TEMPLATE **NewEvtTrb
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing,
+ OUT TRB_TEMPLATE **NewEvtTrb
)
{
ASSERT (EvtRing != NULL);
@@ -2520,7 +2565,7 @@ XhcPeiCheckNewEvent ( //
// If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
//
- if ((UINTN) EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
}
@@ -2538,12 +2583,12 @@ XhcPeiCheckNewEvent ( **/
EFI_STATUS
XhcPeiSyncEventRing (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EvtRing
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EvtRing
)
{
- UINTN Index;
- TRB_TEMPLATE *EvtTrb;
+ UINTN Index;
+ TRB_TEMPLATE *EvtTrb;
ASSERT (EvtRing != NULL);
@@ -2560,8 +2605,8 @@ XhcPeiSyncEventRing ( EvtTrb++;
- if ((UINTN) EvtTrb >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
- EvtTrb = EvtRing->EventRingSeg0;
+ if ((UINTN)EvtTrb >= ((UINTN)EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
+ EvtTrb = EvtRing->EventRingSeg0;
EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
}
}
@@ -2584,11 +2629,11 @@ XhcPeiSyncEventRing ( **/
VOID
XhcPeiFreeEventRing (
- IN PEI_XHC_DEV *Xhc,
- IN EVENT_RING *EventRing
+ IN PEI_XHC_DEV *Xhc,
+ IN EVENT_RING *EventRing
)
{
- if(EventRing->EventRingSeg0 == NULL) {
+ if (EventRing->EventRingSeg0 == NULL) {
return;
}
@@ -2612,30 +2657,30 @@ XhcPeiFreeEventRing ( **/
VOID
XhcPeiCreateEventRing (
- IN PEI_XHC_DEV *Xhc,
- OUT EVENT_RING *EventRing
+ IN PEI_XHC_DEV *Xhc,
+ OUT EVENT_RING *EventRing
)
{
- VOID *Buf;
- EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
- UINTN Size;
- EFI_PHYSICAL_ADDRESS ERSTPhy;
- EFI_PHYSICAL_ADDRESS DequeuePhy;
+ VOID *Buf;
+ EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
+ UINTN Size;
+ EFI_PHYSICAL_ADDRESS ERSTPhy;
+ EFI_PHYSICAL_ADDRESS DequeuePhy;
ASSERT (EventRing != NULL);
Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
- EventRing->EventRingSeg0 = Buf;
- EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
- EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
- EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
+ EventRing->EventRingSeg0 = Buf;
+ EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
+ EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
+ EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
@@ -2644,12 +2689,12 @@ XhcPeiCreateEventRing ( EventRing->EventRingCCS = 1;
Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
- Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
+ Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, Size);
- ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
+ ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *)Buf;
EventRing->ERSTBase = ERSTBase;
ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
@@ -2674,12 +2719,12 @@ XhcPeiCreateEventRing ( XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET,
- XHC_LOW_32BIT ((UINT64) (UINTN) DequeuePhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)DequeuePhy)
);
XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERDP_OFFSET + 4,
- XHC_HIGH_32BIT ((UINT64) (UINTN) DequeuePhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)DequeuePhy)
);
//
// Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)
@@ -2690,12 +2735,12 @@ XhcPeiCreateEventRing ( XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET,
- XHC_LOW_32BIT ((UINT64) (UINTN) ERSTPhy)
+ XHC_LOW_32BIT ((UINT64)(UINTN)ERSTPhy)
);
XhcPeiWriteRuntimeReg (
Xhc,
XHC_ERSTBA_OFFSET + 4,
- XHC_HIGH_32BIT ((UINT64) (UINTN) ERSTPhy)
+ XHC_HIGH_32BIT ((UINT64)(UINTN)ERSTPhy)
);
//
// Need set IMAN IE bit to enable the ring interrupt
@@ -2718,8 +2763,8 @@ XhcPeiSyncTrsRing ( IN TRANSFER_RING *TrsRing
)
{
- UINTN Index;
- TRB_TEMPLATE *TrsTrb;
+ UINTN Index;
+ TRB_TEMPLATE *TrsTrb;
ASSERT (TrsRing != NULL);
//
@@ -2732,18 +2777,19 @@ XhcPeiSyncTrsRing ( if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
break;
}
+
TrsTrb++;
- if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
- ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);
+ if ((UINT8)TrsTrb->Type == TRB_TYPE_LINK) {
+ ASSERT (((LINK_TRB *)TrsTrb)->TC != 0);
//
// set cycle bit in Link TRB as normal
//
- ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
+ ((LINK_TRB *)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
//
// Toggle PCS maintained by software
//
TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
- TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
+ TrsTrb = (TRB_TEMPLATE *)TrsRing->RingSeg0; // Use host address
}
}
@@ -2776,9 +2822,9 @@ XhcPeiSyncTrsRing ( **/
VOID
XhcPeiCreateTransferRing (
- IN PEI_XHC_DEV *Xhc,
- IN UINTN TrbNum,
- OUT TRANSFER_RING *TransferRing
+ IN PEI_XHC_DEV *Xhc,
+ IN UINTN TrbNum,
+ OUT TRANSFER_RING *TransferRing
)
{
VOID *Buf;
@@ -2787,28 +2833,28 @@ XhcPeiCreateTransferRing ( Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
ASSERT (Buf != NULL);
- ASSERT (((UINTN) Buf & 0x3F) == 0);
+ ASSERT (((UINTN)Buf & 0x3F) == 0);
ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
- TransferRing->RingSeg0 = Buf;
- TransferRing->TrbNumber = TrbNum;
- TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
- TransferRing->RingPCS = 1;
+ TransferRing->RingSeg0 = Buf;
+ TransferRing->TrbNumber = TrbNum;
+ TransferRing->RingEnqueue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingDequeue = (TRB_TEMPLATE *)TransferRing->RingSeg0;
+ TransferRing->RingPCS = 1;
//
// 4.9.2 Transfer Ring Management
// To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
// point to the first TRB in the ring.
//
- EndTrb = (LINK_TRB *) ((UINTN) Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
+ EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
// Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
//
- EndTrb->TC = 1;
+ EndTrb->TC = 1;
//
// Set Cycle bit as other TRB PCS init value
//
@@ -2823,7 +2869,7 @@ XhcPeiCreateTransferRing ( **/
VOID
XhcPeiInitSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
VOID *Dcbaa;
@@ -2859,7 +2905,7 @@ XhcPeiInitSched ( // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
// Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
//
- Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
+ Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Size);
ASSERT (Dcbaa != NULL);
@@ -2887,13 +2933,13 @@ XhcPeiInitSched ( Xhc->ScratchEntry = ScratchEntry;
ScratchPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
- Xhc->PageSize,
- (VOID **) &ScratchBuf,
- &ScratchPhy,
- &Xhc->ScratchMap
- );
+ Status = UsbHcAllocateAlignedPages (
+ EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
+ Xhc->PageSize,
+ (VOID **)&ScratchBuf,
+ &ScratchPhy,
+ &Xhc->ScratchMap
+ );
ASSERT_EFI_ERROR (Status);
ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
@@ -2904,32 +2950,33 @@ XhcPeiInitSched ( //
for (Index = 0; Index < MaxScratchpadBufs; Index++) {
ScratchEntryPhy = 0;
- Status = UsbHcAllocateAlignedPages (
- EFI_SIZE_TO_PAGES (Xhc->PageSize),
- Xhc->PageSize,
- (VOID **) &ScratchEntry[Index],
- &ScratchEntryPhy,
- (VOID **) &ScratchEntryMap[Index]
- );
+ Status = UsbHcAllocateAlignedPages (
+ EFI_SIZE_TO_PAGES (Xhc->PageSize),
+ Xhc->PageSize,
+ (VOID **)&ScratchEntry[Index],
+ &ScratchEntryPhy,
+ (VOID **)&ScratchEntryMap[Index]
+ );
ASSERT_EFI_ERROR (Status);
- ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize);
+ ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
//
// Fill with the PCI device address
//
*ScratchBuf++ = ScratchEntryPhy;
}
+
//
// The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
// Device Context Base Address Array points to the Scratchpad Buffer Array.
//
- *(UINT64 *) Dcbaa = (UINT64) (UINTN) ScratchPhy;
+ *(UINT64 *)Dcbaa = (UINT64)(UINTN)ScratchPhy;
}
//
// Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
// a 64-bit address pointing to where the Device Context Base Address Array is located.
//
- Xhc->DCBAA = (UINT64 *) (UINTN) Dcbaa;
+ Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
//
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
@@ -2989,11 +3036,11 @@ XhcPeiInitSched ( **/
VOID
XhcPeiFreeSched (
- IN PEI_XHC_DEV *Xhc
+ IN PEI_XHC_DEV *Xhc
)
{
- UINT32 Index;
- UINT64 *ScratchEntry;
+ UINT32 Index;
+ UINT64 *ScratchEntry;
if (Xhc->ScratchBuf != NULL) {
ScratchEntry = Xhc->ScratchEntry;
@@ -3001,8 +3048,9 @@ XhcPeiFreeSched ( //
// Free Scratchpad Buffers
//
- UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
+ UsbHcFreeAlignedPages ((VOID *)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *)Xhc->ScratchEntryMap[Index]);
}
+
//
// Free Scratchpad Buffer Array
//
@@ -3016,7 +3064,7 @@ XhcPeiFreeSched ( Xhc->CmdRing.RingSeg0 = NULL;
}
- XhcPeiFreeEventRing (Xhc,&Xhc->EventRing);
+ XhcPeiFreeEventRing (Xhc, &Xhc->EventRing);
if (Xhc->DCBAA != NULL) {
UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
|