1 files changed, 10 insertions, 10 deletions
diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiHc.h
index 6840c25ece..30128dd5c4 100644
--- a/MdePkg/Include/Protocol/SpiHc.h
+++ b/MdePkg/Include/Protocol/SpiHc.h
@@ -54,7 +54,7 @@ typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;
 
 **/
 typedef EFI_STATUS
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT)(
   IN CONST EFI_SPI_HC_PROTOCOL  *This,
   IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,
   IN BOOLEAN                    PinValue
@@ -87,7 +87,7 @@ typedef EFI_STATUS
 
 **/
 typedef EFI_STATUS
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK)(
   IN CONST EFI_SPI_HC_PROTOCOL  *This,
   IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,
   IN UINT32                      *ClockHz
@@ -116,7 +116,7 @@ typedef EFI_STATUS
 
 **/
 typedef EFI_STATUS
-(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (
+(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION)(
   IN CONST EFI_SPI_HC_PROTOCOL  *This,
   IN EFI_SPI_BUS_TRANSACTION    *BusTransaction
   );
@@ -151,38 +151,38 @@ struct _EFI_SPI_HC_PROTOCOL {
   /// sending) operation.The SPI host controller must support a 1 - bit bus
   /// width.
   ///
-  UINT32                          Attributes;
+  UINT32                             Attributes;
 
   ///
   /// Mask of frame sizes which the SPI host controller supports. Frame size of
   /// N-bits is supported when bit N-1 is set. The host controller must support
   /// a frame size of 8-bits.
   ///
-  UINT32                          FrameSizeSupportMask;
+  UINT32                             FrameSizeSupportMask;
 
   ///
   /// Maximum transfer size in bytes: 1 - Oxffffffff
   ///
-  UINT32                          MaximumTransferBytes;
+  UINT32                             MaximumTransferBytes;
 
   ///
   /// Assert or deassert the SPI chip select.
   ///
-  EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;
+  EFI_SPI_HC_PROTOCOL_CHIP_SELECT    ChipSelect;
 
   ///
   /// Set up the clock generator to produce the correct clock frequency, phase
   /// and polarity for a SPI chip.
   ///
-  EFI_SPI_HC_PROTOCOL_CLOCK       Clock;
+  EFI_SPI_HC_PROTOCOL_CLOCK          Clock;
 
   ///
   /// Perform the SPI transaction on the SPI peripheral using the SPI host
   /// controller.
   ///
-  EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;
+  EFI_SPI_HC_PROTOCOL_TRANSACTION    Transaction;
 };
 
-extern EFI_GUID gEfiSpiHcProtocolGuid;
+extern EFI_GUID  gEfiSpiHcProtocolGuid;
 
 #endif // __SPI_HC_PROTOCOL_H__