diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/ArchitecturalMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 2046 |
1 files changed, 951 insertions, 1095 deletions
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h index 28e71cf713..071a8c689c 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -34,8 +34,7 @@ @endcode
@note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
**/
-#define MSR_IA32_P5_MC_ADDR 0x00000000
-
+#define MSR_IA32_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@@ -53,8 +52,7 @@ @endcode
@note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
**/
-#define MSR_IA32_P5_MC_TYPE 0x00000001
-
+#define MSR_IA32_P5_MC_TYPE 0x00000001
/**
See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
@@ -73,8 +71,7 @@ @endcode
@note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
**/
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
-
+#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
/**
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
@@ -93,8 +90,7 @@ @endcode
@note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
**/
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
-
+#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
/**
Platform ID (RO) The operating system can use this MSR to determine "slot"
@@ -115,7 +111,7 @@ @endcode
@note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
**/
-#define MSR_IA32_PLATFORM_ID 0x00000017
+#define MSR_IA32_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
@@ -125,8 +121,8 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:18;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 18;
///
/// [Bits 52:50] Platform Id (RO) Contains information concerning the
/// intended platform for the processor.
@@ -141,16 +137,15 @@ typedef union { /// 1 1 0 Processor Flag 6
/// 1 1 1 Processor Flag 7
///
- UINT32 PlatformId:3;
- UINT32 Reserved3:11;
+ UINT32 PlatformId : 3;
+ UINT32 Reserved3 : 11;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PLATFORM_ID_REGISTER;
-
/**
06_01H.
@@ -169,7 +164,7 @@ typedef union { @endcode
@note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
**/
-#define MSR_IA32_APIC_BASE 0x0000001B
+#define MSR_IA32_APIC_BASE 0x0000001B
/**
MSR information returned for MSR index #MSR_IA32_APIC_BASE
@@ -179,37 +174,36 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] BSP flag (R/W).
///
- UINT32 BSP:1;
- UINT32 Reserved2:1;
+ UINT32 BSP : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
/// Model 06_1AH.
///
- UINT32 EXTD:1;
+ UINT32 EXTD : 1;
///
/// [Bit 11] APIC Global Enable (R/W).
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bits 31:12] APIC Base (R/W).
///
- UINT32 ApicBase:20;
+ UINT32 ApicBase : 20;
///
/// [Bits 63:32] APIC Base (R/W).
///
- UINT32 ApicBaseHi:32;
+ UINT32 ApicBaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_APIC_BASE_REGISTER;
-
/**
Control Features in Intel 64 Processor (R/W). If any one enumeration
condition for defined bit field holds.
@@ -229,7 +223,7 @@ typedef union { @endcode
@note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
**/
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A
+#define MSR_IA32_FEATURE_CONTROL 0x0000003A
/**
MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
@@ -250,7 +244,7 @@ typedef union { /// is not deasserted. If any one enumeration condition for defined bit
/// field position greater than bit 0 holds.
///
- UINT32 Lock:1;
+ UINT32 Lock : 1;
///
/// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
/// system executive to use VMX in conjunction with SMX to support
@@ -259,61 +253,60 @@ typedef union { /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
/// CPUID.01H:ECX[6] = 1.
///
- UINT32 EnableVmxInsideSmx:1;
+ UINT32 EnableVmxInsideSmx : 1;
///
/// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
/// for system executive that do not require SMX. BIOS must set this bit
/// only when the CPUID function 1 returns VMX feature flag set (ECX bit
/// 5). If CPUID.01H:ECX[5] = 1.
///
- UINT32 EnableVmxOutsideSmx:1;
- UINT32 Reserved1:5;
+ UINT32 EnableVmxOutsideSmx : 1;
+ UINT32 Reserved1 : 5;
///
/// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
/// in the field represents an enable control for a corresponding SENTER
/// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
/// CPUID.01H:ECX[6] = 1.
///
- UINT32 SenterLocalFunctionEnables:7;
+ UINT32 SenterLocalFunctionEnables : 7;
///
/// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
/// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
/// 6] is set. If CPUID.01H:ECX[6] = 1.
///
- UINT32 SenterGlobalEnable:1;
- UINT32 Reserved2:1;
+ UINT32 SenterGlobalEnable : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
/// enable runtime reconfiguration of SGX Launch Control via
/// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
///
- UINT32 SgxLaunchControlEnable:1;
+ UINT32 SgxLaunchControlEnable : 1;
///
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
/// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
///
- UINT32 SgxEnable:1;
- UINT32 Reserved3:1;
+ UINT32 SgxEnable : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 20] LMCE On (R/WL): When set, system software can program the
/// MSRs associated with LMCE to configure delivery of some machine check
/// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
///
- UINT32 LmceOn:1;
- UINT32 Reserved4:11;
- UINT32 Reserved5:32;
+ UINT32 LmceOn : 1;
+ UINT32 Reserved4 : 11;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_FEATURE_CONTROL_REGISTER;
-
/**
Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
@@ -334,8 +327,7 @@ typedef union { @endcode
@note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
**/
-#define MSR_IA32_TSC_ADJUST 0x0000003B
-
+#define MSR_IA32_TSC_ADJUST 0x0000003B
/**
BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
@@ -357,8 +349,7 @@ typedef union { @endcode
@note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
**/
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
-
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
/**
BIOS Update Signature (RO) Returns the microcode update signature following
@@ -380,7 +371,7 @@ typedef union { @endcode
@note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
**/
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
/**
MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
@@ -390,7 +381,7 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:32;
+ UINT32 Reserved : 32;
///
/// [Bits 63:32] Microcode update signature. This field contains the
/// signature of the currently loaded microcode update when read following
@@ -400,15 +391,14 @@ typedef union { /// is no microcode update loaded. Another nonzero value will be the
/// signature.
///
- UINT32 MicrocodeUpdateSignature:32;
+ UINT32 MicrocodeUpdateSignature : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_BIOS_SIGN_ID_REGISTER;
-
/**
IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
@@ -433,13 +423,12 @@ typedef union { MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
@{
**/
-#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
-#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
-#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
-#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
/// @}
-
/**
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
1.
@@ -459,7 +448,7 @@ typedef union { @endcode
@note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
**/
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
+#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
/**
MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
@@ -476,28 +465,28 @@ typedef union { /// if the bit is 0. This bit is cleared when the logical processor is
/// reset.
///
- UINT32 Valid:1;
- UINT32 Reserved1:1;
+ UINT32 Valid : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
/// IA32_VMX_MISC[28].
///
- UINT32 BlockSmi:1;
- UINT32 Reserved2:9;
+ UINT32 BlockSmi : 1;
+ UINT32 Reserved2 : 9;
///
/// [Bits 31:12] MSEG Base (R/W).
///
- UINT32 MsegBase:20;
- UINT32 Reserved3:32;
+ UINT32 MsegBase : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
/**
@@ -512,29 +501,29 @@ typedef struct { /// discover the MSEG revision identifier that a processor uses by reading
/// the VMX capability MSR IA32_VMX_MISC.
//
- UINT32 MsegHeaderRevision;
+ UINT32 MsegHeaderRevision;
///
/// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
/// is the IA-32e mode SMM feature bit. It indicates whether the logical
/// processor will be in IA-32e mode after the STM is activated.
///
- UINT32 MonitorFeatures;
- UINT32 GdtrLimit;
- UINT32 GdtrBaseOffset;
- UINT32 CsSelector;
- UINT32 EipOffset;
- UINT32 EspOffset;
- UINT32 Cr3Offset;
+ UINT32 MonitorFeatures;
+ UINT32 GdtrLimit;
+ UINT32 GdtrBaseOffset;
+ UINT32 CsSelector;
+ UINT32 EipOffset;
+ UINT32 EspOffset;
+ UINT32 Cr3Offset;
///
/// Pad header so total size is 2KB
///
- UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
///
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
///
-#define STM_FEATURES_IA32E 0x1
+#define STM_FEATURES_IA32E 0x1
///
/// @}
///
@@ -555,8 +544,7 @@ typedef struct { @endcode
@note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
**/
-#define MSR_IA32_SMBASE 0x0000009E
-
+#define MSR_IA32_SMBASE 0x0000009E
/**
General Performance Counters (R/W).
@@ -583,17 +571,16 @@ typedef struct { MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
@{
**/
-#define MSR_IA32_PMC0 0x000000C1
-#define MSR_IA32_PMC1 0x000000C2
-#define MSR_IA32_PMC2 0x000000C3
-#define MSR_IA32_PMC3 0x000000C4
-#define MSR_IA32_PMC4 0x000000C5
-#define MSR_IA32_PMC5 0x000000C6
-#define MSR_IA32_PMC6 0x000000C7
-#define MSR_IA32_PMC7 0x000000C8
+#define MSR_IA32_PMC0 0x000000C1
+#define MSR_IA32_PMC1 0x000000C2
+#define MSR_IA32_PMC2 0x000000C3
+#define MSR_IA32_PMC3 0x000000C4
+#define MSR_IA32_PMC4 0x000000C5
+#define MSR_IA32_PMC5 0x000000C6
+#define MSR_IA32_PMC6 0x000000C7
+#define MSR_IA32_PMC7 0x000000C8
/// @}
-
/**
TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
@@ -613,8 +600,7 @@ typedef struct { @endcode
@note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
**/
-#define MSR_IA32_MPERF 0x000000E7
-
+#define MSR_IA32_MPERF 0x000000E7
/**
Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
@@ -635,8 +621,7 @@ typedef struct { @endcode
@note MSR_IA32_APERF is defined as IA32_APERF in SDM.
**/
-#define MSR_IA32_APERF 0x000000E8
-
+#define MSR_IA32_APERF 0x000000E8
/**
MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
@@ -656,7 +641,7 @@ typedef struct { @endcode
@note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
**/
-#define MSR_IA32_MTRRCAP 0x000000FE
+#define MSR_IA32_MTRRCAP 0x000000FE
/**
MSR information returned for MSR index #MSR_IA32_MTRRCAP
@@ -670,34 +655,33 @@ typedef union { /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
/// processor.
///
- UINT32 VCNT:8;
+ UINT32 VCNT : 8;
///
/// [Bit 8] Fixed range MTRRs are supported when set.
///
- UINT32 FIX:1;
- UINT32 Reserved1:1;
+ UINT32 FIX : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 10] WC Supported when set.
///
- UINT32 WC:1;
+ UINT32 WC : 1;
///
/// [Bit 11] SMRR Supported when set.
///
- UINT32 SMRR:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
+ UINT32 SMRR : 1;
+ UINT32 Reserved2 : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
-
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -716,7 +700,7 @@ typedef union { @endcode
@note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
**/
-#define MSR_IA32_SYSENTER_CS 0x00000174
+#define MSR_IA32_SYSENTER_CS 0x00000174
/**
MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
@@ -729,21 +713,20 @@ typedef union { ///
/// [Bits 15:0] CS Selector.
///
- UINT32 CS:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
+ UINT32 CS : 16;
+ UINT32 Reserved1 : 16;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SYSENTER_CS_REGISTER;
-
/**
SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -760,8 +743,7 @@ typedef union { @endcode
@note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
**/
-#define MSR_IA32_SYSENTER_ESP 0x00000175
-
+#define MSR_IA32_SYSENTER_ESP 0x00000175
/**
SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -779,8 +761,7 @@ typedef union { @endcode
@note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
**/
-#define MSR_IA32_SYSENTER_EIP 0x00000176
-
+#define MSR_IA32_SYSENTER_EIP 0x00000176
/**
Global Machine Check Capability (RO). Introduced at Display Family / Display
@@ -800,7 +781,7 @@ typedef union { @endcode
@note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
**/
-#define MSR_IA32_MCG_CAP 0x00000179
+#define MSR_IA32_MCG_CAP 0x00000179
/**
MSR information returned for MSR index #MSR_IA32_MCG_CAP
@@ -813,38 +794,38 @@ typedef union { ///
/// [Bits 7:0] Count: Number of reporting banks.
///
- UINT32 Count:8;
+ UINT32 Count : 8;
///
/// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
///
- UINT32 MCG_CTL_P:1;
+ UINT32 MCG_CTL_P : 1;
///
/// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
/// if this bit is set.
///
- UINT32 MCG_EXT_P:1;
+ UINT32 MCG_EXT_P : 1;
///
/// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
/// Introduced at Display Family / Display Model 06_01H.
///
- UINT32 MCP_CMCI_P:1;
+ UINT32 MCP_CMCI_P : 1;
///
/// [Bit 11] MCG_TES_P: Threshold-based error status register are present
/// if this bit is set.
///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
+ UINT32 MCG_TES_P : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
/// registers present.
///
- UINT32 MCG_EXT_CNT:8;
+ UINT32 MCG_EXT_CNT : 8;
///
/// [Bit 24] MCG_SER_P: The processor supports software error recovery if
/// this bit is set.
///
- UINT32 MCG_SER_P:1;
- UINT32 Reserved2:1;
+ UINT32 MCG_SER_P : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
/// firmware to be invoked when an error is detected so that it may
@@ -853,28 +834,27 @@ typedef union { /// check bank registers. Introduced at Display Family / Display Model
/// 06_3EH.
///
- UINT32 MCG_ELOG_P:1;
+ UINT32 MCG_ELOG_P : 1;
///
/// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
/// state in IA32_MCG_STATUS and associated MSR necessary to configure
/// Local Machine Check Exception (LMCE). Introduced at Display Family /
/// Display Model 06_3EH.
///
- UINT32 MCG_LMCE_P:1;
- UINT32 Reserved3:4;
- UINT32 Reserved4:32;
+ UINT32 MCG_LMCE_P : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_CAP_REGISTER;
-
/**
Global Machine Check Status (R/W0). Introduced at Display Family / Display
Model 06_01H.
@@ -894,7 +874,7 @@ typedef union { @endcode
@note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
**/
-#define MSR_IA32_MCG_STATUS 0x0000017A
+#define MSR_IA32_MCG_STATUS 0x0000017A
/**
MSR information returned for MSR index #MSR_IA32_MCG_STATUS
@@ -908,35 +888,34 @@ typedef union { /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
- UINT32 RIPV:1;
+ UINT32 RIPV : 1;
///
/// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
- UINT32 EIPV:1;
+ UINT32 EIPV : 1;
///
/// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
/// / Display Model 06_01H.
///
- UINT32 MCIP:1;
+ UINT32 MCIP : 1;
///
/// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
///
- UINT32 LMCE_S:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 LMCE_S : 1;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_STATUS_REGISTER;
-
/**
Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
@@ -953,8 +932,7 @@ typedef union { @endcode
@note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
**/
-#define MSR_IA32_MCG_CTL 0x0000017B
-
+#define MSR_IA32_MCG_CTL 0x0000017B
/**
Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
@@ -978,10 +956,10 @@ typedef union { MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
@{
**/
-#define MSR_IA32_PERFEVTSEL0 0x00000186
-#define MSR_IA32_PERFEVTSEL1 0x00000187
-#define MSR_IA32_PERFEVTSEL2 0x00000188
-#define MSR_IA32_PERFEVTSEL3 0x00000189
+#define MSR_IA32_PERFEVTSEL0 0x00000186
+#define MSR_IA32_PERFEVTSEL1 0x00000187
+#define MSR_IA32_PERFEVTSEL2 0x00000188
+#define MSR_IA32_PERFEVTSEL3 0x00000189
/// @}
/**
@@ -996,32 +974,32 @@ typedef union { ///
/// [Bits 7:0] Event Select: Selects a performance event logic unit.
///
- UINT32 EventSelect:8;
+ UINT32 EventSelect : 8;
///
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
/// detect on the selected event logic.
///
- UINT32 UMASK:8;
+ UINT32 UMASK : 8;
///
/// [Bit 16] USR: Counts while in privilege level is not ring 0.
///
- UINT32 USR:1;
+ UINT32 USR : 1;
///
/// [Bit 17] OS: Counts while in privilege level is ring 0.
///
- UINT32 OS:1;
+ UINT32 OS : 1;
///
/// [Bit 18] Edge: Enables edge detection if set.
///
- UINT32 E:1;
+ UINT32 E : 1;
///
/// [Bit 19] PC: enables pin control.
///
- UINT32 PC:1;
+ UINT32 PC : 1;
///
/// [Bit 20] INT: enables interrupt on counter overflow.
///
- UINT32 INT:1;
+ UINT32 INT : 1;
///
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -1029,35 +1007,34 @@ typedef union { /// associated event conditions occurring in the logical processor which
/// programmed the MSR.
///
- UINT32 ANY:1;
+ UINT32 ANY : 1;
///
/// [Bit 22] EN: enables the corresponding performance counter to commence
/// counting when this bit is set.
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bit 23] INV: invert the CMASK.
///
- UINT32 INV:1;
+ UINT32 INV : 1;
///
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
/// performance counter increments each cycle if the event count is
/// greater than or equal to the CMASK.
///
- UINT32 CMASK:8;
- UINT32 Reserved:32;
+ UINT32 CMASK : 8;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
-
/**
Current performance state(P-State) operating point (RO). Introduced at
Display Family / Display Model 0F_03H.
@@ -1076,7 +1053,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
**/
-#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_STATUS 0x00000198
/**
MSR information returned for MSR index #MSR_IA32_PERF_STATUS
@@ -1089,21 +1066,20 @@ typedef union { ///
/// [Bits 15:0] Current performance State Value.
///
- UINT32 State:16;
- UINT32 Reserved1:16;
- UINT32 Reserved2:32;
+ UINT32 State : 16;
+ UINT32 Reserved1 : 16;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_STATUS_REGISTER;
-
/**
(R/W). Introduced at Display Family / Display Model 0F_03H.
@@ -1122,7 +1098,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
**/
-#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_PERF_CTL 0x00000199
/**
MSR information returned for MSR index #MSR_IA32_PERF_CTL
@@ -1135,22 +1111,21 @@ typedef union { ///
/// [Bits 15:0] Target performance State Value.
///
- UINT32 TargetState:16;
- UINT32 Reserved1:16;
+ UINT32 TargetState : 16;
+ UINT32 Reserved1 : 16;
///
/// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
/// (Mobile only).
///
- UINT32 IDA:1;
- UINT32 Reserved2:31;
+ UINT32 IDA : 1;
+ UINT32 Reserved2 : 31;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_CTL_REGISTER;
-
/**
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
Clock Modulation.". If CPUID.01H:EDX[22] = 1.
@@ -1170,7 +1145,7 @@ typedef union { @endcode
@note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
**/
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A
+#define MSR_IA32_CLOCK_MODULATION 0x0000019A
/**
MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
@@ -1184,31 +1159,30 @@ typedef union { /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
/// CPUID.06H:EAX[5] = 1.
///
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;
+ UINT32 ExtendedOnDemandClockModulationDutyCycle : 1;
///
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
/// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
///
- UINT32 OnDemandClockModulationDutyCycle:3;
+ UINT32 OnDemandClockModulationDutyCycle : 3;
///
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 OnDemandClockModulationEnable:1;
- UINT32 Reserved1:27;
- UINT32 Reserved2:32;
+ UINT32 OnDemandClockModulationEnable : 1;
+ UINT32 Reserved1 : 27;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_CLOCK_MODULATION_REGISTER;
-
/**
Thermal Interrupt Control (R/W) Enables and disables the generation of an
interrupt on temperature transitions detected with the processor's thermal
@@ -1230,7 +1204,7 @@ typedef union { @endcode
@note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
**/
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B
+#define MSR_IA32_THERM_INTERRUPT 0x0000019B
/**
MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
@@ -1243,59 +1217,58 @@ typedef union { ///
/// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 HighTempEnable:1;
+ UINT32 HighTempEnable : 1;
///
/// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 LowTempEnable:1;
+ UINT32 LowTempEnable : 1;
///
/// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_Enable:1;
+ UINT32 PROCHOT_Enable : 1;
///
/// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 FORCEPR_Enable:1;
+ UINT32 FORCEPR_Enable : 1;
///
/// [Bit 4] Critical Temperature Interrupt Enable.
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempEnable:1;
- UINT32 Reserved1:3;
+ UINT32 CriticalTempEnable : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold1:7;
+ UINT32 Threshold1 : 7;
///
/// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold1Enable:1;
+ UINT32 Threshold1Enable : 1;
///
/// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold2:7;
+ UINT32 Threshold2 : 7;
///
/// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
- UINT32 Threshold2Enable:1;
+ UINT32 Threshold2Enable : 1;
///
/// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved2:7;
- UINT32 Reserved3:32;
+ UINT32 PowerLimitNotificationEnable : 1;
+ UINT32 Reserved2 : 7;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_THERM_INTERRUPT_REGISTER;
-
/**
Thermal Status Information (RO) Contains status information about the
processor's thermal sensor and automatic thermal monitoring facilities. See
@@ -1315,7 +1288,7 @@ typedef union { @endcode
@note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
**/
-#define MSR_IA32_THERM_STATUS 0x0000019C
+#define MSR_IA32_THERM_STATUS 0x0000019C
/**
MSR information returned for MSR index #MSR_IA32_THERM_STATUS
@@ -1328,95 +1301,94 @@ typedef union { ///
/// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
///
- UINT32 ThermalStatusLog:1;
+ UINT32 ThermalStatusLog : 1;
///
/// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_FORCEPR_Event:1;
+ UINT32 PROCHOT_FORCEPR_Event : 1;
///
/// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
///
- UINT32 PROCHOT_FORCEPR_Log:1;
+ UINT32 PROCHOT_FORCEPR_Log : 1;
///
/// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempStatus:1;
+ UINT32 CriticalTempStatus : 1;
///
/// [Bit 5] Critical Temperature Status log (R/WC0).
/// If CPUID.01H:EDX[22] = 1.
///
- UINT32 CriticalTempStatusLog:1;
+ UINT32 CriticalTempStatusLog : 1;
///
/// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold1Status:1;
+ UINT32 ThermalThreshold1Status : 1;
///
/// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold1Log:1;
+ UINT32 ThermalThreshold1Log : 1;
///
/// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold2Status:1;
+ UINT32 ThermalThreshold2Status : 1;
///
/// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
///
- UINT32 ThermalThreshold2Log:1;
+ UINT32 ThermalThreshold2Log : 1;
///
/// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitStatus:1;
+ UINT32 PowerLimitStatus : 1;
///
/// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
///
- UINT32 PowerLimitLog:1;
+ UINT32 PowerLimitLog : 1;
///
/// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CurrentLimitStatus:1;
+ UINT32 CurrentLimitStatus : 1;
///
/// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CurrentLimitLog:1;
+ UINT32 CurrentLimitLog : 1;
///
/// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CrossDomainLimitStatus:1;
+ UINT32 CrossDomainLimitStatus : 1;
///
/// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
///
- UINT32 CrossDomainLimitLog:1;
+ UINT32 CrossDomainLimitLog : 1;
///
/// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
///
- UINT32 DigitalReadout:7;
- UINT32 Reserved1:4;
+ UINT32 DigitalReadout : 7;
+ UINT32 Reserved1 : 4;
///
/// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
/// 1.
///
- UINT32 ResolutionInDegreesCelsius:4;
+ UINT32 ResolutionInDegreesCelsius : 4;
///
/// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
///
- UINT32 ReadingValid:1;
- UINT32 Reserved2:32;
+ UINT32 ReadingValid : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_THERM_STATUS_REGISTER;
-
/**
Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -1436,7 +1408,7 @@ typedef union { @endcode
@note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_IA32_MISC_ENABLE 0x000001A0
+#define MSR_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
@@ -1451,8 +1423,8 @@ typedef union { /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
/// are disabled. Introduced at Display Family / Display Model 0F_0H.
///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
+ UINT32 FastStrings : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
@@ -1464,35 +1436,35 @@ typedef union { /// field varies with product. See respective tables where default value is
/// listed. Introduced at Display Family / Display Model 0F_0H.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled. Introduced at
/// Display Family / Display Model 0F_0H.
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 3;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
/// Display Family / Display Model 0F_0H.
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
/// Family / Display Model 06_0FH.
///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
+ UINT32 PEBS : 1;
+ UINT32 Reserved4 : 3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
/// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
/// Technology enabled. If CPUID.01H: ECX[7] =1.
///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
+ UINT32 EIST : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
/// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
@@ -1505,8 +1477,8 @@ typedef union { /// set to 0 may generate a #GP exception. Introduced at Display Family /
/// Display Model 0F_03H.
///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
+ UINT32 MONITOR : 1;
+ UINT32 Reserved6 : 3;
///
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
/// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
@@ -1520,15 +1492,15 @@ typedef union { /// depends on the availability of CPUID leaves greater than 2. Introduced
/// at Display Family / Display Model 0F_03H.
///
- UINT32 LimitCpuidMaxval:1;
+ UINT32 LimitCpuidMaxval : 1;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
+ UINT32 xTPR_Message_Disable : 1;
+ UINT32 Reserved7 : 8;
+ UINT32 Reserved8 : 2;
///
/// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
/// feature (XD Bit) is disabled and the XD Bit extended feature flag will
@@ -1539,16 +1511,15 @@ typedef union { /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
/// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
///
- UINT32 XD:1;
- UINT32 Reserved9:29;
+ UINT32 XD : 1;
+ UINT32 Reserved9 : 29;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MISC_ENABLE_REGISTER;
-
/**
Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
@@ -1567,7 +1538,7 @@ typedef union { @endcode
@note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
**/
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
+#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
/**
MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
@@ -1581,21 +1552,20 @@ typedef union { /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
/// performance. 15 indicates preference to maximize energy saving.
///
- UINT32 PowerPolicyPreference:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 PowerPolicyPreference : 4;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
-
/**
Package Thermal Status Information (RO) Contains status information about
the package's thermal sensor. See Section 14.8, "Package Level Thermal
@@ -1615,7 +1585,7 @@ typedef union { @endcode
@note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
**/
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
+#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
/**
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
@@ -1628,70 +1598,69 @@ typedef union { ///
/// [Bit 0] Pkg Thermal Status (RO):.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 1] Pkg Thermal Status Log (R/W):.
///
- UINT32 ThermalStatusLog:1;
+ UINT32 ThermalStatusLog : 1;
///
/// [Bit 2] Pkg PROCHOT # event (RO).
///
- UINT32 PROCHOT_Event:1;
+ UINT32 PROCHOT_Event : 1;
///
/// [Bit 3] Pkg PROCHOT # log (R/WC0).
///
- UINT32 PROCHOT_Log:1;
+ UINT32 PROCHOT_Log : 1;
///
/// [Bit 4] Pkg Critical Temperature Status (RO).
///
- UINT32 CriticalTempStatus:1;
+ UINT32 CriticalTempStatus : 1;
///
/// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
///
- UINT32 CriticalTempStatusLog:1;
+ UINT32 CriticalTempStatusLog : 1;
///
/// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
///
- UINT32 ThermalThreshold1Status:1;
+ UINT32 ThermalThreshold1Status : 1;
///
/// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
///
- UINT32 ThermalThreshold1Log:1;
+ UINT32 ThermalThreshold1Log : 1;
///
/// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
///
- UINT32 ThermalThreshold2Status:1;
+ UINT32 ThermalThreshold2Status : 1;
///
/// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
///
- UINT32 ThermalThreshold2Log:1;
+ UINT32 ThermalThreshold2Log : 1;
///
/// [Bit 10] Pkg Power Limitation Status (RO).
///
- UINT32 PowerLimitStatus:1;
+ UINT32 PowerLimitStatus : 1;
///
/// [Bit 11] Pkg Power Limitation log (R/WC0).
///
- UINT32 PowerLimitLog:1;
- UINT32 Reserved1:4;
+ UINT32 PowerLimitLog : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 22:16] Pkg Digital Readout (RO).
///
- UINT32 DigitalReadout:7;
- UINT32 Reserved2:9;
- UINT32 Reserved3:32;
+ UINT32 DigitalReadout : 7;
+ UINT32 Reserved2 : 9;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
-
/**
Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
an interrupt on temperature transitions detected with the package's thermal
@@ -1713,7 +1682,7 @@ typedef union { @endcode
@note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
**/
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
/**
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
@@ -1726,55 +1695,54 @@ typedef union { ///
/// [Bit 0] Pkg High-Temperature Interrupt Enable.
///
- UINT32 HighTempEnable:1;
+ UINT32 HighTempEnable : 1;
///
/// [Bit 1] Pkg Low-Temperature Interrupt Enable.
///
- UINT32 LowTempEnable:1;
+ UINT32 LowTempEnable : 1;
///
/// [Bit 2] Pkg PROCHOT# Interrupt Enable.
///
- UINT32 PROCHOT_Enable:1;
- UINT32 Reserved1:1;
+ UINT32 PROCHOT_Enable : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Pkg Overheat Interrupt Enable.
///
- UINT32 OverheatEnable:1;
- UINT32 Reserved2:3;
+ UINT32 OverheatEnable : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bits 14:8] Pkg Threshold #1 Value.
///
- UINT32 Threshold1:7;
+ UINT32 Threshold1 : 7;
///
/// [Bit 15] Pkg Threshold #1 Interrupt Enable.
///
- UINT32 Threshold1Enable:1;
+ UINT32 Threshold1Enable : 1;
///
/// [Bits 22:16] Pkg Threshold #2 Value.
///
- UINT32 Threshold2:7;
+ UINT32 Threshold2 : 7;
///
/// [Bit 23] Pkg Threshold #2 Interrupt Enable.
///
- UINT32 Threshold2Enable:1;
+ UINT32 Threshold2Enable : 1;
///
/// [Bit 24] Pkg Power Limit Notification Enable.
///
- UINT32 PowerLimitNotificationEnable:1;
- UINT32 Reserved3:7;
- UINT32 Reserved4:32;
+ UINT32 PowerLimitNotificationEnable : 1;
+ UINT32 Reserved3 : 7;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
-
/**
Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
Model 06_0EH.
@@ -1794,7 +1762,7 @@ typedef union { @endcode
@note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
**/
-#define MSR_IA32_DEBUGCTL 0x000001D9
+#define MSR_IA32_DEBUGCTL 0x000001D9
/**
MSR information returned for MSR index #MSR_IA32_DEBUGCTL
@@ -1809,83 +1777,82 @@ typedef union { /// running trace of the most recent branches taken by the processor in
/// the LBR stack. Introduced at Display Family / Display Model 06_01H.
///
- UINT32 LBR:1;
+ UINT32 LBR : 1;
///
/// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
/// EFLAGS.TF as single-step on branches instead of single-step on
/// instructions. Introduced at Display Family / Display Model 06_01H.
///
- UINT32 BTF:1;
- UINT32 Reserved1:4;
+ UINT32 BTF : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
/// sent. Introduced at Display Family / Display Model 06_0EH.
///
- UINT32 TR:1;
+ UINT32 TR : 1;
///
/// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
/// be logged in a BTS buffer. Introduced at Display Family / Display
/// Model 06_0EH.
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
/// fashion. When this bit is set, an interrupt is generated by the BTS
/// facility when the BTS buffer is full. Introduced at Display Family /
/// Display Model 06_0EH.
///
- UINT32 BTINT:1;
+ UINT32 BTINT : 1;
///
/// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
/// Introduced at Display Family / Display Model 06_0FH.
///
- UINT32 BTS_OFF_OS:1;
+ UINT32 BTS_OFF_OS : 1;
///
/// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
/// Introduced at Display Family / Display Model 06_0FH.
///
- UINT32 BTS_OFF_USR:1;
+ UINT32 BTS_OFF_USR : 1;
///
/// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
/// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 FREEZE_LBRS_ON_PMI:1;
+ UINT32 FREEZE_LBRS_ON_PMI : 1;
///
/// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
/// global counter control MSR are frozen (address 38FH) on a PMI request.
/// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 FREEZE_PERFMON_ON_PMI:1;
+ UINT32 FREEZE_PERFMON_ON_PMI : 1;
///
/// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
/// receive and generate PMI on behalf of the uncore. Introduced at
/// Display Family / Display Model 06_1AH.
///
- UINT32 ENABLE_UNCORE_PMI:1;
+ UINT32 ENABLE_UNCORE_PMI : 1;
///
/// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
/// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
///
- UINT32 FREEZE_WHILE_SMM:1;
+ UINT32 FREEZE_WHILE_SMM : 1;
///
/// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
/// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
///
- UINT32 RTM_DEBUG:1;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
+ UINT32 RTM_DEBUG : 1;
+ UINT32 Reserved2 : 16;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DEBUGCTL_REGISTER;
-
/**
SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
If IA32_MTRRCAP.SMRR[11] = 1.
@@ -1905,7 +1872,7 @@ typedef union { @endcode
@note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
**/
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
+#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
/**
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
@@ -1918,25 +1885,24 @@ typedef union { ///
/// [Bits 7:0] Type. Specifies memory type of the range.
///
- UINT32 Type:8;
- UINT32 Reserved1:4;
+ UINT32 Type : 8;
+ UINT32 Reserved1 : 4;
///
/// [Bits 31:12] PhysBase. SMRR physical Base Address.
///
- UINT32 PhysBase:20;
- UINT32 Reserved2:32;
+ UINT32 PhysBase : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMRR_PHYSBASE_REGISTER;
-
/**
SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@@ -1956,7 +1922,7 @@ typedef union { @endcode
@note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
**/
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
+#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
/**
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
@@ -1966,28 +1932,27 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] Valid Enable range mask.
///
- UINT32 Valid:1;
+ UINT32 Valid : 1;
///
/// [Bits 31:12] PhysMask SMRR address range mask.
///
- UINT32 PhysMask:20;
- UINT32 Reserved2:32;
+ UINT32 PhysMask : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SMRR_PHYSMASK_REGISTER;
-
/**
DCA Capability (R). If CPUID.01H: ECX[18] = 1.
@@ -2003,8 +1968,7 @@ typedef union { @endcode
@note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
**/
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
-
+#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
/**
If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
@@ -2022,8 +1986,7 @@ typedef union { @endcode
@note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
**/
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9
-
+#define MSR_IA32_CPU_DCA_CAP 0x000001F9
/**
DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
@@ -2043,7 +2006,7 @@ typedef union { @endcode
@note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
**/
-#define MSR_IA32_DCA_0_CAP 0x000001FA
+#define MSR_IA32_DCA_0_CAP 0x000001FA
/**
MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
@@ -2057,49 +2020,48 @@ typedef union { /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
/// defeatures are set.
///
- UINT32 DCA_ACTIVE:1;
+ UINT32 DCA_ACTIVE : 1;
///
/// [Bits 2:1] TRANSACTION.
///
- UINT32 TRANSACTION:2;
+ UINT32 TRANSACTION : 2;
///
/// [Bits 6:3] DCA_TYPE.
///
- UINT32 DCA_TYPE:4;
+ UINT32 DCA_TYPE : 4;
///
/// [Bits 10:7] DCA_QUEUE_SIZE.
///
- UINT32 DCA_QUEUE_SIZE:4;
- UINT32 Reserved1:2;
+ UINT32 DCA_QUEUE_SIZE : 4;
+ UINT32 Reserved1 : 2;
///
/// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
/// side-effect.
///
- UINT32 DCA_DELAY:4;
- UINT32 Reserved2:7;
+ UINT32 DCA_DELAY : 4;
+ UINT32 Reserved2 : 7;
///
/// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
///
- UINT32 SW_BLOCK:1;
- UINT32 Reserved3:1;
+ UINT32 SW_BLOCK : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
///
- UINT32 HW_BLOCK:1;
- UINT32 Reserved4:5;
- UINT32 Reserved5:32;
+ UINT32 HW_BLOCK : 1;
+ UINT32 Reserved4 : 5;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DCA_0_CAP_REGISTER;
-
/**
MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
@@ -2129,16 +2091,16 @@ typedef union { MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
@{
**/
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
+#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
+#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
+#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
+#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
+#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
+#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
+#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
+#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
+#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
+#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
/// @}
/**
@@ -2153,12 +2115,12 @@ typedef union { ///
/// [Bits 7:0] Type. Specifies memory type of the range.
///
- UINT32 Type:8;
- UINT32 Reserved1:4;
+ UINT32 Type : 8;
+ UINT32 Reserved1 : 4;
///
/// [Bits 31:12] PhysBase. MTRR physical Base Address.
///
- UINT32 PhysBase:20;
+ UINT32 PhysBase : 20;
///
/// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
@@ -2167,15 +2129,14 @@ typedef union { /// leaf 80000008H, the processor supports 36-bit physical address size,
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
///
- UINT32 PhysBaseHi:32;
+ UINT32 PhysBaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_PHYSBASE_REGISTER;
-
/**
MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
@@ -2205,16 +2166,16 @@ typedef union { MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
@{
**/
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
+#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
+#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
+#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
+#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
+#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
+#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
+#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
+#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
+#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
+#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
/// @}
/**
@@ -2226,15 +2187,15 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] Valid Enable range mask.
///
- UINT32 V:1;
+ UINT32 V : 1;
///
/// [Bits 31:12] PhysMask. MTRR address range mask.
///
- UINT32 PhysMask:20;
+ UINT32 PhysMask : 20;
///
/// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
@@ -2243,15 +2204,14 @@ typedef union { /// leaf 80000008H, the processor supports 36-bit physical address size,
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
///
- UINT32 PhysMaskHi:32;
+ UINT32 PhysMaskHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_PHYSMASK_REGISTER;
-
/**
MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2268,8 +2228,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
-
+#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
/**
MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2287,8 +2246,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
-
+#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
/**
MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2306,8 +2264,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
-
+#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
/**
See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
@@ -2325,8 +2282,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
-
+#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
/**
MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2344,8 +2300,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
-
+#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
/**
MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2363,8 +2318,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
-
+#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
/**
MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2382,8 +2336,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
-
+#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
/**
MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2401,8 +2354,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
-
+#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
/**
MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2420,8 +2372,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
-
+#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
/**
MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2439,8 +2390,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
-
+#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
/**
MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
@@ -2458,8 +2408,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
**/
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
-
+#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
/**
IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
@@ -2479,7 +2428,7 @@ typedef union { @endcode
@note MSR_IA32_PAT is defined as IA32_PAT in SDM.
**/
-#define MSR_IA32_PAT 0x00000277
+#define MSR_IA32_PAT 0x00000277
/**
MSR information returned for MSR index #MSR_IA32_PAT
@@ -2492,51 +2441,50 @@ typedef union { ///
/// [Bits 2:0] PA0.
///
- UINT32 PA0:3;
- UINT32 Reserved1:5;
+ UINT32 PA0 : 3;
+ UINT32 Reserved1 : 5;
///
/// [Bits 10:8] PA1.
///
- UINT32 PA1:3;
- UINT32 Reserved2:5;
+ UINT32 PA1 : 3;
+ UINT32 Reserved2 : 5;
///
/// [Bits 18:16] PA2.
///
- UINT32 PA2:3;
- UINT32 Reserved3:5;
+ UINT32 PA2 : 3;
+ UINT32 Reserved3 : 5;
///
/// [Bits 26:24] PA3.
///
- UINT32 PA3:3;
- UINT32 Reserved4:5;
+ UINT32 PA3 : 3;
+ UINT32 Reserved4 : 5;
///
/// [Bits 34:32] PA4.
///
- UINT32 PA4:3;
- UINT32 Reserved5:5;
+ UINT32 PA4 : 3;
+ UINT32 Reserved5 : 5;
///
/// [Bits 42:40] PA5.
///
- UINT32 PA5:3;
- UINT32 Reserved6:5;
+ UINT32 PA5 : 3;
+ UINT32 Reserved6 : 5;
///
/// [Bits 50:48] PA6.
///
- UINT32 PA6:3;
- UINT32 Reserved7:5;
+ UINT32 PA6 : 3;
+ UINT32 Reserved7 : 5;
///
/// [Bits 58:56] PA7.
///
- UINT32 PA7:3;
- UINT32 Reserved8:5;
+ UINT32 PA7 : 3;
+ UINT32 Reserved8 : 5;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PAT_REGISTER;
-
/**
Provides the programming interface to use corrected MC error signaling
capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
@@ -2588,38 +2536,38 @@ typedef union { MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
@{
**/
-#define MSR_IA32_MC0_CTL2 0x00000280
-#define MSR_IA32_MC1_CTL2 0x00000281
-#define MSR_IA32_MC2_CTL2 0x00000282
-#define MSR_IA32_MC3_CTL2 0x00000283
-#define MSR_IA32_MC4_CTL2 0x00000284
-#define MSR_IA32_MC5_CTL2 0x00000285
-#define MSR_IA32_MC6_CTL2 0x00000286
-#define MSR_IA32_MC7_CTL2 0x00000287
-#define MSR_IA32_MC8_CTL2 0x00000288
-#define MSR_IA32_MC9_CTL2 0x00000289
-#define MSR_IA32_MC10_CTL2 0x0000028A
-#define MSR_IA32_MC11_CTL2 0x0000028B
-#define MSR_IA32_MC12_CTL2 0x0000028C
-#define MSR_IA32_MC13_CTL2 0x0000028D
-#define MSR_IA32_MC14_CTL2 0x0000028E
-#define MSR_IA32_MC15_CTL2 0x0000028F
-#define MSR_IA32_MC16_CTL2 0x00000290
-#define MSR_IA32_MC17_CTL2 0x00000291
-#define MSR_IA32_MC18_CTL2 0x00000292
-#define MSR_IA32_MC19_CTL2 0x00000293
-#define MSR_IA32_MC20_CTL2 0x00000294
-#define MSR_IA32_MC21_CTL2 0x00000295
-#define MSR_IA32_MC22_CTL2 0x00000296
-#define MSR_IA32_MC23_CTL2 0x00000297
-#define MSR_IA32_MC24_CTL2 0x00000298
-#define MSR_IA32_MC25_CTL2 0x00000299
-#define MSR_IA32_MC26_CTL2 0x0000029A
-#define MSR_IA32_MC27_CTL2 0x0000029B
-#define MSR_IA32_MC28_CTL2 0x0000029C
-#define MSR_IA32_MC29_CTL2 0x0000029D
-#define MSR_IA32_MC30_CTL2 0x0000029E
-#define MSR_IA32_MC31_CTL2 0x0000029F
+#define MSR_IA32_MC0_CTL2 0x00000280
+#define MSR_IA32_MC1_CTL2 0x00000281
+#define MSR_IA32_MC2_CTL2 0x00000282
+#define MSR_IA32_MC3_CTL2 0x00000283
+#define MSR_IA32_MC4_CTL2 0x00000284
+#define MSR_IA32_MC5_CTL2 0x00000285
+#define MSR_IA32_MC6_CTL2 0x00000286
+#define MSR_IA32_MC7_CTL2 0x00000287
+#define MSR_IA32_MC8_CTL2 0x00000288
+#define MSR_IA32_MC9_CTL2 0x00000289
+#define MSR_IA32_MC10_CTL2 0x0000028A
+#define MSR_IA32_MC11_CTL2 0x0000028B
+#define MSR_IA32_MC12_CTL2 0x0000028C
+#define MSR_IA32_MC13_CTL2 0x0000028D
+#define MSR_IA32_MC14_CTL2 0x0000028E
+#define MSR_IA32_MC15_CTL2 0x0000028F
+#define MSR_IA32_MC16_CTL2 0x00000290
+#define MSR_IA32_MC17_CTL2 0x00000291
+#define MSR_IA32_MC18_CTL2 0x00000292
+#define MSR_IA32_MC19_CTL2 0x00000293
+#define MSR_IA32_MC20_CTL2 0x00000294
+#define MSR_IA32_MC21_CTL2 0x00000295
+#define MSR_IA32_MC22_CTL2 0x00000296
+#define MSR_IA32_MC23_CTL2 0x00000297
+#define MSR_IA32_MC24_CTL2 0x00000298
+#define MSR_IA32_MC25_CTL2 0x00000299
+#define MSR_IA32_MC26_CTL2 0x0000029A
+#define MSR_IA32_MC27_CTL2 0x0000029B
+#define MSR_IA32_MC28_CTL2 0x0000029C
+#define MSR_IA32_MC29_CTL2 0x0000029D
+#define MSR_IA32_MC30_CTL2 0x0000029E
+#define MSR_IA32_MC31_CTL2 0x0000029F
/// @}
/**
@@ -2634,26 +2582,25 @@ typedef union { ///
/// [Bits 14:0] Corrected error count threshold.
///
- UINT32 CorrectedErrorCountThreshold:15;
- UINT32 Reserved1:15;
+ UINT32 CorrectedErrorCountThreshold : 15;
+ UINT32 Reserved1 : 15;
///
/// [Bit 30] CMCI_EN.
///
- UINT32 CMCI_EN:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:32;
+ UINT32 CMCI_EN : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MC_CTL2_REGISTER;
-
/**
MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
@@ -2672,7 +2619,7 @@ typedef union { @endcode
@note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
**/
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
+#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
/**
MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
@@ -2685,30 +2632,29 @@ typedef union { ///
/// [Bits 2:0] Default Memory Type.
///
- UINT32 Type:3;
- UINT32 Reserved1:7;
+ UINT32 Type : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] Fixed Range MTRR Enable.
///
- UINT32 FE:1;
+ UINT32 FE : 1;
///
/// [Bit 11] MTRR Enable.
///
- UINT32 E:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
+ UINT32 E : 1;
+ UINT32 Reserved2 : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
-
/**
Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
CPUID.0AH: EDX[4:0] > 0.
@@ -2726,8 +2672,7 @@ typedef union { @endcode
@note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
**/
-#define MSR_IA32_FIXED_CTR0 0x00000309
-
+#define MSR_IA32_FIXED_CTR0 0x00000309
/**
Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
@@ -2746,8 +2691,7 @@ typedef union { @endcode
@note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
**/
-#define MSR_IA32_FIXED_CTR1 0x0000030A
-
+#define MSR_IA32_FIXED_CTR1 0x0000030A
/**
Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
@@ -2766,8 +2710,7 @@ typedef union { @endcode
@note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
**/
-#define MSR_IA32_FIXED_CTR2 0x0000030B
-
+#define MSR_IA32_FIXED_CTR2 0x0000030B
/**
RO. If CPUID.01H: ECX[15] = 1.
@@ -2787,7 +2730,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
**/
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_IA32_PERF_CAPABILITIES 0x00000345
/**
MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
@@ -2800,41 +2743,40 @@ typedef union { ///
/// [Bits 5:0] LBR format.
///
- UINT32 LBR_FMT:6;
+ UINT32 LBR_FMT : 6;
///
/// [Bit 6] PEBS Trap.
///
- UINT32 PEBS_TRAP:1;
+ UINT32 PEBS_TRAP : 1;
///
/// [Bit 7] PEBSSaveArchRegs.
///
- UINT32 PEBS_ARCH_REG:1;
+ UINT32 PEBS_ARCH_REG : 1;
///
/// [Bits 11:8] PEBS Record Format.
///
- UINT32 PEBS_REC_FMT:4;
+ UINT32 PEBS_REC_FMT : 4;
///
/// [Bit 12] 1: Freeze while SMM is supported.
///
- UINT32 SMM_FREEZE:1;
+ UINT32 SMM_FREEZE : 1;
///
/// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
///
- UINT32 FW_WRITE:1;
- UINT32 Reserved1:18;
- UINT32 Reserved2:32;
+ UINT32 FW_WRITE : 1;
+ UINT32 Reserved1 : 18;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_CAPABILITIES_REGISTER;
-
/**
Fixed-Function Performance Counter Control (R/W) Counter increments while
the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
@@ -2856,7 +2798,7 @@ typedef union { @endcode
@note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
**/
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
+#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
/**
MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
@@ -2869,11 +2811,11 @@ typedef union { ///
/// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
///
- UINT32 EN0_OS:1;
+ UINT32 EN0_OS : 1;
///
/// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
///
- UINT32 EN0_Usr:1;
+ UINT32 EN0_Usr : 1;
///
/// [Bit 2] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2881,19 +2823,19 @@ typedef union { /// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread0:1;
+ UINT32 AnyThread0 : 1;
///
/// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
///
- UINT32 EN0_PMI:1;
+ UINT32 EN0_PMI : 1;
///
/// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
///
- UINT32 EN1_OS:1;
+ UINT32 EN1_OS : 1;
///
/// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
///
- UINT32 EN1_Usr:1;
+ UINT32 EN1_Usr : 1;
///
/// [Bit 6] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2901,19 +2843,19 @@ typedef union { /// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread1:1;
+ UINT32 AnyThread1 : 1;
///
/// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
///
- UINT32 EN1_PMI:1;
+ UINT32 EN1_PMI : 1;
///
/// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
///
- UINT32 EN2_OS:1;
+ UINT32 EN2_OS : 1;
///
/// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
///
- UINT32 EN2_Usr:1;
+ UINT32 EN2_Usr : 1;
///
/// [Bit 10] AnyThread: When set to 1, it enables counting the associated
/// event conditions occurring across all logical processors sharing a
@@ -2921,25 +2863,24 @@ typedef union { /// associated event conditions occurring in the logical processor which
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
///
- UINT32 AnyThread2:1;
+ UINT32 AnyThread2 : 1;
///
/// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
///
- UINT32 EN2_PMI:1;
- UINT32 Reserved1:20;
- UINT32 Reserved2:32;
+ UINT32 EN2_PMI : 1;
+ UINT32 Reserved1 : 20;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
-
/**
Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
@@ -2957,7 +2898,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
+#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
@@ -2971,87 +2912,86 @@ typedef union { /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
/// EAX[15:8] > 0.
///
- UINT32 Ovf_PMC0:1;
+ UINT32 Ovf_PMC0 : 1;
///
/// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
/// EAX[15:8] > 1.
///
- UINT32 Ovf_PMC1:1;
+ UINT32 Ovf_PMC1 : 1;
///
/// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
/// EAX[15:8] > 2.
///
- UINT32 Ovf_PMC2:1;
+ UINT32 Ovf_PMC2 : 1;
///
/// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
/// EAX[15:8] > 3.
///
- UINT32 Ovf_PMC3:1;
- UINT32 Reserved1:28;
+ UINT32 Ovf_PMC3 : 1;
+ UINT32 Reserved1 : 28;
///
/// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr0:1;
+ UINT32 Ovf_FixedCtr0 : 1;
///
/// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr1:1;
+ UINT32 Ovf_FixedCtr1 : 1;
///
/// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
/// CPUID.0AH: EAX[7:0] > 1.
///
- UINT32 Ovf_FixedCtr2:1;
- UINT32 Reserved2:20;
+ UINT32 Ovf_FixedCtr2 : 1;
+ UINT32 Reserved2 : 20;
///
/// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
/// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
/// && IA32_RTIT_CTL.ToPA = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved3:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved3 : 2;
///
/// [Bit 58] LBR_Frz: LBRs are frozen due to -
/// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
/// CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
/// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
/// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] ASCI: Data in the performance counters in the core PMU may
/// include contributions from the direct or indirect operation intel SGX
/// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
/// EAX[7:0] > 2.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
/// EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] CondChgd: status bits of this register has changed. If
/// CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
-
/**
Global Performance Counter Control (R/W) Counter increments while the result
of ANDing respective enable bit in this MSR with the corresponding OS or USR
@@ -3073,7 +3013,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
+#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
@@ -3081,28 +3021,27 @@ typedef union { typedef union {
///
/// Individual bit fields
-///
+ ///
struct {
///
/// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
/// Enable bitmask. Only the first n-1 bits are valid.
/// Bits n..31 are reserved.
///
- UINT32 EN_PMCn:32;
+ UINT32 EN_PMCn : 32;
///
/// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
/// Enable bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 EN_FIXED_CTRn:32;
+ UINT32 EN_FIXED_CTRn : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
-
/**
Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
0 && CPUID.0AH: EAX[7:0] <= 3.
@@ -3122,7 +3061,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
@@ -3137,41 +3076,40 @@ typedef union { /// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
/// If CPUID.0AH: EDX[4:0] > n.
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:5;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 5;
///
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
/// Display Model 06_2EH.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
-
/**
Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
EAX[7:0] > 3.
@@ -3191,7 +3129,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
@@ -3206,53 +3144,52 @@ typedef union { /// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
/// If CPUID.0AH: EDX[4:0] > n.
/// Clear bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
/// Display Model 06_2EH.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 OvfBuf:1;
+ UINT32 OvfBuf : 1;
///
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
///
- UINT32 CondChgd:1;
+ UINT32 CondChgd : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
-
/**
Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
EAX[7:0] > 3.
@@ -3272,7 +3209,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
+#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
@@ -3287,48 +3224,47 @@ typedef union { /// Set bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 Ovf_PMCn:32;
+ UINT32 Ovf_PMCn : 32;
///
/// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
/// If CPUID.0AH: EAX[7:0] > n.
/// Set bitmask. Only the first n-1 bits are valid.
/// Bits 22:n are reserved.
///
- UINT32 Ovf_FIXED_CTRn:23;
+ UINT32 Ovf_FIXED_CTRn : 23;
///
/// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 Trace_ToPA_PMI:1;
- UINT32 Reserved2:2;
+ UINT32 Trace_ToPA_PMI : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 LBR_Frz:1;
+ UINT32 LBR_Frz : 1;
///
/// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 CTR_Frz:1;
+ UINT32 CTR_Frz : 1;
///
/// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 ASCI:1;
+ UINT32 ASCI : 1;
///
/// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 Ovf_Uncore:1;
+ UINT32 Ovf_Uncore : 1;
///
/// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
///
- UINT32 OvfBuf:1;
- UINT32 Reserved3:1;
+ UINT32 OvfBuf : 1;
+ UINT32 Reserved3 : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
-
/**
Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3.
@@ -3347,7 +3283,7 @@ typedef union { @endcode
@note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
**/
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
+#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
/**
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
@@ -3362,26 +3298,25 @@ typedef union { /// Status bitmask. Only the first n-1 bits are valid.
/// Bits 31:n are reserved.
///
- UINT32 IA32_PERFEVTSELn:32;
+ UINT32 IA32_PERFEVTSELn : 32;
///
/// [Bits 62:32] IA32_FIXED_CTRn in use.
/// If CPUID.0AH: EAX[7:0] > n.
/// Status bitmask. Only the first n-1 bits are valid.
/// Bits 30:n are reserved.
///
- UINT32 IA32_FIXED_CTRn:31;
+ UINT32 IA32_FIXED_CTRn : 31;
///
/// [Bit 63] PMI in use.
///
- UINT32 PMI:1;
+ UINT32 PMI : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
-
/**
PEBS Control (R/W).
@@ -3400,7 +3335,7 @@ typedef union { @endcode
@note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
**/
-#define MSR_IA32_PEBS_ENABLE 0x000003F1
+#define MSR_IA32_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
@@ -3414,25 +3349,24 @@ typedef union { /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
/// Display Model 06_0FH.
///
- UINT32 Enable:1;
+ UINT32 Enable : 1;
///
/// [Bits 3:1] Reserved or Model specific.
///
- UINT32 Reserved1:3;
- UINT32 Reserved2:28;
+ UINT32 Reserved1 : 3;
+ UINT32 Reserved2 : 28;
///
/// [Bits 35:32] Reserved or Model specific.
///
- UINT32 Reserved3:4;
- UINT32 Reserved4:28;
+ UINT32 Reserved3 : 4;
+ UINT32 Reserved4 : 28;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PEBS_ENABLE_REGISTER;
-
/**
MCn_CTL. If IA32_MCG_CAP.CNT > n.
@@ -3478,38 +3412,37 @@ typedef union { MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
@{
**/
-#define MSR_IA32_MC0_CTL 0x00000400
-#define MSR_IA32_MC1_CTL 0x00000404
-#define MSR_IA32_MC2_CTL 0x00000408
-#define MSR_IA32_MC3_CTL 0x0000040C
-#define MSR_IA32_MC4_CTL 0x00000410
-#define MSR_IA32_MC5_CTL 0x00000414
-#define MSR_IA32_MC6_CTL 0x00000418
-#define MSR_IA32_MC7_CTL 0x0000041C
-#define MSR_IA32_MC8_CTL 0x00000420
-#define MSR_IA32_MC9_CTL 0x00000424
-#define MSR_IA32_MC10_CTL 0x00000428
-#define MSR_IA32_MC11_CTL 0x0000042C
-#define MSR_IA32_MC12_CTL 0x00000430
-#define MSR_IA32_MC13_CTL 0x00000434
-#define MSR_IA32_MC14_CTL 0x00000438
-#define MSR_IA32_MC15_CTL 0x0000043C
-#define MSR_IA32_MC16_CTL 0x00000440
-#define MSR_IA32_MC17_CTL 0x00000444
-#define MSR_IA32_MC18_CTL 0x00000448
-#define MSR_IA32_MC19_CTL 0x0000044C
-#define MSR_IA32_MC20_CTL 0x00000450
-#define MSR_IA32_MC21_CTL 0x00000454
-#define MSR_IA32_MC22_CTL 0x00000458
-#define MSR_IA32_MC23_CTL 0x0000045C
-#define MSR_IA32_MC24_CTL 0x00000460
-#define MSR_IA32_MC25_CTL 0x00000464
-#define MSR_IA32_MC26_CTL 0x00000468
-#define MSR_IA32_MC27_CTL 0x0000046C
-#define MSR_IA32_MC28_CTL 0x00000470
+#define MSR_IA32_MC0_CTL 0x00000400
+#define MSR_IA32_MC1_CTL 0x00000404
+#define MSR_IA32_MC2_CTL 0x00000408
+#define MSR_IA32_MC3_CTL 0x0000040C
+#define MSR_IA32_MC4_CTL 0x00000410
+#define MSR_IA32_MC5_CTL 0x00000414
+#define MSR_IA32_MC6_CTL 0x00000418
+#define MSR_IA32_MC7_CTL 0x0000041C
+#define MSR_IA32_MC8_CTL 0x00000420
+#define MSR_IA32_MC9_CTL 0x00000424
+#define MSR_IA32_MC10_CTL 0x00000428
+#define MSR_IA32_MC11_CTL 0x0000042C
+#define MSR_IA32_MC12_CTL 0x00000430
+#define MSR_IA32_MC13_CTL 0x00000434
+#define MSR_IA32_MC14_CTL 0x00000438
+#define MSR_IA32_MC15_CTL 0x0000043C
+#define MSR_IA32_MC16_CTL 0x00000440
+#define MSR_IA32_MC17_CTL 0x00000444
+#define MSR_IA32_MC18_CTL 0x00000448
+#define MSR_IA32_MC19_CTL 0x0000044C
+#define MSR_IA32_MC20_CTL 0x00000450
+#define MSR_IA32_MC21_CTL 0x00000454
+#define MSR_IA32_MC22_CTL 0x00000458
+#define MSR_IA32_MC23_CTL 0x0000045C
+#define MSR_IA32_MC24_CTL 0x00000460
+#define MSR_IA32_MC25_CTL 0x00000464
+#define MSR_IA32_MC26_CTL 0x00000468
+#define MSR_IA32_MC27_CTL 0x0000046C
+#define MSR_IA32_MC28_CTL 0x00000470
/// @}
-
/**
MCn_STATUS. If IA32_MCG_CAP.CNT > n.
@@ -3555,38 +3488,37 @@ typedef union { MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
@{
**/
-#define MSR_IA32_MC0_STATUS 0x00000401
-#define MSR_IA32_MC1_STATUS 0x00000405
-#define MSR_IA32_MC2_STATUS 0x00000409
-#define MSR_IA32_MC3_STATUS 0x0000040D
-#define MSR_IA32_MC4_STATUS 0x00000411
-#define MSR_IA32_MC5_STATUS 0x00000415
-#define MSR_IA32_MC6_STATUS 0x00000419
-#define MSR_IA32_MC7_STATUS 0x0000041D
-#define MSR_IA32_MC8_STATUS 0x00000421
-#define MSR_IA32_MC9_STATUS 0x00000425
-#define MSR_IA32_MC10_STATUS 0x00000429
-#define MSR_IA32_MC11_STATUS 0x0000042D
-#define MSR_IA32_MC12_STATUS 0x00000431
-#define MSR_IA32_MC13_STATUS 0x00000435
-#define MSR_IA32_MC14_STATUS 0x00000439
-#define MSR_IA32_MC15_STATUS 0x0000043D
-#define MSR_IA32_MC16_STATUS 0x00000441
-#define MSR_IA32_MC17_STATUS 0x00000445
-#define MSR_IA32_MC18_STATUS 0x00000449
-#define MSR_IA32_MC19_STATUS 0x0000044D
-#define MSR_IA32_MC20_STATUS 0x00000451
-#define MSR_IA32_MC21_STATUS 0x00000455
-#define MSR_IA32_MC22_STATUS 0x00000459
-#define MSR_IA32_MC23_STATUS 0x0000045D
-#define MSR_IA32_MC24_STATUS 0x00000461
-#define MSR_IA32_MC25_STATUS 0x00000465
-#define MSR_IA32_MC26_STATUS 0x00000469
-#define MSR_IA32_MC27_STATUS 0x0000046D
-#define MSR_IA32_MC28_STATUS 0x00000471
+#define MSR_IA32_MC0_STATUS 0x00000401
+#define MSR_IA32_MC1_STATUS 0x00000405
+#define MSR_IA32_MC2_STATUS 0x00000409
+#define MSR_IA32_MC3_STATUS 0x0000040D
+#define MSR_IA32_MC4_STATUS 0x00000411
+#define MSR_IA32_MC5_STATUS 0x00000415
+#define MSR_IA32_MC6_STATUS 0x00000419
+#define MSR_IA32_MC7_STATUS 0x0000041D
+#define MSR_IA32_MC8_STATUS 0x00000421
+#define MSR_IA32_MC9_STATUS 0x00000425
+#define MSR_IA32_MC10_STATUS 0x00000429
+#define MSR_IA32_MC11_STATUS 0x0000042D
+#define MSR_IA32_MC12_STATUS 0x00000431
+#define MSR_IA32_MC13_STATUS 0x00000435
+#define MSR_IA32_MC14_STATUS 0x00000439
+#define MSR_IA32_MC15_STATUS 0x0000043D
+#define MSR_IA32_MC16_STATUS 0x00000441
+#define MSR_IA32_MC17_STATUS 0x00000445
+#define MSR_IA32_MC18_STATUS 0x00000449
+#define MSR_IA32_MC19_STATUS 0x0000044D
+#define MSR_IA32_MC20_STATUS 0x00000451
+#define MSR_IA32_MC21_STATUS 0x00000455
+#define MSR_IA32_MC22_STATUS 0x00000459
+#define MSR_IA32_MC23_STATUS 0x0000045D
+#define MSR_IA32_MC24_STATUS 0x00000461
+#define MSR_IA32_MC25_STATUS 0x00000465
+#define MSR_IA32_MC26_STATUS 0x00000469
+#define MSR_IA32_MC27_STATUS 0x0000046D
+#define MSR_IA32_MC28_STATUS 0x00000471
/// @}
-
/**
MCn_ADDR. If IA32_MCG_CAP.CNT > n.
@@ -3632,38 +3564,37 @@ typedef union { MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
@{
**/
-#define MSR_IA32_MC0_ADDR 0x00000402
-#define MSR_IA32_MC1_ADDR 0x00000406
-#define MSR_IA32_MC2_ADDR 0x0000040A
-#define MSR_IA32_MC3_ADDR 0x0000040E
-#define MSR_IA32_MC4_ADDR 0x00000412
-#define MSR_IA32_MC5_ADDR 0x00000416
-#define MSR_IA32_MC6_ADDR 0x0000041A
-#define MSR_IA32_MC7_ADDR 0x0000041E
-#define MSR_IA32_MC8_ADDR 0x00000422
-#define MSR_IA32_MC9_ADDR 0x00000426
-#define MSR_IA32_MC10_ADDR 0x0000042A
-#define MSR_IA32_MC11_ADDR 0x0000042E
-#define MSR_IA32_MC12_ADDR 0x00000432
-#define MSR_IA32_MC13_ADDR 0x00000436
-#define MSR_IA32_MC14_ADDR 0x0000043A
-#define MSR_IA32_MC15_ADDR 0x0000043E
-#define MSR_IA32_MC16_ADDR 0x00000442
-#define MSR_IA32_MC17_ADDR 0x00000446
-#define MSR_IA32_MC18_ADDR 0x0000044A
-#define MSR_IA32_MC19_ADDR 0x0000044E
-#define MSR_IA32_MC20_ADDR 0x00000452
-#define MSR_IA32_MC21_ADDR 0x00000456
-#define MSR_IA32_MC22_ADDR 0x0000045A
-#define MSR_IA32_MC23_ADDR 0x0000045E
-#define MSR_IA32_MC24_ADDR 0x00000462
-#define MSR_IA32_MC25_ADDR 0x00000466
-#define MSR_IA32_MC26_ADDR 0x0000046A
-#define MSR_IA32_MC27_ADDR 0x0000046E
-#define MSR_IA32_MC28_ADDR 0x00000472
+#define MSR_IA32_MC0_ADDR 0x00000402
+#define MSR_IA32_MC1_ADDR 0x00000406
+#define MSR_IA32_MC2_ADDR 0x0000040A
+#define MSR_IA32_MC3_ADDR 0x0000040E
+#define MSR_IA32_MC4_ADDR 0x00000412
+#define MSR_IA32_MC5_ADDR 0x00000416
+#define MSR_IA32_MC6_ADDR 0x0000041A
+#define MSR_IA32_MC7_ADDR 0x0000041E
+#define MSR_IA32_MC8_ADDR 0x00000422
+#define MSR_IA32_MC9_ADDR 0x00000426
+#define MSR_IA32_MC10_ADDR 0x0000042A
+#define MSR_IA32_MC11_ADDR 0x0000042E
+#define MSR_IA32_MC12_ADDR 0x00000432
+#define MSR_IA32_MC13_ADDR 0x00000436
+#define MSR_IA32_MC14_ADDR 0x0000043A
+#define MSR_IA32_MC15_ADDR 0x0000043E
+#define MSR_IA32_MC16_ADDR 0x00000442
+#define MSR_IA32_MC17_ADDR 0x00000446
+#define MSR_IA32_MC18_ADDR 0x0000044A
+#define MSR_IA32_MC19_ADDR 0x0000044E
+#define MSR_IA32_MC20_ADDR 0x00000452
+#define MSR_IA32_MC21_ADDR 0x00000456
+#define MSR_IA32_MC22_ADDR 0x0000045A
+#define MSR_IA32_MC23_ADDR 0x0000045E
+#define MSR_IA32_MC24_ADDR 0x00000462
+#define MSR_IA32_MC25_ADDR 0x00000466
+#define MSR_IA32_MC26_ADDR 0x0000046A
+#define MSR_IA32_MC27_ADDR 0x0000046E
+#define MSR_IA32_MC28_ADDR 0x00000472
/// @}
-
/**
MCn_MISC. If IA32_MCG_CAP.CNT > n.
@@ -3709,38 +3640,37 @@ typedef union { MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
@{
**/
-#define MSR_IA32_MC0_MISC 0x00000403
-#define MSR_IA32_MC1_MISC 0x00000407
-#define MSR_IA32_MC2_MISC 0x0000040B
-#define MSR_IA32_MC3_MISC 0x0000040F
-#define MSR_IA32_MC4_MISC 0x00000413
-#define MSR_IA32_MC5_MISC 0x00000417
-#define MSR_IA32_MC6_MISC 0x0000041B
-#define MSR_IA32_MC7_MISC 0x0000041F
-#define MSR_IA32_MC8_MISC 0x00000423
-#define MSR_IA32_MC9_MISC 0x00000427
-#define MSR_IA32_MC10_MISC 0x0000042B
-#define MSR_IA32_MC11_MISC 0x0000042F
-#define MSR_IA32_MC12_MISC 0x00000433
-#define MSR_IA32_MC13_MISC 0x00000437
-#define MSR_IA32_MC14_MISC 0x0000043B
-#define MSR_IA32_MC15_MISC 0x0000043F
-#define MSR_IA32_MC16_MISC 0x00000443
-#define MSR_IA32_MC17_MISC 0x00000447
-#define MSR_IA32_MC18_MISC 0x0000044B
-#define MSR_IA32_MC19_MISC 0x0000044F
-#define MSR_IA32_MC20_MISC 0x00000453
-#define MSR_IA32_MC21_MISC 0x00000457
-#define MSR_IA32_MC22_MISC 0x0000045B
-#define MSR_IA32_MC23_MISC 0x0000045F
-#define MSR_IA32_MC24_MISC 0x00000463
-#define MSR_IA32_MC25_MISC 0x00000467
-#define MSR_IA32_MC26_MISC 0x0000046B
-#define MSR_IA32_MC27_MISC 0x0000046F
-#define MSR_IA32_MC28_MISC 0x00000473
+#define MSR_IA32_MC0_MISC 0x00000403
+#define MSR_IA32_MC1_MISC 0x00000407
+#define MSR_IA32_MC2_MISC 0x0000040B
+#define MSR_IA32_MC3_MISC 0x0000040F
+#define MSR_IA32_MC4_MISC 0x00000413
+#define MSR_IA32_MC5_MISC 0x00000417
+#define MSR_IA32_MC6_MISC 0x0000041B
+#define MSR_IA32_MC7_MISC 0x0000041F
+#define MSR_IA32_MC8_MISC 0x00000423
+#define MSR_IA32_MC9_MISC 0x00000427
+#define MSR_IA32_MC10_MISC 0x0000042B
+#define MSR_IA32_MC11_MISC 0x0000042F
+#define MSR_IA32_MC12_MISC 0x00000433
+#define MSR_IA32_MC13_MISC 0x00000437
+#define MSR_IA32_MC14_MISC 0x0000043B
+#define MSR_IA32_MC15_MISC 0x0000043F
+#define MSR_IA32_MC16_MISC 0x00000443
+#define MSR_IA32_MC17_MISC 0x00000447
+#define MSR_IA32_MC18_MISC 0x0000044B
+#define MSR_IA32_MC19_MISC 0x0000044F
+#define MSR_IA32_MC20_MISC 0x00000453
+#define MSR_IA32_MC21_MISC 0x00000457
+#define MSR_IA32_MC22_MISC 0x0000045B
+#define MSR_IA32_MC23_MISC 0x0000045F
+#define MSR_IA32_MC24_MISC 0x00000463
+#define MSR_IA32_MC25_MISC 0x00000467
+#define MSR_IA32_MC26_MISC 0x0000046B
+#define MSR_IA32_MC27_MISC 0x0000046F
+#define MSR_IA32_MC28_MISC 0x00000473
/// @}
-
/**
Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
VMX Information.". If CPUID.01H:ECX.[5] = 1.
@@ -3757,7 +3687,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
**/
-#define MSR_IA32_VMX_BASIC 0x00000480
+#define MSR_IA32_VMX_BASIC 0x00000480
/**
MSR information returned for MSR index #MSR_IA32_VMX_BASIC
@@ -3777,15 +3707,15 @@ typedef union { /// processors produced prior to this change, bit 31 of this MSR was read
/// as 0.
///
- UINT32 VmcsRevisonId:31;
- UINT32 MustBeZero:1;
+ UINT32 VmcsRevisonId : 31;
+ UINT32 MustBeZero : 1;
///
/// [Bit 44:32] Reports the number of bytes that software should allocate
/// for the VMXON region and any VMCS region. It is a value greater than
/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
///
- UINT32 VmcsSize:13;
- UINT32 Reserved1:3;
+ UINT32 VmcsSize : 13;
+ UINT32 Reserved1 : 3;
///
/// [Bit 48] Indicates the width of the physical addresses that may be used
/// for the VMXON region, each VMCS, and data structures referenced by
@@ -3798,13 +3728,13 @@ typedef union { /// @note On processors that support Intel 64 architecture, the pointer
/// must not set bits beyond the processor's physical address width.
///
- UINT32 VmcsAddressWidth:1;
+ UINT32 VmcsAddressWidth : 1;
///
/// [Bit 49] If bit 49 is read as 1, the logical processor supports the
/// dual-monitor treatment of system-management interrupts and
/// system-management mode. See Section 34.15 for details of this treatment.
///
- UINT32 DualMonitor:1;
+ UINT32 DualMonitor : 1;
///
/// [Bit 53:50] report the memory type that should be used for the VMCS,
/// for data structures referenced by pointers in the VMCS (I/O bitmaps,
@@ -3830,14 +3760,14 @@ typedef union { /// performance of software accesses to those structures to suffer.
///
///
- UINT32 MemoryType:4;
+ UINT32 MemoryType : 4;
///
/// [Bit 54] If bit 54 is read as 1, the processor reports information in
/// the VM-exit instruction-information field on VM exitsdue to execution
/// of the INS and OUTS instructions (see Section 27.2.4). This reporting
/// is done only if this bit is read as 1.
///
- UINT32 InsOutsReporting:1;
+ UINT32 InsOutsReporting : 1;
///
/// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
/// be cleared to 0. See Appendix A.2 for details. It also reports support
@@ -3846,13 +3776,13 @@ typedef union { /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
/// Appendix A.4, and Appendix A.5 for details.
///
- UINT32 VmxControls:1;
- UINT32 Reserved2:8;
+ UINT32 VmxControls : 1;
+ UINT32 Reserved2 : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_VMX_BASIC_REGISTER;
///
@@ -3864,7 +3794,6 @@ typedef union { /// @}
///
-
/**
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
@@ -3881,8 +3810,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
-
+#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
/**
Capability Reporting Register of Primary Processor-based VM-execution
@@ -3901,8 +3829,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
-
+#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
/**
Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
@@ -3920,8 +3847,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
**/
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
-
+#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
/**
Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
@@ -3939,8 +3865,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
**/
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
-
+#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
/**
Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
@@ -3958,7 +3883,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
**/
-#define MSR_IA32_VMX_MISC 0x00000485
+#define MSR_IA32_VMX_MISC 0x00000485
/**
MSR information returned for MSR index #IA32_VMX_MISC
@@ -3974,27 +3899,27 @@ typedef union { /// Specifically, the VMX-preemption timer (if it is active) counts down by
/// 1 every time bit X in the TSC changes due to a TSC increment.
///
- UINT32 VmxTimerRatio:5;
+ UINT32 VmxTimerRatio : 5;
///
/// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
/// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
/// details. This bit is read as 1 on any logical processor that supports
/// the 1-setting of the "unrestricted guest" VM-execution control.
///
- UINT32 VmExitEferLma:1;
+ UINT32 VmExitEferLma : 1;
///
/// [Bit 6] reports (if set) the support for activity state 1 (HLT).
///
- UINT32 HltActivityStateSupported:1;
+ UINT32 HltActivityStateSupported : 1;
///
/// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
///
- UINT32 ShutdownActivityStateSupported:1;
+ UINT32 ShutdownActivityStateSupported : 1;
///
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
///
- UINT32 WaitForSipiActivityStateSupported:1;
- UINT32 Reserved1:5;
+ UINT32 WaitForSipiActivityStateSupported : 1;
+ UINT32 Reserved1 : 5;
///
/// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
/// in VMX operation. If the processor supports Intel PT but does not allow
@@ -4004,19 +3929,19 @@ typedef union { /// operation) using the WRMSR instruction causes a general-protection
/// exception.
///
- UINT32 ProcessorTraceSupported:1;
+ UINT32 ProcessorTraceSupported : 1;
///
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
/// See Section 34.15.6.3.
///
- UINT32 SmBaseMsrSupported:1;
+ UINT32 SmBaseMsrSupported : 1;
///
/// [Bits 24:16] Indicate the number of CR3-target values supported by the
/// processor. This number is a value between 0 and 256, inclusive (bit 24
/// is set if and only if bits 23:16 are clear).
///
- UINT32 NumberOfCr3TargetValues:9;
+ UINT32 NumberOfCr3TargetValues : 9;
///
/// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
/// number of MSRs that should appear in the VM-exit MSR-store list, the
@@ -4026,39 +3951,38 @@ typedef union { /// limit is exceeded, undefined processor behavior may result (including a
/// machine check during the VMX transition).
///
- UINT32 MsrStoreListMaximum:3;
+ UINT32 MsrStoreListMaximum : 3;
///
/// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
/// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
/// (see Section 34.14.4).
///
- UINT32 BlockSmiSupported:1;
+ UINT32 BlockSmiSupported : 1;
///
/// [Bit 29] read as 1, software can use VMWRITE to write to any supported
/// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
/// information fields.
///
- UINT32 VmWriteSupported:1;
+ UINT32 VmWriteSupported : 1;
///
/// [Bit 30] If read as 1, VM entry allows injection of a software
/// interrupt, software exception, or privileged software exception with an
/// instruction length of 0.
///
- UINT32 VmInjectSupported:1;
- UINT32 Reserved2:1;
+ UINT32 VmInjectSupported : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
/// processor.
///
- UINT32 MsegRevisionIdentifier:32;
+ UINT32 MsegRevisionIdentifier : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_VMX_MISC_REGISTER;
-
/**
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
"VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
@@ -4075,8 +3999,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
**/
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
-
+#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
/**
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
@@ -4094,8 +4017,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
**/
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
-
+#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
/**
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
@@ -4113,8 +4035,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
**/
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
-
+#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
/**
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
@@ -4132,8 +4053,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
**/
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
-
+#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
/**
Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
@@ -4151,8 +4071,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
**/
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
-
+#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
/**
Capability Reporting Register of Secondary Processor-based VM-execution
@@ -4171,8 +4090,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
**/
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
-
+#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
/**
Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
@@ -4191,8 +4109,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
**/
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
-
+#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
/**
Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
@@ -4211,8 +4128,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
/**
Capability Reporting Register of Primary Processor-based VM-execution Flex
@@ -4231,8 +4147,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
-
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
/**
Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
@@ -4250,8 +4165,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
-
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
/**
Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
@@ -4269,8 +4183,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
**/
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
-
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
/**
Capability Reporting Register of VMfunction Controls (R/O). If(
@@ -4288,8 +4201,7 @@ typedef union { @endcode
@note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
**/
-#define MSR_IA32_VMX_VMFUNC 0x00000491
-
+#define MSR_IA32_VMX_VMFUNC 0x00000491
/**
Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
@@ -4316,17 +4228,16 @@ typedef union { MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
@{
**/
-#define MSR_IA32_A_PMC0 0x000004C1
-#define MSR_IA32_A_PMC1 0x000004C2
-#define MSR_IA32_A_PMC2 0x000004C3
-#define MSR_IA32_A_PMC3 0x000004C4
-#define MSR_IA32_A_PMC4 0x000004C5
-#define MSR_IA32_A_PMC5 0x000004C6
-#define MSR_IA32_A_PMC6 0x000004C7
-#define MSR_IA32_A_PMC7 0x000004C8
+#define MSR_IA32_A_PMC0 0x000004C1
+#define MSR_IA32_A_PMC1 0x000004C2
+#define MSR_IA32_A_PMC2 0x000004C3
+#define MSR_IA32_A_PMC3 0x000004C4
+#define MSR_IA32_A_PMC4 0x000004C5
+#define MSR_IA32_A_PMC5 0x000004C6
+#define MSR_IA32_A_PMC6 0x000004C7
+#define MSR_IA32_A_PMC7 0x000004C8
/// @}
-
/**
(R/W). If IA32_MCG_CAP.LMCE_P =1.
@@ -4345,7 +4256,7 @@ typedef union { @endcode
@note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
**/
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0
+#define MSR_IA32_MCG_EXT_CTL 0x000004D0
/**
MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
@@ -4358,21 +4269,20 @@ typedef union { ///
/// [Bit 0] LMCE_EN.
///
- UINT32 LMCE_EN:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 LMCE_EN : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_MCG_EXT_CTL_REGISTER;
-
/**
Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
ECX=0H): EBX[2] = 1.
@@ -4391,7 +4301,7 @@ typedef union { @endcode
@note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
**/
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500
+#define MSR_IA32_SGX_SVN_STATUS 0x00000500
/**
MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
@@ -4405,27 +4315,26 @@ typedef union { /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
- UINT32 Lock:1;
- UINT32 Reserved1:15;
+ UINT32 Lock : 1;
+ UINT32 Reserved1 : 15;
///
/// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
- UINT32 SGX_SVN_SINIT:8;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
+ UINT32 SGX_SVN_SINIT : 8;
+ UINT32 Reserved2 : 8;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_SGX_SVN_STATUS_REGISTER;
-
/**
Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
&& ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
@@ -4446,7 +4355,7 @@ typedef union { @endcode
@note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
**/
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
/**
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
@@ -4456,23 +4365,22 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:7;
+ UINT32 Reserved : 7;
///
/// [Bits 31:7] Base physical address.
///
- UINT32 Base:25;
+ UINT32 Base : 25;
///
/// [Bits 63:32] Base physical address.
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
-
/**
Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
@@ -4493,7 +4401,7 @@ typedef union { @endcode
@note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
**/
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
+#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
/**
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
@@ -4503,20 +4411,20 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:7;
+ UINT32 Reserved : 7;
///
/// [Bits 31:7] MaskOrTableOffset.
///
- UINT32 MaskOrTableOffset:25;
+ UINT32 MaskOrTableOffset : 25;
///
/// [Bits 63:32] Output Offset.
///
- UINT32 OutputOffset:32;
+ UINT32 OutputOffset : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
/**
@@ -4530,24 +4438,24 @@ typedef union { ///
/// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 END:1;
- UINT32 Reserved1:1;
+ UINT32 END : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 INT:1;
- UINT32 Reserved2:1;
+ UINT32 INT : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 STOP:1;
- UINT32 Reserved3:1;
+ UINT32 STOP : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 6:9] Indicates the size of the associated output region. See Section
/// 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 Size:4;
- UINT32 Reserved4:2;
+ UINT32 Size : 4;
+ UINT32 Reserved4 : 2;
///
/// [Bit 12:31] Output Region Base Physical Address low part.
/// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
@@ -4557,7 +4465,7 @@ typedef union { /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 Base:20;
+ UINT32 Base : 20;
///
/// [Bit 32:63] Output Region Base Physical Address high part.
/// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
@@ -4567,12 +4475,12 @@ typedef union { /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} RTIT_TOPA_TABLE_ENTRY;
///
@@ -4615,7 +4523,7 @@ typedef enum { @endcode
@note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
**/
-#define MSR_IA32_RTIT_CTL 0x00000570
+#define MSR_IA32_RTIT_CTL 0x00000570
/**
MSR information returned for MSR index #MSR_IA32_RTIT_CTL
@@ -4628,99 +4536,98 @@ typedef union { ///
/// [Bit 0] TraceEn.
///
- UINT32 TraceEn:1;
+ UINT32 TraceEn : 1;
///
/// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 CYCEn:1;
+ UINT32 CYCEn : 1;
///
/// [Bit 2] OS.
///
- UINT32 OS:1;
+ UINT32 OS : 1;
///
/// [Bit 3] User.
///
- UINT32 User:1;
+ UINT32 User : 1;
///
/// [Bit 4] PwrEvtEn.
///
- UINT32 PwrEvtEn:1;
+ UINT32 PwrEvtEn : 1;
///
/// [Bit 5] FUPonPTW.
///
- UINT32 FUPonPTW:1;
+ UINT32 FUPonPTW : 1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
- UINT32 FabricEn:1;
+ UINT32 FabricEn : 1;
///
/// [Bit 7] CR3 filter.
///
- UINT32 CR3:1;
+ UINT32 CR3 : 1;
///
/// [Bit 8] ToPA.
///
- UINT32 ToPA:1;
+ UINT32 ToPA : 1;
///
/// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
///
- UINT32 MTCEn:1;
+ UINT32 MTCEn : 1;
///
/// [Bit 10] TSCEn.
///
- UINT32 TSCEn:1;
+ UINT32 TSCEn : 1;
///
/// [Bit 11] DisRETC.
///
- UINT32 DisRETC:1;
+ UINT32 DisRETC : 1;
///
/// [Bit 12] PTWEn.
///
- UINT32 PTWEn:1;
+ UINT32 PTWEn : 1;
///
/// [Bit 13] BranchEn.
///
- UINT32 BranchEn:1;
+ UINT32 BranchEn : 1;
///
/// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
///
- UINT32 MTCFreq:4;
- UINT32 Reserved3:1;
+ UINT32 MTCFreq : 4;
+ UINT32 Reserved3 : 1;
///
/// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 CYCThresh:4;
- UINT32 Reserved4:1;
+ UINT32 CYCThresh : 4;
+ UINT32 Reserved4 : 1;
///
/// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
///
- UINT32 PSBFreq:4;
- UINT32 Reserved5:4;
+ UINT32 PSBFreq : 4;
+ UINT32 Reserved5 : 4;
///
/// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
///
- UINT32 ADDR0_CFG:4;
+ UINT32 ADDR0_CFG : 4;
///
/// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
///
- UINT32 ADDR1_CFG:4;
+ UINT32 ADDR1_CFG : 4;
///
/// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
///
- UINT32 ADDR2_CFG:4;
+ UINT32 ADDR2_CFG : 4;
///
/// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
///
- UINT32 ADDR3_CFG:4;
- UINT32 Reserved6:16;
+ UINT32 ADDR3_CFG : 4;
+ UINT32 Reserved6 : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_CTL_REGISTER;
-
/**
Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
@@ -4739,7 +4646,7 @@ typedef union { @endcode
@note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
**/
-#define MSR_IA32_RTIT_STATUS 0x00000571
+#define MSR_IA32_RTIT_STATUS 0x00000571
/**
MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
@@ -4753,38 +4660,37 @@ typedef union { /// [Bit 0] FilterEn, (writes ignored).
/// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
///
- UINT32 FilterEn:1;
+ UINT32 FilterEn : 1;
///
/// [Bit 1] ContexEn, (writes ignored).
///
- UINT32 ContexEn:1;
+ UINT32 ContexEn : 1;
///
/// [Bit 2] TriggerEn, (writes ignored).
///
- UINT32 TriggerEn:1;
- UINT32 Reserved1:1;
+ UINT32 TriggerEn : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Error.
///
- UINT32 Error:1;
+ UINT32 Error : 1;
///
/// [Bit 5] Stopped.
///
- UINT32 Stopped:1;
- UINT32 Reserved2:26;
+ UINT32 Stopped : 1;
+ UINT32 Reserved2 : 26;
///
/// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
///
- UINT32 PacketByteCnt:17;
- UINT32 Reserved3:15;
+ UINT32 PacketByteCnt : 17;
+ UINT32 Reserved3 : 15;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_STATUS_REGISTER;
-
/**
Trace Filter CR3 Match Register (R/W).
If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
@@ -4804,7 +4710,7 @@ typedef union { @endcode
@note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
**/
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
/**
MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
@@ -4814,23 +4720,22 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:5;
+ UINT32 Reserved : 5;
///
/// [Bits 31:5] CR3[63:5] value to match.
///
- UINT32 Cr3:27;
+ UINT32 Cr3 : 27;
///
/// [Bits 63:32] CR3[63:5] value to match.
///
- UINT32 Cr3Hi:32;
+ UINT32 Cr3Hi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
-
/**
Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
@@ -4853,13 +4758,12 @@ typedef union { MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
@{
**/
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586
+#define MSR_IA32_RTIT_ADDR0_A 0x00000580
+#define MSR_IA32_RTIT_ADDR1_A 0x00000582
+#define MSR_IA32_RTIT_ADDR2_A 0x00000584
+#define MSR_IA32_RTIT_ADDR3_A 0x00000586
/// @}
-
/**
Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
@@ -4882,13 +4786,12 @@ typedef union { MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
@{
**/
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587
+#define MSR_IA32_RTIT_ADDR0_B 0x00000581
+#define MSR_IA32_RTIT_ADDR1_B 0x00000583
+#define MSR_IA32_RTIT_ADDR2_B 0x00000585
+#define MSR_IA32_RTIT_ADDR3_B 0x00000587
/// @}
-
/**
MSR information returned for MSR indexes
#MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
@@ -4902,23 +4805,22 @@ typedef union { ///
/// [Bits 31:0] Virtual Address.
///
- UINT32 VirtualAddress:32;
+ UINT32 VirtualAddress : 32;
///
/// [Bits 47:32] Virtual Address.
///
- UINT32 VirtualAddressHi:16;
+ UINT32 VirtualAddressHi : 16;
///
/// [Bits 63:48] SignExt_VA.
///
- UINT32 SignExt_VA:16;
+ UINT32 SignExt_VA : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_RTIT_ADDR_REGISTER;
-
/**
DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
@@ -4941,8 +4843,7 @@ typedef union { @endcode
@note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
**/
-#define MSR_IA32_DS_AREA 0x00000600
-
+#define MSR_IA32_DS_AREA 0x00000600
/**
TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
@@ -4961,8 +4862,7 @@ typedef union { @endcode
@note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
**/
-#define MSR_IA32_TSC_DEADLINE 0x000006E0
-
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
/**
Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
@@ -4982,7 +4882,7 @@ typedef union { @endcode
@note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
**/
-#define MSR_IA32_PM_ENABLE 0x00000770
+#define MSR_IA32_PM_ENABLE 0x00000770
/**
MSR information returned for MSR index #MSR_IA32_PM_ENABLE
@@ -4996,21 +4896,20 @@ typedef union { /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 HWP_ENABLE:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HWP_ENABLE : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PM_ENABLE_REGISTER;
-
/**
HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
@@ -5028,7 +4927,7 @@ typedef union { @endcode
@note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
**/
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771
+#define MSR_IA32_HWP_CAPABILITIES 0x00000771
/**
MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
@@ -5042,35 +4941,34 @@ typedef union { /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Highest_Performance:8;
+ UINT32 Highest_Performance : 8;
///
/// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Guaranteed_Performance:8;
+ UINT32 Guaranteed_Performance : 8;
///
/// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Most_Efficient_Performance:8;
+ UINT32 Most_Efficient_Performance : 8;
///
/// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Lowest_Performance:8;
- UINT32 Reserved:32;
+ UINT32 Lowest_Performance : 8;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_CAPABILITIES_REGISTER;
-
/**
Power Management Control Hints for All Logical Processors in a Package
(R/W). If CPUID.06H:EAX.[11] = 1.
@@ -5090,7 +4988,7 @@ typedef union { @endcode
@note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
**/
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
+#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
/**
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
@@ -5104,36 +5002,35 @@ typedef union { /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1.
///
- UINT32 Minimum_Performance:8;
+ UINT32 Minimum_Performance : 8;
///
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1.
///
- UINT32 Maximum_Performance:8;
+ UINT32 Maximum_Performance : 8;
///
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
/// If CPUID.06H:EAX.[11] = 1.
///
- UINT32 Desired_Performance:8;
+ UINT32 Desired_Performance : 8;
///
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
/// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
///
- UINT32 Energy_Performance_Preference:8;
+ UINT32 Energy_Performance_Preference : 8;
///
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
///
- UINT32 Activity_Window:10;
- UINT32 Reserved:22;
+ UINT32 Activity_Window : 10;
+ UINT32 Reserved : 22;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
-
/**
Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
@@ -5152,7 +5049,7 @@ typedef union { @endcode
@note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
**/
-#define MSR_IA32_HWP_INTERRUPT 0x00000773
+#define MSR_IA32_HWP_INTERRUPT 0x00000773
/**
MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
@@ -5166,26 +5063,25 @@ typedef union { /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
/// Notifications". If CPUID.06H:EAX.[8] = 1.
///
- UINT32 EN_Guaranteed_Performance_Change:1;
+ UINT32 EN_Guaranteed_Performance_Change : 1;
///
/// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
/// If CPUID.06H:EAX.[8] = 1.
///
- UINT32 EN_Excursion_Minimum:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 EN_Excursion_Minimum : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_INTERRUPT_REGISTER;
-
/**
Power Management Control Hints to a Logical Processor (R/W). If
CPUID.06H:EAX.[7] = 1.
@@ -5205,7 +5101,7 @@ typedef union { @endcode
@note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
**/
-#define MSR_IA32_HWP_REQUEST 0x00000774
+#define MSR_IA32_HWP_REQUEST 0x00000774
/**
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
@@ -5219,41 +5115,40 @@ typedef union { /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 Minimum_Performance:8;
+ UINT32 Minimum_Performance : 8;
///
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1.
///
- UINT32 Maximum_Performance:8;
+ UINT32 Maximum_Performance : 8;
///
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
/// If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Desired_Performance:8;
+ UINT32 Desired_Performance : 8;
///
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
/// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
///
- UINT32 Energy_Performance_Preference:8;
+ UINT32 Energy_Performance_Preference : 8;
///
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
///
- UINT32 Activity_Window:10;
+ UINT32 Activity_Window : 10;
///
/// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
///
- UINT32 Package_Control:1;
- UINT32 Reserved:21;
+ UINT32 Package_Control : 1;
+ UINT32 Reserved : 21;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_REQUEST_REGISTER;
-
/**
Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
CPUID.06H:EAX.[7] = 1.
@@ -5273,7 +5168,7 @@ typedef union { @endcode
@note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
**/
-#define MSR_IA32_HWP_STATUS 0x00000777
+#define MSR_IA32_HWP_STATUS 0x00000777
/**
MSR information returned for MSR index #MSR_IA32_HWP_STATUS
@@ -5287,27 +5182,26 @@ typedef union { /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
/// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Guaranteed_Performance_Change:1;
- UINT32 Reserved1:1;
+ UINT32 Guaranteed_Performance_Change : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
/// Feedback". If CPUID.06H:EAX.[7] = 1.
///
- UINT32 Excursion_To_Minimum:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
+ UINT32 Excursion_To_Minimum : 1;
+ UINT32 Reserved2 : 29;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_HWP_STATUS_REGISTER;
-
/**
x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
&& IA32_APIC_BASE.[10] = 1.
@@ -5324,8 +5218,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
**/
-#define MSR_IA32_X2APIC_APICID 0x00000802
-
+#define MSR_IA32_X2APIC_APICID 0x00000802
/**
x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5343,8 +5236,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
**/
-#define MSR_IA32_X2APIC_VERSION 0x00000803
-
+#define MSR_IA32_X2APIC_VERSION 0x00000803
/**
x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5363,8 +5255,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
**/
-#define MSR_IA32_X2APIC_TPR 0x00000808
-
+#define MSR_IA32_X2APIC_TPR 0x00000808
/**
x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5382,8 +5273,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
**/
-#define MSR_IA32_X2APIC_PPR 0x0000080A
-
+#define MSR_IA32_X2APIC_PPR 0x0000080A
/**
x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
@@ -5402,8 +5292,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
**/
-#define MSR_IA32_X2APIC_EOI 0x0000080B
-
+#define MSR_IA32_X2APIC_EOI 0x0000080B
/**
x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5421,8 +5310,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
**/
-#define MSR_IA32_X2APIC_LDR 0x0000080D
-
+#define MSR_IA32_X2APIC_LDR 0x0000080D
/**
x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
@@ -5441,8 +5329,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
**/
-#define MSR_IA32_X2APIC_SIVR 0x0000080F
-
+#define MSR_IA32_X2APIC_SIVR 0x0000080F
/**
x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
@@ -5468,17 +5355,16 @@ typedef union { MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_ISR0 0x00000810
-#define MSR_IA32_X2APIC_ISR1 0x00000811
-#define MSR_IA32_X2APIC_ISR2 0x00000812
-#define MSR_IA32_X2APIC_ISR3 0x00000813
-#define MSR_IA32_X2APIC_ISR4 0x00000814
-#define MSR_IA32_X2APIC_ISR5 0x00000815
-#define MSR_IA32_X2APIC_ISR6 0x00000816
-#define MSR_IA32_X2APIC_ISR7 0x00000817
+#define MSR_IA32_X2APIC_ISR0 0x00000810
+#define MSR_IA32_X2APIC_ISR1 0x00000811
+#define MSR_IA32_X2APIC_ISR2 0x00000812
+#define MSR_IA32_X2APIC_ISR3 0x00000813
+#define MSR_IA32_X2APIC_ISR4 0x00000814
+#define MSR_IA32_X2APIC_ISR5 0x00000815
+#define MSR_IA32_X2APIC_ISR6 0x00000816
+#define MSR_IA32_X2APIC_ISR7 0x00000817
/// @}
-
/**
x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
@@ -5503,17 +5389,16 @@ typedef union { MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_TMR0 0x00000818
-#define MSR_IA32_X2APIC_TMR1 0x00000819
-#define MSR_IA32_X2APIC_TMR2 0x0000081A
-#define MSR_IA32_X2APIC_TMR3 0x0000081B
-#define MSR_IA32_X2APIC_TMR4 0x0000081C
-#define MSR_IA32_X2APIC_TMR5 0x0000081D
-#define MSR_IA32_X2APIC_TMR6 0x0000081E
-#define MSR_IA32_X2APIC_TMR7 0x0000081F
+#define MSR_IA32_X2APIC_TMR0 0x00000818
+#define MSR_IA32_X2APIC_TMR1 0x00000819
+#define MSR_IA32_X2APIC_TMR2 0x0000081A
+#define MSR_IA32_X2APIC_TMR3 0x0000081B
+#define MSR_IA32_X2APIC_TMR4 0x0000081C
+#define MSR_IA32_X2APIC_TMR5 0x0000081D
+#define MSR_IA32_X2APIC_TMR6 0x0000081E
+#define MSR_IA32_X2APIC_TMR7 0x0000081F
/// @}
-
/**
x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
@@ -5538,17 +5423,16 @@ typedef union { MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
@{
**/
-#define MSR_IA32_X2APIC_IRR0 0x00000820
-#define MSR_IA32_X2APIC_IRR1 0x00000821
-#define MSR_IA32_X2APIC_IRR2 0x00000822
-#define MSR_IA32_X2APIC_IRR3 0x00000823
-#define MSR_IA32_X2APIC_IRR4 0x00000824
-#define MSR_IA32_X2APIC_IRR5 0x00000825
-#define MSR_IA32_X2APIC_IRR6 0x00000826
-#define MSR_IA32_X2APIC_IRR7 0x00000827
+#define MSR_IA32_X2APIC_IRR0 0x00000820
+#define MSR_IA32_X2APIC_IRR1 0x00000821
+#define MSR_IA32_X2APIC_IRR2 0x00000822
+#define MSR_IA32_X2APIC_IRR3 0x00000823
+#define MSR_IA32_X2APIC_IRR4 0x00000824
+#define MSR_IA32_X2APIC_IRR5 0x00000825
+#define MSR_IA32_X2APIC_IRR6 0x00000826
+#define MSR_IA32_X2APIC_IRR7 0x00000827
/// @}
-
/**
x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1.
@@ -5566,8 +5450,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
**/
-#define MSR_IA32_X2APIC_ESR 0x00000828
-
+#define MSR_IA32_X2APIC_ESR 0x00000828
/**
x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
@@ -5586,8 +5469,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
-
+#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
/**
x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5606,8 +5488,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
**/
-#define MSR_IA32_X2APIC_ICR 0x00000830
-
+#define MSR_IA32_X2APIC_ICR 0x00000830
/**
x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5626,8 +5507,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
-
+#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
/**
x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
@@ -5646,8 +5526,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
-
+#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
/**
x2APIC LVT Performance Monitor Interrupt Register (R/W). If
@@ -5666,8 +5545,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
-
+#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
/**
x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5686,8 +5564,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
-
+#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
/**
x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5706,8 +5583,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
-
+#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
/**
x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5726,8 +5602,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
**/
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
-
+#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
/**
x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5746,8 +5621,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
**/
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
-
+#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
/**
x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5765,8 +5639,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
**/
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
-
+#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
/**
x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
@@ -5785,8 +5658,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
**/
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
-
+#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
/**
x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
@@ -5805,8 +5677,7 @@ typedef union { @endcode
@note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
**/
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
-
+#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
/**
Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
@@ -5826,7 +5697,7 @@ typedef union { @endcode
@note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
**/
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
+#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
/**
MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
@@ -5840,32 +5711,31 @@ typedef union { /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
/// Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 Enable:1;
- UINT32 Reserved1:29;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 29;
///
/// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
/// lock bit is set automatically on the first SMI assertion even if not
/// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 Lock:1;
+ UINT32 Lock : 1;
///
/// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
/// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
///
- UINT32 DebugOccurred:1;
- UINT32 Reserved2:32;
+ UINT32 DebugOccurred : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_DEBUG_INTERFACE_REGISTER;
-
/**
L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
@@ -5884,7 +5754,7 @@ typedef union { @endcode
@note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
**/
-#define MSR_IA32_L3_QOS_CFG 0x00000C81
+#define MSR_IA32_L3_QOS_CFG 0x00000C81
/**
MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
@@ -5898,18 +5768,18 @@ typedef union { /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
/// in Code and Data Prioritization (CDP) mode.
///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
/**
@@ -5930,7 +5800,7 @@ typedef union { @endcode
@note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
**/
-#define MSR_IA32_L2_QOS_CFG 0x00000C82
+#define MSR_IA32_L2_QOS_CFG 0x00000C82
/**
MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
@@ -5944,18 +5814,18 @@ typedef union { /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
/// in Code and Data Prioritization (CDP) mode.
///
- UINT32 Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_L2_QOS_CFG_REGISTER;
/**
@@ -5977,7 +5847,7 @@ typedef union { @endcode
@note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
**/
-#define MSR_IA32_QM_EVTSEL 0x00000C8D
+#define MSR_IA32_QM_EVTSEL 0x00000C8D
/**
MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
@@ -5991,22 +5861,21 @@ typedef union { /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
/// IA32_QM_CTR.
///
- UINT32 EventID:8;
- UINT32 Reserved:24;
+ UINT32 EventID : 8;
+ UINT32 Reserved : 24;
///
/// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
/// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
/// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
///
- UINT32 ResourceMonitoringID:32;
+ UINT32 ResourceMonitoringID : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_QM_EVTSEL_REGISTER;
-
/**
Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
).
@@ -6025,7 +5894,7 @@ typedef union { @endcode
@note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
**/
-#define MSR_IA32_QM_CTR 0x00000C8E
+#define MSR_IA32_QM_CTR 0x00000C8E
/**
MSR information returned for MSR index #MSR_IA32_QM_CTR
@@ -6038,29 +5907,28 @@ typedef union { ///
/// [Bits 31:0] Resource Monitored Data.
///
- UINT32 ResourceMonitoredData:32;
+ UINT32 ResourceMonitoredData : 32;
///
/// [Bits 61:32] Resource Monitored Data.
///
- UINT32 ResourceMonitoredDataHi:30;
+ UINT32 ResourceMonitoredDataHi : 30;
///
/// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
/// available or not monitored for this resource or RMID.
///
- UINT32 Unavailable:1;
+ UINT32 Unavailable : 1;
///
/// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
/// written to IA32_PQR_QM_EVTSEL.
///
- UINT32 Error:1;
+ UINT32 Error : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_QM_CTR_REGISTER;
-
/**
Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
=1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
@@ -6080,7 +5948,7 @@ typedef union { @endcode
@note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
**/
-#define MSR_IA32_PQR_ASSOC 0x00000C8F
+#define MSR_IA32_PQR_ASSOC 0x00000C8F
/**
MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
@@ -6095,21 +5963,20 @@ typedef union { /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
/// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
///
- UINT32 ResourceMonitoringID:32;
+ UINT32 ResourceMonitoringID : 32;
///
/// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
/// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
/// ECX=0):EBX.[15] = 1 ).
///
- UINT32 COS:32;
+ UINT32 COS : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PQR_ASSOC_REGISTER;
-
/**
Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
ECX=0H):EBX[14] = 1).
@@ -6129,7 +5996,7 @@ typedef union { @endcode
@note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
**/
-#define MSR_IA32_BNDCFGS 0x00000D90
+#define MSR_IA32_BNDCFGS 0x00000D90
/**
MSR information returned for MSR index #MSR_IA32_BNDCFGS
@@ -6142,29 +6009,28 @@ typedef union { ///
/// [Bit 0] EN: Enable Intel MPX in supervisor mode.
///
- UINT32 EN:1;
+ UINT32 EN : 1;
///
/// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
/// instructions in the absence of the BND prefix.
///
- UINT32 BNDPRESERVE:1;
- UINT32 Reserved:10;
+ UINT32 BNDPRESERVE : 1;
+ UINT32 Reserved : 10;
///
/// [Bits 31:12] Base Address of Bound Directory.
///
- UINT32 Base:20;
+ UINT32 Base : 20;
///
/// [Bits 63:32] Base Address of Bound Directory.
///
- UINT32 BaseHi:32;
+ UINT32 BaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_BNDCFGS_REGISTER;
-
/**
Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
@@ -6183,7 +6049,7 @@ typedef union { @endcode
@note MSR_IA32_XSS is defined as IA32_XSS in SDM.
**/
-#define MSR_IA32_XSS 0x00000DA0
+#define MSR_IA32_XSS 0x00000DA0
/**
MSR information returned for MSR index #MSR_IA32_XSS
@@ -6193,25 +6059,24 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] Trace Packet Configuration State (R/W).
///
- UINT32 TracePacketConfigurationState:1;
- UINT32 Reserved2:23;
- UINT32 Reserved3:32;
+ UINT32 TracePacketConfigurationState : 1;
+ UINT32 Reserved2 : 23;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_XSS_REGISTER;
-
/**
Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
@@ -6230,7 +6095,7 @@ typedef union { @endcode
@note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
**/
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
+#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
/**
MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
@@ -6245,21 +6110,20 @@ typedef union { /// logical processors in the package. See Section 14.5.2, "Package level
/// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
///
- UINT32 HDC_Pkg_Enable:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HDC_Pkg_Enable : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PKG_HDC_CTL_REGISTER;
-
/**
Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
@@ -6278,7 +6142,7 @@ typedef union { @endcode
@note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
**/
-#define MSR_IA32_PM_CTL1 0x00000DB1
+#define MSR_IA32_PM_CTL1 0x00000DB1
/**
MSR information returned for MSR index #MSR_IA32_PM_CTL1
@@ -6293,21 +6157,20 @@ typedef union { /// package level HDC control. See Section 14.5.3.
/// If CPUID.06H:EAX.[13] = 1.
///
- UINT32 HDC_Allow_Block:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 HDC_Allow_Block : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_PM_CTL1_REGISTER;
-
/**
Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
@@ -6325,8 +6188,7 @@ typedef union { @endcode
@note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
**/
-#define MSR_IA32_THREAD_STALL 0x00000DB2
-
+#define MSR_IA32_THREAD_STALL 0x00000DB2
/**
Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
@@ -6347,7 +6209,7 @@ typedef union { @endcode
@note MSR_IA32_EFER is defined as IA32_EFER in SDM.
**/
-#define MSR_IA32_EFER 0xC0000080
+#define MSR_IA32_EFER 0xC0000080
/**
MSR information returned for MSR index #MSR_IA32_EFER
@@ -6361,37 +6223,36 @@ typedef union { /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
/// instructions in 64-bit mode.
///
- UINT32 SCE:1;
- UINT32 Reserved1:7;
+ UINT32 SCE : 1;
+ UINT32 Reserved1 : 7;
///
/// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
/// operation.
///
- UINT32 LME:1;
- UINT32 Reserved2:1;
+ UINT32 LME : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
/// is active when set.
///
- UINT32 LMA:1;
+ UINT32 LMA : 1;
///
/// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
///
- UINT32 NXE:1;
- UINT32 Reserved3:20;
- UINT32 Reserved4:32;
+ UINT32 NXE : 1;
+ UINT32 Reserved3 : 20;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_EFER_REGISTER;
-
/**
System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6408,8 +6269,7 @@ typedef union { @endcode
@note MSR_IA32_STAR is defined as IA32_STAR in SDM.
**/
-#define MSR_IA32_STAR 0xC0000081
-
+#define MSR_IA32_STAR 0xC0000081
/**
IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6427,7 +6287,7 @@ typedef union { @endcode
@note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
**/
-#define MSR_IA32_LSTAR 0xC0000082
+#define MSR_IA32_LSTAR 0xC0000082
/**
IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
@@ -6447,7 +6307,7 @@ typedef union { @endcode
@note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
**/
-#define MSR_IA32_CSTAR 0xC0000083
+#define MSR_IA32_CSTAR 0xC0000083
/**
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6465,8 +6325,7 @@ typedef union { @endcode
@note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
**/
-#define MSR_IA32_FMASK 0xC0000084
-
+#define MSR_IA32_FMASK 0xC0000084
/**
Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6484,8 +6343,7 @@ typedef union { @endcode
@note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
**/
-#define MSR_IA32_FS_BASE 0xC0000100
-
+#define MSR_IA32_FS_BASE 0xC0000100
/**
Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6503,8 +6361,7 @@ typedef union { @endcode
@note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
**/
-#define MSR_IA32_GS_BASE 0xC0000101
-
+#define MSR_IA32_GS_BASE 0xC0000101
/**
Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
@@ -6522,8 +6379,7 @@ typedef union { @endcode
@note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
**/
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
-
+#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
/**
Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
@@ -6543,7 +6399,7 @@ typedef union { @endcode
@note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
**/
-#define MSR_IA32_TSC_AUX 0xC0000103
+#define MSR_IA32_TSC_AUX 0xC0000103
/**
MSR information returned for MSR index #MSR_IA32_TSC_AUX
@@ -6556,17 +6412,17 @@ typedef union { ///
/// [Bits 31:0] AUX: Auxiliary signature of TSC.
///
- UINT32 AUX:32;
- UINT32 Reserved:32;
+ UINT32 AUX : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_TSC_AUX_REGISTER;
#endif
|