diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Cpuid.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Cpuid.h | 982 |
1 files changed, 477 insertions, 505 deletions
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h index 5ec85ba561..bd6349d794 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -40,7 +40,7 @@ AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
@endcode
**/
-#define CPUID_SIGNATURE 0x00
+#define CPUID_SIGNATURE 0x00
///
/// @{ CPUID signature values returned by Intel processors
@@ -52,7 +52,6 @@ /// @}
///
-
/**
CPUID Version Information
@@ -77,7 +76,7 @@ AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_VERSION_INFO 0x01
+#define CPUID_VERSION_INFO 0x01
/**
CPUID Version Information returned in EAX for CPUID leaf
@@ -88,14 +87,14 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
- UINT32 Model:4; ///< [Bits 7:4] Model
- UINT32 FamilyId:4; ///< [Bits 11:8] Family
- UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
- UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
- UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
- UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
- UINT32 Reserved2:4; ///< Reserved
+ UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID
+ UINT32 Model : 4; ///< [Bits 7:4] Model
+ UINT32 FamilyId : 4; ///< [Bits 11:8] Family
+ UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type
+ UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved
+ UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID
+ UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID
+ UINT32 Reserved2 : 4; ///< Reserved
} Bits;
///
/// All bit fields as a 32-bit value
@@ -126,13 +125,13 @@ typedef union { /// [Bits 7:0] Provides an entry into a brand string table that contains
/// brand strings for IA-32 processors.
///
- UINT32 BrandIndex:8;
+ UINT32 BrandIndex : 8;
///
/// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
/// and CLFLUSHOPT instructions in 8-byte increments. This field was
/// introduced in the Pentium 4 processor.
///
- UINT32 CacheLineSize:8;
+ UINT32 CacheLineSize : 8;
///
/// [Bits 23:16] Maximum number of addressable IDs for logical processors
/// in this physical package.
@@ -143,13 +142,13 @@ typedef union { /// logical processors in a physical package. This field is only valid if
/// CPUID.1.EDX.HTT[bit 28]= 1.
///
- UINT32 MaximumAddressableIdsForLogicalProcessors:8;
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 8;
///
/// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
/// processor during power up. This field was introduced in the Pentium 4
/// processor.
///
- UINT32 InitialLocalApicId:8;
+ UINT32 InitialLocalApicId : 8;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -170,161 +169,161 @@ typedef union { /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
/// processor supports this technology
///
- UINT32 SSE3:1;
+ UINT32 SSE3 : 1;
///
/// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
/// instruction. Carryless Multiplication
///
- UINT32 PCLMULQDQ:1;
+ UINT32 PCLMULQDQ : 1;
///
/// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
/// DS area using 64-bit layout.
///
- UINT32 DTES64:1;
+ UINT32 DTES64 : 1;
///
/// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
/// this feature.
///
- UINT32 MONITOR:1;
+ UINT32 MONITOR : 1;
///
/// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
/// supports the extensions to the Debug Store feature to allow for branch
/// message storage qualified by CPL
///
- UINT32 DS_CPL:1;
+ UINT32 DS_CPL : 1;
///
/// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
/// processor supports this technology.
///
- UINT32 VMX:1;
+ UINT32 VMX : 1;
///
/// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
/// supports this technology
///
- UINT32 SMX:1;
+ UINT32 SMX : 1;
///
/// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
/// that the processor supports this technology
///
- UINT32 EIST:1;
+ UINT32 EIST : 1;
///
/// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
/// supports this technology
///
- UINT32 TM2:1;
+ UINT32 TM2 : 1;
///
/// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
/// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
/// extensions are not present in the processor.
///
- UINT32 SSSE3:1;
+ UINT32 SSSE3 : 1;
///
/// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
/// can be set to either adaptive mode or shared mode. A value of 0 indicates
/// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
/// Bit 24 (L1 Data Cache Context Mode) for details
///
- UINT32 CNXT_ID:1;
+ UINT32 CNXT_ID : 1;
///
/// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
/// MSR for silicon debug
///
- UINT32 SDBG:1;
+ UINT32 SDBG : 1;
///
/// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
/// Add) extensions using YMM state.
///
- UINT32 FMA:1;
+ UINT32 FMA : 1;
///
/// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
/// is available.
///
- UINT32 CMPXCHG16B:1;
+ UINT32 CMPXCHG16B : 1;
///
/// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
/// supports changing IA32_MISC_ENABLE[Bit 23].
///
- UINT32 xTPR_Update_Control:1;
+ UINT32 xTPR_Update_Control : 1;
///
/// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
/// processor supports the performance and debug feature indication MSR
/// IA32_PERF_CAPABILITIES.
///
- UINT32 PDCM:1;
- UINT32 Reserved:1;
+ UINT32 PDCM : 1;
+ UINT32 Reserved : 1;
///
/// [Bit 17] Process-context identifiers. A value of 1 indicates that the
/// processor supports PCIDs and that software may set CR4.PCIDE to 1.
///
- UINT32 PCID:1;
+ UINT32 PCID : 1;
///
/// [Bit 18] A value of 1 indicates the processor supports the ability to
/// prefetch data from a memory mapped device. Direct Cache Access.
///
- UINT32 DCA:1;
+ UINT32 DCA : 1;
///
/// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
///
- UINT32 SSE4_1:1;
+ UINT32 SSE4_1 : 1;
///
/// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
///
- UINT32 SSE4_2:1;
+ UINT32 SSE4_2 : 1;
///
/// [Bit 21] A value of 1 indicates that the processor supports x2APIC
/// feature.
///
- UINT32 x2APIC:1;
+ UINT32 x2APIC : 1;
///
/// [Bit 22] A value of 1 indicates that the processor supports MOVBE
/// instruction.
///
- UINT32 MOVBE:1;
+ UINT32 MOVBE : 1;
///
/// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
/// instruction.
///
- UINT32 POPCNT:1;
+ UINT32 POPCNT : 1;
///
/// [Bit 24] A value of 1 indicates that the processor's local APIC timer
/// supports one-shot operation using a TSC deadline value.
///
- UINT32 TSC_Deadline:1;
+ UINT32 TSC_Deadline : 1;
///
/// [Bit 25] A value of 1 indicates that the processor supports the AESNI
/// instruction extensions.
///
- UINT32 AESNI:1;
+ UINT32 AESNI : 1;
///
/// [Bit 26] A value of 1 indicates that the processor supports the
/// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
/// instructions, and XCR0.
///
- UINT32 XSAVE:1;
+ UINT32 XSAVE : 1;
///
/// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
/// to enable XSETBV/XGETBV instructions to access XCR0 and to support
/// processor extended state management using XSAVE/XRSTOR.
///
- UINT32 OSXSAVE:1;
+ UINT32 OSXSAVE : 1;
///
/// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
/// extensions.
///
- UINT32 AVX:1;
+ UINT32 AVX : 1;
///
/// [Bit 29] A value of 1 indicates that processor supports 16-bit
/// floating-point conversion instructions.
///
- UINT32 F16C:1;
+ UINT32 F16C : 1;
///
/// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
///
- UINT32 RDRAND:1;
+ UINT32 RDRAND : 1;
///
/// [Bit 31] Always returns 0.
///
- UINT32 NotUsed:1;
+ UINT32 NotUsed : 1;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -344,7 +343,7 @@ typedef union { ///
/// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
///
- UINT32 FPU:1;
+ UINT32 FPU : 1;
///
/// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
/// including CR4.VME for controlling the feature, CR4.PVI for protected
@@ -352,38 +351,38 @@ typedef union { /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
/// EFLAGS.VIP flags.
///
- UINT32 VME:1;
+ UINT32 VME : 1;
///
/// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
/// CR4.DE for controlling the feature, and optional trapping of accesses to
/// DR4 and DR5.
///
- UINT32 DE:1;
+ UINT32 DE : 1;
///
/// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
/// including CR4.PSE for controlling the feature, the defined dirty bit in
/// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
/// PDEs, and PTEs.
///
- UINT32 PSE:1;
+ UINT32 PSE : 1;
///
/// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
/// including CR4.TSD for controlling privilege.
///
- UINT32 TSC:1;
+ UINT32 TSC : 1;
///
/// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
/// RDMSR and WRMSR instructions are supported. Some of the MSRs are
/// implementation dependent.
///
- UINT32 MSR:1;
+ UINT32 MSR : 1;
///
/// [Bit 6] Physical Address Extension. Physical addresses greater than 32
/// bits are supported: extended page table entry formats, an extra level in
/// the page translation tables is defined, 2-MByte pages are supported
/// instead of 4 Mbyte pages if PAE bit is 1.
///
- UINT32 PAE:1;
+ UINT32 PAE : 1;
///
/// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
/// Checks, including CR4.MCE for controlling the feature. This feature does
@@ -393,59 +392,59 @@ typedef union { /// processing of the exception, or test for the presence of the Machine
/// Check feature.
///
- UINT32 MCE:1;
+ UINT32 MCE : 1;
///
/// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
/// instruction is supported (implicitly locked and atomic).
///
- UINT32 CX8:1;
+ UINT32 CX8 : 1;
///
/// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
/// Interrupt Controller (APIC), responding to memory mapped commands in the
/// physical address range FFFE0000H to FFFE0FFFH (by default - some
/// processors permit the APIC to be relocated).
///
- UINT32 APIC:1;
- UINT32 Reserved1:1;
+ UINT32 APIC : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
/// and associated MSRs are supported.
///
- UINT32 SEP:1;
+ UINT32 SEP : 1;
///
/// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
/// MSR contains feature bits that describe what memory types are supported,
/// how many variable MTRRs are supported, and whether fixed MTRRs are
/// supported.
///
- UINT32 MTRR:1;
+ UINT32 MTRR : 1;
///
/// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
/// entries that map a page, indicating TLB entries that are common to
/// different processes and need not be flushed. The CR4.PGE bit controls
/// this feature.
///
- UINT32 PGE:1;
+ UINT32 PGE : 1;
///
/// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
/// Check Architecture of reporting machine errors is supported. The MCG_CAP
/// MSR contains feature bits describing how many banks of error reporting
/// MSRs are supported.
///
- UINT32 MCA:1;
+ UINT32 MCA : 1;
///
/// [Bit 15] Conditional Move Instructions. The conditional move instruction
/// CMOV is supported. In addition, if x87 FPU is present as indicated by the
/// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
///
- UINT32 CMOV:1;
+ UINT32 CMOV : 1;
///
/// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
/// feature augments the Memory Type Range Registers (MTRRs), allowing an
/// operating system to specify attributes of memory accessed through a
/// linear address on a 4KB granularity.
///
- UINT32 PAT:1;
+ UINT32 PAT : 1;
///
/// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
/// memory beyond 4 GBytes are supported with 32-bit paging. This feature
@@ -453,36 +452,36 @@ typedef union { /// encoded in bits 20:13 of the page-directory entry. Such physical
/// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
///
- UINT32 PSE_36:1;
+ UINT32 PSE_36 : 1;
///
/// [Bit 18] Processor Serial Number. The processor supports the 96-bit
/// processor identification number feature and the feature is enabled.
///
- UINT32 PSN:1;
+ UINT32 PSN : 1;
///
/// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
///
- UINT32 CLFSH:1;
- UINT32 Reserved2:1;
+ UINT32 CLFSH : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 21] Debug Store. The processor supports the ability to write debug
/// information into a memory resident buffer. This feature is used by the
/// branch trace store (BTS) and precise event-based sampling (PEBS)
/// facilities.
///
- UINT32 DS:1;
+ UINT32 DS : 1;
///
/// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
/// processor implements internal MSRs that allow processor temperature to
/// be monitored and processor performance to be modulated in predefined
/// duty cycles under software control.
///
- UINT32 ACPI:1;
+ UINT32 ACPI : 1;
///
/// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
/// technology.
///
- UINT32 MMX:1;
+ UINT32 MMX : 1;
///
/// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
/// instructions are supported for fast save and restore of the floating
@@ -490,21 +489,21 @@ typedef union { /// available for an operating system to indicate that it supports the
/// FXSAVE and FXRSTOR instructions.
///
- UINT32 FXSR:1;
+ UINT32 FXSR : 1;
///
/// [Bit 25] SSE. The processor supports the SSE extensions.
///
- UINT32 SSE:1;
+ UINT32 SSE : 1;
///
/// [Bit 26] SSE2. The processor supports the SSE2 extensions.
///
- UINT32 SSE2:1;
+ UINT32 SSE2 : 1;
///
/// [Bit 27] Self Snoop. The processor supports the management of
/// conflicting memory types by performing a snoop of its own cache
/// structure for transactions issued to the bus.
///
- UINT32 SS:1;
+ UINT32 SS : 1;
///
/// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
/// indicates there is only a single logical processor in the package and
@@ -513,13 +512,13 @@ typedef union { /// addressable IDs for logical processors in this package) is valid for the
/// package.
///
- UINT32 HTT:1;
+ UINT32 HTT : 1;
///
/// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
/// automatic thermal control circuitry (TCC).
///
- UINT32 TM:1;
- UINT32 Reserved3:1;
+ UINT32 TM : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 31] Pending Break Enable. The processor supports the use of the
/// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
@@ -527,7 +526,7 @@ typedef union { /// the processor should return to normal operation to handle the interrupt.
/// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
///
- UINT32 PBE:1;
+ UINT32 PBE : 1;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -535,7 +534,6 @@ typedef union { UINT32 Uint32;
} CPUID_VERSION_INFO_EDX;
-
/**
CPUID Cache and TLB Information
@@ -707,7 +705,7 @@ typedef union { use CPUID leaf 4 to query cache parameters</td></tr>
</table>
**/
-#define CPUID_CACHE_INFO 0x02
+#define CPUID_CACHE_INFO 0x02
/**
CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
@@ -718,24 +716,23 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:31;
+ UINT32 Reserved : 31;
///
/// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
/// if 1, then none of the cache descriptor bytes in the register are valid.
///
- UINT32 NotValid:1;
+ UINT32 NotValid : 1;
} Bits;
///
/// Array of Cache and TLB descriptor bytes
///
- UINT8 CacheDescriptor[4];
+ UINT8 CacheDescriptor[4];
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_INFO_CACHE_TLB;
-
/**
CPUID Processor Serial Number
@@ -762,8 +759,7 @@ typedef union { AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
@endcode
**/
-#define CPUID_SERIAL_NUMBER 0x03
-
+#define CPUID_SERIAL_NUMBER 0x03
/**
CPUID Cache Parameters
@@ -801,7 +797,7 @@ typedef union { } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
@endcode
**/
-#define CPUID_CACHE_PARAMS 0x04
+#define CPUID_CACHE_PARAMS 0x04
/**
CPUID Cache Parameters Information returned in EAX for CPUID leaf
@@ -816,23 +812,23 @@ typedef union { /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
/// then there is no information for the requested cache level.
///
- UINT32 CacheType:5;
+ UINT32 CacheType : 5;
///
/// [Bits 7:5] Cache level (Starts at 1).
///
- UINT32 CacheLevel:3;
+ UINT32 CacheLevel : 3;
///
/// [Bit 8] Self Initializing cache level (does not need SW initialization).
///
- UINT32 SelfInitializingCache:1;
+ UINT32 SelfInitializingCache : 1;
///
/// [Bit 9] Fully Associative cache.
///
- UINT32 FullyAssociativeCache:1;
+ UINT32 FullyAssociativeCache : 1;
///
/// [Bits 13:10] Reserved.
///
- UINT32 Reserved:4;
+ UINT32 Reserved : 4;
///
/// [Bits 25:14] Maximum number of addressable IDs for logical processors
/// sharing this cache.
@@ -842,7 +838,7 @@ typedef union { /// is the number of unique initial APIC IDs reserved for addressing
/// different logical processors sharing this cache.
///
- UINT32 MaximumAddressableIdsForLogicalProcessors:12;
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 12;
///
/// [Bits 31:26] Maximum number of addressable IDs for processor cores in
/// the physical package.
@@ -854,12 +850,12 @@ typedef union { /// The returned value is constant for valid initial values in ECX. Valid
/// ECX values start from 0.
///
- UINT32 MaximumAddressableIdsForProcessorCores:6;
+ UINT32 MaximumAddressableIdsForProcessorCores : 6;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EAX;
///
@@ -886,22 +882,22 @@ typedef union { /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
/// get the result.
///
- UINT32 LineSize:12;
+ UINT32 LineSize : 12;
///
/// [Bits 21:12] Physical Line Partitions. Add one to the return value to
/// get the result.
///
- UINT32 LinePartitions:10;
+ UINT32 LinePartitions : 10;
///
/// [Bits 31:22] Ways of associativity. Add one to the return value to get
/// the result.
///
- UINT32 Ways:10;
+ UINT32 Ways : 10;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EBX;
/**
@@ -920,29 +916,28 @@ typedef union { /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
/// non-originating threads sharing this cache.
///
- UINT32 Invalidate:1;
+ UINT32 Invalidate : 1;
///
/// [Bit 1] Cache Inclusiveness.
/// 0 = Cache is not inclusive of lower cache levels.
/// 1 = Cache is inclusive of lower cache levels.
///
- UINT32 CacheInclusiveness:1;
+ UINT32 CacheInclusiveness : 1;
///
/// [Bit 2] Complex Cache Indexing.
/// 0 = Direct mapped cache.
/// 1 = A complex function is used to index the cache, potentially using all
/// address bits.
///
- UINT32 ComplexCacheIndexing:1;
- UINT32 Reserved:29;
+ UINT32 ComplexCacheIndexing : 1;
+ UINT32 Reserved : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_CACHE_PARAMS_EDX;
-
/**
CPUID MONITOR/MWAIT Information
@@ -967,7 +962,7 @@ typedef union { AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_MONITOR_MWAIT 0x05
+#define CPUID_MONITOR_MWAIT 0x05
/**
CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
@@ -982,13 +977,13 @@ typedef union { /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
/// monitor granularity).
///
- UINT32 SmallestMonitorLineSize:16;
- UINT32 Reserved:16;
+ UINT32 SmallestMonitorLineSize : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EAX;
/**
@@ -1004,13 +999,13 @@ typedef union { /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
/// monitor granularity).
///
- UINT32 LargestMonitorLineSize:16;
- UINT32 Reserved:16;
+ UINT32 LargestMonitorLineSize : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EBX;
/**
@@ -1026,18 +1021,18 @@ typedef union { /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
/// and EDX are valid.
///
- UINT32 ExtensionsSupported:1;
+ UINT32 ExtensionsSupported : 1;
///
/// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
/// interrupts disabled.
///
- UINT32 InterruptAsBreak:1;
- UINT32 Reserved:30;
+ UINT32 InterruptAsBreak : 1;
+ UINT32 Reserved : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_ECX;
/**
@@ -1056,43 +1051,42 @@ typedef union { ///
/// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
///
- UINT32 C0States:4;
+ UINT32 C0States : 4;
///
/// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
///
- UINT32 C1States:4;
+ UINT32 C1States : 4;
///
/// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
///
- UINT32 C2States:4;
+ UINT32 C2States : 4;
///
/// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
///
- UINT32 C3States:4;
+ UINT32 C3States : 4;
///
/// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
///
- UINT32 C4States:4;
+ UINT32 C4States : 4;
///
/// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
///
- UINT32 C5States:4;
+ UINT32 C5States : 4;
///
/// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
///
- UINT32 C6States:4;
+ UINT32 C6States : 4;
///
/// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
///
- UINT32 C7States:4;
+ UINT32 C7States : 4;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_MONITOR_MWAIT_EDX;
-
/**
CPUID Thermal and Power Management
@@ -1115,7 +1109,7 @@ typedef union { AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
+#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
/**
CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
@@ -1129,87 +1123,87 @@ typedef union { ///
/// [Bit 0] Digital temperature sensor is supported if set.
///
- UINT32 DigitalTemperatureSensor:1;
+ UINT32 DigitalTemperatureSensor : 1;
///
/// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
///
- UINT32 TurboBoostTechnology:1;
+ UINT32 TurboBoostTechnology : 1;
///
/// [Bit 2] APIC-Timer-always-running feature is supported if set.
///
- UINT32 ARAT:1;
- UINT32 Reserved1:1;
+ UINT32 ARAT : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 4] Power limit notification controls are supported if set.
///
- UINT32 PLN:1;
+ UINT32 PLN : 1;
///
/// [Bit 5] Clock modulation duty cycle extension is supported if set.
///
- UINT32 ECMD:1;
+ UINT32 ECMD : 1;
///
/// [Bit 6] Package thermal management is supported if set.
///
- UINT32 PTM:1;
+ UINT32 PTM : 1;
///
/// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
/// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
///
- UINT32 HWP:1;
+ UINT32 HWP : 1;
///
/// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
///
- UINT32 HWP_Notification:1;
+ UINT32 HWP_Notification : 1;
///
/// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
///
- UINT32 HWP_Activity_Window:1;
+ UINT32 HWP_Activity_Window : 1;
///
/// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
///
- UINT32 HWP_Energy_Performance_Preference:1;
+ UINT32 HWP_Energy_Performance_Preference : 1;
///
/// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
///
- UINT32 HWP_Package_Level_Request:1;
- UINT32 Reserved2:1;
+ UINT32 HWP_Package_Level_Request : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
/// IA32_THREAD_STALL MSRs are supported if set.
///
- UINT32 HDC:1;
+ UINT32 HDC : 1;
///
/// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
///
- UINT32 TurboBoostMaxTechnology30:1;
+ UINT32 TurboBoostMaxTechnology30 : 1;
///
/// [Bit 15] HWP Capabilities.
/// Highest Performance change is supported if set.
///
- UINT32 HWPCapabilities:1;
+ UINT32 HWPCapabilities : 1;
///
/// [Bit 16] HWP PECI override is supported if set.
///
- UINT32 HWPPECIOverride:1;
+ UINT32 HWPPECIOverride : 1;
///
/// [Bit 17] Flexible HWP is supported if set.
///
- UINT32 FlexibleHWP:1;
+ UINT32 FlexibleHWP : 1;
///
/// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
///
- UINT32 FastAccessMode:1;
- UINT32 Reserved4:1;
+ UINT32 FastAccessMode : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
///
- UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;
- UINT32 Reserved5:11;
+ UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;
+ UINT32 Reserved5 : 11;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_EAX;
/**
@@ -1224,13 +1218,13 @@ typedef union { ///
/// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
///
- UINT32 InterruptThresholds:4;
- UINT32 Reserved:28;
+ UINT32 InterruptThresholds : 4;
+ UINT32 Reserved : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_EBX;
/**
@@ -1248,23 +1242,22 @@ typedef union { /// processor performance (since last reset of the counters), as a percentage
/// of the expected processor performance when running at the TSC frequency.
///
- UINT32 HardwareCoordinationFeedback:1;
- UINT32 Reserved1:2;
+ UINT32 HardwareCoordinationFeedback : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] If this bit is set, then the processor supports performance-energy
/// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
/// (1B0H).
///
- UINT32 PerformanceEnergyBias:1;
- UINT32 Reserved2:28;
+ UINT32 PerformanceEnergyBias : 1;
+ UINT32 Reserved2 : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_THERMAL_POWER_MANAGEMENT_ECX;
-
/**
CPUID Structured Extended Feature Flags Enumeration
@@ -1303,7 +1296,7 @@ typedef union { }
@endcode
**/
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
///
/// CPUID Structured Extended Feature Flags Enumeration sub-leaf
@@ -1323,144 +1316,144 @@ typedef union { ///
/// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
///
- UINT32 FSGSBASE:1;
+ UINT32 FSGSBASE : 1;
///
/// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
///
- UINT32 IA32_TSC_ADJUST:1;
+ UINT32 IA32_TSC_ADJUST : 1;
///
/// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
/// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
///
- UINT32 SGX:1;
+ UINT32 SGX : 1;
///
/// [Bit 3] If 1 indicates the processor supports the first group of advanced
/// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
///
- UINT32 BMI1:1;
+ UINT32 BMI1 : 1;
///
/// [Bit 4] Hardware Lock Elision
///
- UINT32 HLE:1;
+ UINT32 HLE : 1;
///
/// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
///
- UINT32 AVX2:1;
+ UINT32 AVX2 : 1;
///
/// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
///
- UINT32 FDP_EXCPTN_ONLY:1;
+ UINT32 FDP_EXCPTN_ONLY : 1;
///
/// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
///
- UINT32 SMEP:1;
+ UINT32 SMEP : 1;
///
/// [Bit 8] If 1 indicates the processor supports the second group of
/// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
/// SARX, SHLX, SHRX)
///
- UINT32 BMI2:1;
+ UINT32 BMI2 : 1;
///
/// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
///
- UINT32 EnhancedRepMovsbStosb:1;
+ UINT32 EnhancedRepMovsbStosb : 1;
///
/// [Bit 10] If 1, supports INVPCID instruction for system software that
/// manages process-context identifiers.
///
- UINT32 INVPCID:1;
+ UINT32 INVPCID : 1;
///
/// [Bit 11] Restricted Transactional Memory
///
- UINT32 RTM:1;
+ UINT32 RTM : 1;
///
/// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
/// Monitoring capability if 1.
///
- UINT32 RDT_M:1;
+ UINT32 RDT_M : 1;
///
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
///
- UINT32 DeprecateFpuCsDs:1;
+ UINT32 DeprecateFpuCsDs : 1;
///
/// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
///
- UINT32 MPX:1;
+ UINT32 MPX : 1;
///
/// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
/// Allocation capability if 1.
///
- UINT32 RDT_A:1;
+ UINT32 RDT_A : 1;
///
/// [Bit 16] AVX512F.
///
- UINT32 AVX512F:1;
+ UINT32 AVX512F : 1;
///
/// [Bit 17] AVX512DQ.
///
- UINT32 AVX512DQ:1;
+ UINT32 AVX512DQ : 1;
///
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
///
- UINT32 RDSEED:1;
+ UINT32 RDSEED : 1;
///
/// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
/// instructions.
///
- UINT32 ADX:1;
+ UINT32 ADX : 1;
///
/// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
/// instructions) if 1.
///
- UINT32 SMAP:1;
+ UINT32 SMAP : 1;
///
/// [Bit 21] AVX512_IFMA.
///
- UINT32 AVX512_IFMA:1;
- UINT32 Reserved6:1;
+ UINT32 AVX512_IFMA : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
///
- UINT32 CLFLUSHOPT:1;
+ UINT32 CLFLUSHOPT : 1;
///
/// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
///
- UINT32 CLWB:1;
+ UINT32 CLWB : 1;
///
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
/// extensions.
///
- UINT32 IntelProcessorTrace:1;
+ UINT32 IntelProcessorTrace : 1;
///
/// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
///
- UINT32 AVX512PF:1;
+ UINT32 AVX512PF : 1;
///
/// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
///
- UINT32 AVX512ER:1;
+ UINT32 AVX512ER : 1;
///
/// [Bit 28] AVX512CD.
///
- UINT32 AVX512CD:1;
+ UINT32 AVX512CD : 1;
///
/// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
/// SHA Extensions) if 1.
///
- UINT32 SHA:1;
+ UINT32 SHA : 1;
///
/// [Bit 30] AVX512BW.
///
- UINT32 AVX512BW:1;
+ UINT32 AVX512BW : 1;
///
/// [Bit 31] AVX512VL.
///
- UINT32 AVX512VL:1;
+ UINT32 AVX512VL : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
/**
@@ -1477,54 +1470,54 @@ typedef union { /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
/// (Intel Xeon Phi only.)
///
- UINT32 PREFETCHWT1:1;
+ UINT32 PREFETCHWT1 : 1;
///
/// [Bit 1] AVX512_VBMI.
///
- UINT32 AVX512_VBMI:1;
+ UINT32 AVX512_VBMI : 1;
///
/// [Bit 2] Supports user-mode instruction prevention if 1.
///
- UINT32 UMIP:1;
+ UINT32 UMIP : 1;
///
/// [Bit 3] Supports protection keys for user-mode pages if 1.
///
- UINT32 PKU:1;
+ UINT32 PKU : 1;
///
/// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
/// RDPKRU/WRPKRU instructions).
///
- UINT32 OSPKE:1;
- UINT32 Reserved5:9;
+ UINT32 OSPKE : 1;
+ UINT32 Reserved5 : 9;
///
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
- UINT32 AVX512_VPOPCNTDQ:1;
- UINT32 Reserved7:1;
+ UINT32 AVX512_VPOPCNTDQ : 1;
+ UINT32 Reserved7 : 1;
///
/// [Bits 16] Supports 5-level paging if 1.
///
- UINT32 FiveLevelPage:1;
+ UINT32 FiveLevelPage : 1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.
///
- UINT32 MAWAU:5;
+ UINT32 MAWAU : 5;
///
/// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
///
- UINT32 RDPID:1;
- UINT32 Reserved3:7;
+ UINT32 RDPID : 1;
+ UINT32 Reserved3 : 7;
///
/// [Bit 30] Supports SGX Launch Configuration if 1.
///
- UINT32 SGX_LC:1;
- UINT32 Reserved4:1;
+ UINT32 SGX_LC : 1;
+ UINT32 Reserved4 : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
/**
@@ -1540,27 +1533,27 @@ typedef union { ///
/// [Bit 1:0] Reserved.
///
- UINT32 Reserved1:2;
+ UINT32 Reserved1 : 2;
///
/// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
///
- UINT32 AVX512_4VNNIW:1;
+ UINT32 AVX512_4VNNIW : 1;
///
/// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
///
- UINT32 AVX512_4FMAPS:1;
+ UINT32 AVX512_4FMAPS : 1;
///
/// [Bit 14:4] Reserved.
///
- UINT32 Reserved4:11;
+ UINT32 Reserved4 : 11;
///
/// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
///
- UINT32 Hybrid:1;
+ UINT32 Hybrid : 1;
///
/// [Bit 25:16] Reserved.
///
- UINT32 Reserved5:10;
+ UINT32 Reserved5 : 10;
///
/// [Bit 26] Enumerates support for indirect branch restricted speculation
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
@@ -1568,39 +1561,39 @@ typedef union { /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
/// IA32_PRED_CMD[0] (IBPB).
///
- UINT32 EnumeratesSupportForIBRSAndIBPB:1;
+ UINT32 EnumeratesSupportForIBRSAndIBPB : 1;
///
/// [Bit 27] Enumerates support for single thread indirect branch
/// predictors (STIBP). Processors that set this bit support the
/// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
/// (STIBP).
///
- UINT32 EnumeratesSupportForSTIBP:1;
+ UINT32 EnumeratesSupportForSTIBP : 1;
///
/// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
/// support the IA32_FLUSH_CMD MSR. They allow software to set
/// IA32_FLUSH_CMD[0] (L1D_FLUSH).
///
- UINT32 EnumeratesSupportForL1D_FLUSH:1;
+ UINT32 EnumeratesSupportForL1D_FLUSH : 1;
///
/// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
///
- UINT32 EnumeratesSupportForCapability:1;
+ UINT32 EnumeratesSupportForCapability : 1;
///
/// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
///
- UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
/// software to set IA32_SPEC_CTRL[2] (SSBD).
///
- UINT32 EnumeratesSupportForSSBD:1;
+ UINT32 EnumeratesSupportForSSBD : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;
/**
@@ -1620,8 +1613,7 @@ typedef union { AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
-
+#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
/**
CPUID Architectural Performance Monitoring
@@ -1659,7 +1651,7 @@ typedef union { ///
/// [Bit 7:0] Version ID of architectural performance monitoring.
///
- UINT32 ArchPerfMonVerID:8;
+ UINT32 ArchPerfMonVerID : 8;
///
/// [Bits 15:8] Number of general-purpose performance monitoring counter
/// per logical processor.
@@ -1669,7 +1661,7 @@ typedef union { /// paired with a corresponding performance counter in the 0C1H address
/// block.
///
- UINT32 PerformanceMonitorCounters:8;
+ UINT32 PerformanceMonitorCounters : 8;
///
/// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
///
@@ -1678,17 +1670,17 @@ typedef union { /// may be written with any value, and the high-order bits are sign-extended
/// from the value of bit 31.
///
- UINT32 PerformanceMonitorCounterWidth:8;
+ UINT32 PerformanceMonitorCounterWidth : 8;
///
/// [Bits 31:24] Length of EBX bit vector to enumerate architectural
/// performance monitoring events.
///
- UINT32 EbxBitVectorLength:8;
+ UINT32 EbxBitVectorLength : 8;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
/**
@@ -1703,37 +1695,37 @@ typedef union { ///
/// [Bit 0] Core cycle event not available if 1.
///
- UINT32 UnhaltedCoreCycles:1;
+ UINT32 UnhaltedCoreCycles : 1;
///
/// [Bit 1] Instruction retired event not available if 1.
///
- UINT32 InstructionsRetired:1;
+ UINT32 InstructionsRetired : 1;
///
/// [Bit 2] Reference cycles event not available if 1.
///
- UINT32 UnhaltedReferenceCycles:1;
+ UINT32 UnhaltedReferenceCycles : 1;
///
/// [Bit 3] Last-level cache reference event not available if 1.
///
- UINT32 LastLevelCacheReferences:1;
+ UINT32 LastLevelCacheReferences : 1;
///
/// [Bit 4] Last-level cache misses event not available if 1.
///
- UINT32 LastLevelCacheMisses:1;
+ UINT32 LastLevelCacheMisses : 1;
///
/// [Bit 5] Branch instruction retired event not available if 1.
///
- UINT32 BranchInstructionsRetired:1;
+ UINT32 BranchInstructionsRetired : 1;
///
/// [Bit 6] Branch mispredict retired event not available if 1.
///
- UINT32 AllBranchMispredictRetired:1;
- UINT32 Reserved:25;
+ UINT32 AllBranchMispredictRetired : 1;
+ UINT32 Reserved : 25;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
/**
@@ -1749,26 +1741,25 @@ typedef union { /// [Bits 4:0] Number of fixed-function performance counters
/// (if Version ID > 1).
///
- UINT32 FixedFunctionPerformanceCounters:5;
+ UINT32 FixedFunctionPerformanceCounters : 5;
///
/// [Bits 12:5] Bit width of fixed-function performance counters
/// (if Version ID > 1).
///
- UINT32 FixedFunctionPerformanceCounterWidth:8;
- UINT32 Reserved1:2;
+ UINT32 FixedFunctionPerformanceCounterWidth : 8;
+ UINT32 Reserved1 : 2;
///
/// [Bits 15] AnyThread deprecation.
///
- UINT32 AnyThreadDeprecation:1;
- UINT32 Reserved2:16;
+ UINT32 AnyThreadDeprecation : 1;
+ UINT32 Reserved2 : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
-
/**
CPUID Extended Topology Information
@@ -1814,7 +1805,7 @@ typedef union { } while (Eax.Bits.ApicIdShift != 0);
@endcode
**/
-#define CPUID_EXTENDED_TOPOLOGY 0x0B
+#define CPUID_EXTENDED_TOPOLOGY 0x0B
/**
CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
@@ -1833,13 +1824,13 @@ typedef union { /// Software should use this field (EAX[4:0]) to enumerate processor
/// topology of the system.
///
- UINT32 ApicIdShift:5;
- UINT32 Reserved:27;
+ UINT32 ApicIdShift : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_EAX;
/**
@@ -1861,13 +1852,13 @@ typedef union { /// available to BIOS/OS/Applications may be different from the value of
/// EBX[15:0], depending on software and platform hardware configurations.
///
- UINT32 LogicalProcessors:16;
- UINT32 Reserved:16;
+ UINT32 LogicalProcessors : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_EBX;
/**
@@ -1881,7 +1872,7 @@ typedef union { ///
/// [Bits 7:0] Level number. Same value in ECX input.
///
- UINT32 LevelNumber:8;
+ UINT32 LevelNumber : 8;
///
/// [Bits 15:8] Level type.
///
@@ -1889,26 +1880,25 @@ typedef union { /// The value of the "level type" field is not related to level numbers in
/// any way, higher "level type" values do not mean higher levels.
///
- UINT32 LevelType:8;
- UINT32 Reserved:16;
+ UINT32 LevelType : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TOPOLOGY_ECX;
///
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
///
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
///
/// @}
///
-
/**
CPUID Extended State Information
@@ -1918,7 +1908,7 @@ typedef union { CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
**/
-#define CPUID_EXTENDED_STATE 0x0D
+#define CPUID_EXTENDED_STATE 0x0D
/**
CPUID Extended State Information Main Leaf
@@ -1953,7 +1943,7 @@ typedef union { );
@endcode
**/
-#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
/**
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -1967,42 +1957,42 @@ typedef union { ///
/// [Bit 0] x87 state.
///
- UINT32 x87:1;
+ UINT32 x87 : 1;
///
/// [Bit 1] SSE state.
///
- UINT32 SSE:1;
+ UINT32 SSE : 1;
///
/// [Bit 2] AVX state.
///
- UINT32 AVX:1;
+ UINT32 AVX : 1;
///
/// [Bits 4:3] MPX state.
///
- UINT32 MPX:2;
+ UINT32 MPX : 2;
///
/// [Bits 7:5] AVX-512 state.
///
- UINT32 AVX_512:3;
+ UINT32 AVX_512 : 3;
///
/// [Bit 8] Used for IA32_XSS.
///
- UINT32 IA32_XSS:1;
+ UINT32 IA32_XSS : 1;
///
/// [Bit 9] PKRU state.
///
- UINT32 PKRU:1;
- UINT32 Reserved1:3;
+ UINT32 PKRU : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 13] Used for IA32_XSS, part 2.
///
- UINT32 IA32_XSS_2:1;
- UINT32 Reserved2:18;
+ UINT32 IA32_XSS_2 : 1;
+ UINT32 Reserved2 : 18;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
/**
@@ -2033,7 +2023,7 @@ typedef union { );
@endcode
**/
-#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
/**
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -2047,25 +2037,25 @@ typedef union { ///
/// [Bit 0] XSAVEOPT is available.
///
- UINT32 XSAVEOPT:1;
+ UINT32 XSAVEOPT : 1;
///
/// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
///
- UINT32 XSAVEC:1;
+ UINT32 XSAVEC : 1;
///
/// [Bit 2] Supports XGETBV with ECX = 1 if set.
///
- UINT32 XGETBV:1;
+ UINT32 XGETBV : 1;
///
/// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
///
- UINT32 XSAVES:1;
- UINT32 Reserved:28;
+ UINT32 XSAVES : 1;
+ UINT32 Reserved : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
/**
@@ -2080,26 +2070,26 @@ typedef union { ///
/// [Bits 7:0] Used for XCR0.
///
- UINT32 XCR0:1;
+ UINT32 XCR0 : 1;
///
/// [Bit 8] PT STate.
///
- UINT32 PT:1;
+ UINT32 PT : 1;
///
/// [Bit 9] Used for XCR0.
///
- UINT32 XCR0_1:1;
- UINT32 Reserved1:3;
+ UINT32 XCR0_1 : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 13] HWP state.
///
- UINT32 HWPState:1;
- UINT32 Reserved8:18;
+ UINT32 HWPState : 1;
+ UINT32 Reserved8 : 18;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
/**
@@ -2147,7 +2137,7 @@ typedef union { }
@endcode
**/
-#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
/**
CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
@@ -2163,23 +2153,22 @@ typedef union { /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
/// in XCR0.
///
- UINT32 XSS:1;
+ UINT32 XSS : 1;
///
/// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
/// this extended state component located on the next 64-byte boundary
/// following the preceding state component (otherwise, it is located
/// immediately following the preceding state component).
///
- UINT32 Compacted:1;
- UINT32 Reserved:30;
+ UINT32 Compacted : 1;
+ UINT32 Reserved : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
-
/**
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
@@ -2188,7 +2177,7 @@ typedef union { CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
**/
-#define CPUID_INTEL_RDT_MONITORING 0x0F
+#define CPUID_INTEL_RDT_MONITORING 0x0F
/**
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
@@ -2215,7 +2204,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
/**
CPUID Intel RDT Monitoring Information EDX for CPUID leaf
@@ -2227,17 +2216,17 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
///
- UINT32 L3CacheRDT_M:1;
- UINT32 Reserved2:30;
+ UINT32 L3CacheRDT_M : 1;
+ UINT32 Reserved2 : 30;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
/**
@@ -2264,7 +2253,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
/**
CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
@@ -2279,24 +2268,23 @@ typedef union { ///
/// [Bit 0] Supports L3 occupancy monitoring if 1.
///
- UINT32 L3CacheOccupancyMonitoring:1;
+ UINT32 L3CacheOccupancyMonitoring : 1;
///
/// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
///
- UINT32 L3CacheTotalBandwidthMonitoring:1;
+ UINT32 L3CacheTotalBandwidthMonitoring : 1;
///
/// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
///
- UINT32 L3CacheLocalBandwidthMonitoring:1;
- UINT32 Reserved:29;
+ UINT32 L3CacheLocalBandwidthMonitoring : 1;
+ UINT32 Reserved : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
-
/**
CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
@@ -2305,7 +2293,7 @@ typedef union { CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
**/
-#define CPUID_INTEL_RDT_ALLOCATION 0x10
+#define CPUID_INTEL_RDT_ALLOCATION 0x10
/**
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
@@ -2329,7 +2317,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
/**
CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
@@ -2341,28 +2329,27 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Supports L3 Cache Allocation Technology if 1.
///
- UINT32 L3CacheAllocation:1;
+ UINT32 L3CacheAllocation : 1;
///
/// [Bit 2] Supports L2 Cache Allocation Technology if 1.
///
- UINT32 L2CacheAllocation:1;
+ UINT32 L2CacheAllocation : 1;
///
/// [Bit 3] Supports Memory Bandwidth Allocation if 1.
///
- UINT32 MemoryBandwidth:1;
- UINT32 Reserved3:28;
+ UINT32 MemoryBandwidth : 1;
+ UINT32 Reserved3 : 28;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
-
/**
L3 Cache Allocation Technology Enumeration Sub-leaf
@@ -2390,7 +2377,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
/**
CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
@@ -2406,13 +2393,13 @@ typedef union { /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
/// using minus-one notation.
///
- UINT32 CapacityLength:5;
- UINT32 Reserved:27;
+ UINT32 CapacityLength : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
/**
@@ -2425,17 +2412,17 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved3:2;
+ UINT32 Reserved3 : 2;
///
/// [Bit 2] Code and Data Prioritization Technology supported if 1.
///
- UINT32 CodeDataPrioritization:1;
- UINT32 Reserved2:29;
+ UINT32 CodeDataPrioritization : 1;
+ UINT32 Reserved2 : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
/**
@@ -2451,13 +2438,13 @@ typedef union { ///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
/**
@@ -2485,7 +2472,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
/**
CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
@@ -2501,13 +2488,13 @@ typedef union { /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
/// using minus-one notation.
///
- UINT32 CapacityLength:5;
- UINT32 Reserved:27;
+ UINT32 CapacityLength : 5;
+ UINT32 Reserved : 27;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
/**
@@ -2523,13 +2510,13 @@ typedef union { ///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
/**
@@ -2563,7 +2550,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
/**
CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
@@ -2579,13 +2566,13 @@ typedef union { /// [Bits 11:0] Reports the maximum MBA throttling value supported for
/// the corresponding ResID using minus-one notation.
///
- UINT32 MaximumMBAThrottling:12;
- UINT32 Reserved:20;
+ UINT32 MaximumMBAThrottling : 12;
+ UINT32 Reserved : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;
/**
@@ -2601,17 +2588,17 @@ typedef union { ///
/// [Bits 1:0] Reserved.
///
- UINT32 Reserved1:2;
+ UINT32 Reserved1 : 2;
///
/// [Bits 3] Reports whether the response of the delay values is linear.
///
- UINT32 Liner:1;
- UINT32 Reserved2:29;
+ UINT32 Liner : 1;
+ UINT32 Reserved2 : 29;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;
/**
@@ -2627,13 +2614,13 @@ typedef union { ///
/// [Bits 15:0] Highest COS number supported for this ResID.
///
- UINT32 HighestCosNumber:16;
- UINT32 Reserved:16;
+ UINT32 HighestCosNumber : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;
/**
@@ -2651,7 +2638,7 @@ typedef union { until the sub-leaf type is invalid.
**/
-#define CPUID_INTEL_SGX 0x12
+#define CPUID_INTEL_SGX 0x12
/**
Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
@@ -2680,7 +2667,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
/**
Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
@@ -2694,28 +2681,28 @@ typedef union { ///
/// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
///
- UINT32 SGX1:1;
+ UINT32 SGX1 : 1;
///
/// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
///
- UINT32 SGX2:1;
- UINT32 Reserved1:3;
+ UINT32 SGX2 : 1;
+ UINT32 Reserved1 : 3;
///
/// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
/// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
///
- UINT32 ENCLV:1;
+ UINT32 ENCLV : 1;
///
/// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
/// ERDINFO, ELDBC, and ELDUC.
///
- UINT32 ENCLS:1;
- UINT32 Reserved2:25;
+ UINT32 ENCLS : 1;
+ UINT32 Reserved2 : 25;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
/**
@@ -2731,21 +2718,20 @@ typedef union { /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
/// when not in 64-bit mode.
///
- UINT32 MaxEnclaveSize_Not64:8;
+ UINT32 MaxEnclaveSize_Not64 : 8;
///
/// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
/// when operating in 64-bit mode.
///
- UINT32 MaxEnclaveSize_64:8;
- UINT32 Reserved:16;
+ UINT32 MaxEnclaveSize_64 : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
-
/**
Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
Enumerates Intel SGX capability of processor state configuration and enclave
@@ -2780,8 +2766,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
-
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
/**
Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
@@ -2834,18 +2819,18 @@ typedef union { /// in EBX:EAX and EDX:ECX.
/// All other encoding are reserved.
///
- UINT32 SubLeafType:4;
- UINT32 Reserved:8;
+ UINT32 SubLeafType : 4;
+ UINT32 Reserved : 8;
///
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
/// the base of the EPC section.
///
- UINT32 LowAddressOfEpcSection:20;
+ UINT32 LowAddressOfEpcSection : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
/**
@@ -2861,13 +2846,13 @@ typedef union { /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
/// the base of the EPC section.
///
- UINT32 HighAddressOfEpcSection:20;
- UINT32 Reserved:12;
+ UINT32 HighAddressOfEpcSection : 20;
+ UINT32 Reserved : 12;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
/**
@@ -2885,18 +2870,18 @@ typedef union { /// 0001b: The EPC section is confidentiality, integrity and replay protected.
/// All other encoding are reserved.
///
- UINT32 EpcSection:4;
- UINT32 Reserved:8;
+ UINT32 EpcSection : 4;
+ UINT32 Reserved : 8;
///
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
/// corresponding EPC section within the Processor Reserved Memory.
///
- UINT32 LowSizeOfEpcSection:20;
+ UINT32 LowSizeOfEpcSection : 20;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
/**
@@ -2912,16 +2897,15 @@ typedef union { /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
/// corresponding EPC section within the Processor Reserved Memory.
///
- UINT32 HighSizeOfEpcSection:20;
- UINT32 Reserved:12;
+ UINT32 HighSizeOfEpcSection : 20;
+ UINT32 Reserved : 12;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
-
/**
CPUID Intel Processor Trace Information
@@ -2930,7 +2914,7 @@ typedef union { CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
**/
-#define CPUID_INTEL_PROCESSOR_TRACE 0x14
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14
/**
CPUID Intel Processor Trace Information Main Leaf
@@ -2957,7 +2941,7 @@ typedef union { );
@endcode
**/
-#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
/**
CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
@@ -2972,40 +2956,40 @@ typedef union { /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
///
- UINT32 Cr3Filter:1;
+ UINT32 Cr3Filter : 1;
///
/// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
/// Mode.
///
- UINT32 ConfigurablePsb:1;
+ UINT32 ConfigurablePsb : 1;
///
/// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
/// and preservation of Intel PT MSRs across warm reset.
///
- UINT32 IpTraceStopFiltering:1;
+ UINT32 IpTraceStopFiltering : 1;
///
/// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
/// COFI-based packets.
///
- UINT32 Mtc:1;
+ UINT32 Mtc : 1;
///
/// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
/// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
/// can generate packets.
///
- UINT32 PTWrite:1;
+ UINT32 PTWrite : 1;
///
/// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
/// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
/// generation.
///
- UINT32 PowerEventTrace:1;
- UINT32 Reserved:26;
+ UINT32 PowerEventTrace : 1;
+ UINT32 Reserved : 26;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
/**
@@ -3022,35 +3006,34 @@ typedef union { /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
/// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
///
- UINT32 RTIT:1;
+ UINT32 RTIT : 1;
///
/// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
/// the maximum allowed by the MaskOrTableOffset field of
/// IA32_RTIT_OUTPUT_MASK_PTRS.
///
- UINT32 ToPA:1;
+ UINT32 ToPA : 1;
///
/// [Bit 2] If 1, indicates support of Single-Range Output scheme.
///
- UINT32 SingleRangeOutput:1;
+ UINT32 SingleRangeOutput : 1;
///
/// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
///
- UINT32 TraceTransportSubsystem:1;
- UINT32 Reserved:27;
+ UINT32 TraceTransportSubsystem : 1;
+ UINT32 Reserved : 27;
///
/// [Bit 31] If 1, generated packets which contain IP payloads have LIP
/// values, which include the CS base component.
///
- UINT32 LIP:1;
+ UINT32 LIP : 1;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
-
/**
CPUID Intel Processor Trace Information Sub-leaf
@@ -3084,7 +3067,7 @@ typedef union { }
@endcode
**/
-#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
/**
CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
@@ -3098,18 +3081,17 @@ typedef union { ///
/// [Bits 2:0] Number of configurable Address Ranges for filtering.
///
- UINT32 ConfigurableAddressRanges:3;
- UINT32 Reserved:13;
+ UINT32 ConfigurableAddressRanges : 3;
+ UINT32 Reserved : 13;
///
/// [Bits 31:16] Bitmap of supported MTC period encodings
///
- UINT32 MtcPeriodEncodings:16;
-
+ UINT32 MtcPeriodEncodings : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
/**
@@ -3124,20 +3106,18 @@ typedef union { ///
/// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
///
- UINT32 CycleThresholdEncodings:16;
+ UINT32 CycleThresholdEncodings : 16;
///
/// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
///
- UINT32 PsbFrequencyEncodings:16;
-
+ UINT32 PsbFrequencyEncodings : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
-
/**
CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
@@ -3169,8 +3149,7 @@ typedef union { AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
@endcode
**/
-#define CPUID_TIME_STAMP_COUNTER 0x15
-
+#define CPUID_TIME_STAMP_COUNTER 0x15
/**
CPUID Processor Frequency Information
@@ -3205,7 +3184,7 @@ typedef union { AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_PROCESSOR_FREQUENCY 0x16
+#define CPUID_PROCESSOR_FREQUENCY 0x16
/**
CPUID Processor Frequency Information EAX for CPUID leaf
@@ -3219,13 +3198,13 @@ typedef union { ///
/// [Bits 15:0] Processor Base Frequency (in MHz).
///
- UINT32 ProcessorBaseFrequency:16;
- UINT32 Reserved:16;
+ UINT32 ProcessorBaseFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_EAX;
/**
@@ -3240,13 +3219,13 @@ typedef union { ///
/// [Bits 15:0] Maximum Frequency (in MHz).
///
- UINT32 MaximumFrequency:16;
- UINT32 Reserved:16;
+ UINT32 MaximumFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_EBX;
/**
@@ -3261,16 +3240,15 @@ typedef union { ///
/// [Bits 15:0] Bus (Reference) Frequency (in MHz).
///
- UINT32 BusFrequency:16;
- UINT32 Reserved:16;
+ UINT32 BusFrequency : 16;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_PROCESSOR_FREQUENCY_ECX;
-
/**
CPUID SoC Vendor Information
@@ -3287,7 +3265,7 @@ typedef union { EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
**/
-#define CPUID_SOC_VENDOR 0x17
+#define CPUID_SOC_VENDOR 0x17
/**
CPUID SoC Vendor Information
@@ -3317,7 +3295,7 @@ typedef union { );
@endcode
**/
-#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
/**
CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
@@ -3331,19 +3309,19 @@ typedef union { ///
/// [Bits 15:0] SOC Vendor ID.
///
- UINT32 SocVendorId:16;
+ UINT32 SocVendorId : 16;
///
/// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
/// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
/// assigned by Intel.
///
- UINT32 IsVendorScheme:1;
- UINT32 Reserved:15;
+ UINT32 IsVendorScheme : 1;
+ UINT32 Reserved : 15;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
/**
@@ -3374,7 +3352,7 @@ typedef union { );
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
/**
CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
@@ -3384,11 +3362,11 @@ typedef union { ///
/// 4 UTF-8 characters of Soc Vendor Brand String
///
- CHAR8 BrandString[4];
+ CHAR8 BrandString[4];
///
/// All fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_SOC_VENDOR_BRAND_STRING_DATA;
/**
@@ -3419,7 +3397,7 @@ typedef union { );
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
/**
CPUID SoC Vendor Information
@@ -3449,7 +3427,7 @@ typedef union { );
@endcode
**/
-#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
/**
CPUID Deterministic Address Translation Parameters
@@ -3474,7 +3452,7 @@ typedef union { CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
**/
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
/**
CPUID Deterministic Address Translation Parameters
@@ -3503,7 +3481,7 @@ typedef union { );
@endcode
**/
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
/**
CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
@@ -3516,41 +3494,41 @@ typedef union { ///
/// [Bits 0] 4K page size entries supported by this structure.
///
- UINT32 Page4K:1;
+ UINT32 Page4K : 1;
///
/// [Bits 1] 2MB page size entries supported by this structure.
///
- UINT32 Page2M:1;
+ UINT32 Page2M : 1;
///
/// [Bits 2] 4MB page size entries supported by this structure.
///
- UINT32 Page4M:1;
+ UINT32 Page4M : 1;
///
/// [Bits 3] 1 GB page size entries supported by this structure.
///
- UINT32 Page1G:1;
+ UINT32 Page1G : 1;
///
/// [Bits 7:4] Reserved.
///
- UINT32 Reserved1:4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
/// processors sharing this structure)
///
- UINT32 Partitioning:3;
+ UINT32 Partitioning : 3;
///
/// [Bits 15:11] Reserved.
///
- UINT32 Reserved2:5;
+ UINT32 Reserved2 : 5;
///
/// [Bits 31:16] W = Ways of associativity.
///
- UINT32 Way:16;
+ UINT32 Way : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;
/**
@@ -3564,33 +3542,33 @@ typedef union { ///
/// [Bits 4:0] Translation cache type field.
///
- UINT32 TranslationCacheType:5;
+ UINT32 TranslationCacheType : 5;
///
/// [Bits 7:5] Translation cache level (starts at 1).
///
- UINT32 TranslationCacheLevel:3;
+ UINT32 TranslationCacheLevel : 3;
///
/// [Bits 8] Fully associative structure.
///
- UINT32 FullyAssociative:1;
+ UINT32 FullyAssociative : 1;
///
/// [Bits 13:9] Reserved.
///
- UINT32 Reserved1:5;
+ UINT32 Reserved1 : 5;
///
/// [Bits 25:14] Maximum number of addressable IDs for logical
/// processors sharing this translation cache.
///
- UINT32 MaximumNum:12;
+ UINT32 MaximumNum : 12;
///
/// [Bits 31:26] Reserved.
///
- UINT32 Reserved2:6;
+ UINT32 Reserved2 : 6;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;
///
@@ -3604,7 +3582,6 @@ typedef union { /// @}
///
-
/**
CPUID Hybrid Information Enumeration Leaf
@@ -3629,12 +3606,12 @@ typedef union { @endcode
**/
-#define CPUID_HYBRID_INFORMATION 0x1A
+#define CPUID_HYBRID_INFORMATION 0x1A
///
/// CPUID Hybrid Information Enumeration main leaf
///
-#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00
+#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00
/**
CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,
@@ -3653,28 +3630,27 @@ typedef union { /// across core types, and not related to the model ID reported in CPUID
/// leaf 01H, and does not identify the SOC.
///
- UINT32 NativeModelId:24;
+ UINT32 NativeModelId : 24;
///
/// [Bit 31:24] Core type
///
- UINT32 CoreType:8;
+ UINT32 CoreType : 8;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;
///
/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType
///
-#define CPUID_CORE_TYPE_INTEL_ATOM 0x20
-#define CPUID_CORE_TYPE_INTEL_CORE 0x40
+#define CPUID_CORE_TYPE_INTEL_ATOM 0x20
+#define CPUID_CORE_TYPE_INTEL_CORE 0x40
///
/// @}
///
-
/**
CPUID V2 Extended Topology Enumeration Leaf
@@ -3699,16 +3675,16 @@ typedef union { @param ECX Level number
**/
-#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
+#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
///
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
/// The value of the "level type" field is not related to level numbers in
/// any way, higher "level type" values do not mean higher levels.
///
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
///
/// @}
///
@@ -3730,8 +3706,7 @@ typedef union { AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_EXTENDED_FUNCTION 0x80000000
-
+#define CPUID_EXTENDED_FUNCTION 0x80000000
/**
CPUID Extended Processor Signature and Feature Bits
@@ -3754,7 +3729,7 @@ typedef union { AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_EXTENDED_CPU_SIG 0x80000001
+#define CPUID_EXTENDED_CPU_SIG 0x80000001
/**
CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
@@ -3768,23 +3743,23 @@ typedef union { ///
/// [Bit 0] LAHF/SAHF available in 64-bit mode.
///
- UINT32 LAHF_SAHF:1;
- UINT32 Reserved1:4;
+ UINT32 LAHF_SAHF : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 5] LZCNT.
///
- UINT32 LZCNT:1;
- UINT32 Reserved2:2;
+ UINT32 LZCNT : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 8] PREFETCHW.
///
- UINT32 PREFETCHW:1;
- UINT32 Reserved3:23;
+ UINT32 PREFETCHW : 1;
+ UINT32 Reserved3 : 23;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CPU_SIG_ECX;
/**
@@ -3796,39 +3771,38 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
///
- UINT32 SYSCALL_SYSRET:1;
- UINT32 Reserved2:8;
+ UINT32 SYSCALL_SYSRET : 1;
+ UINT32 Reserved2 : 8;
///
/// [Bit 20] Execute Disable Bit available.
///
- UINT32 NX:1;
- UINT32 Reserved3:5;
+ UINT32 NX : 1;
+ UINT32 Reserved3 : 5;
///
/// [Bit 26] 1-GByte pages are available if 1.
///
- UINT32 Page1GB:1;
+ UINT32 Page1GB : 1;
///
/// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
///
- UINT32 RDTSCP:1;
- UINT32 Reserved4:1;
+ UINT32 RDTSCP : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 29] Intel(R) 64 Architecture available if 1.
///
- UINT32 LM:1;
- UINT32 Reserved5:2;
+ UINT32 LM : 1;
+ UINT32 Reserved5 : 2;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CPU_SIG_EDX;
-
/**
CPUID Processor Brand String
@@ -3849,7 +3823,7 @@ typedef union { AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING1 0x80000002
+#define CPUID_BRAND_STRING1 0x80000002
/**
CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
@@ -3859,11 +3833,11 @@ typedef union { ///
/// 4 ASCII characters of Processor Brand String
///
- CHAR8 BrandString[4];
+ CHAR8 BrandString[4];
///
/// All fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_BRAND_STRING_DATA;
/**
@@ -3886,7 +3860,7 @@ typedef union { AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING2 0x80000003
+#define CPUID_BRAND_STRING2 0x80000003
/**
CPUID Processor Brand String
@@ -3908,8 +3882,7 @@ typedef union { AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@endcode
**/
-#define CPUID_BRAND_STRING3 0x80000004
-
+#define CPUID_BRAND_STRING3 0x80000004
/**
CPUID Extended Cache information
@@ -3929,7 +3902,7 @@ typedef union { AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
@endcode
**/
-#define CPUID_EXTENDED_CACHE_INFO 0x80000006
+#define CPUID_EXTENDED_CACHE_INFO 0x80000006
/**
CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
@@ -3942,23 +3915,23 @@ typedef union { ///
/// [Bits 7:0] Cache line size in bytes.
///
- UINT32 CacheLineSize:8;
- UINT32 Reserved:4;
+ UINT32 CacheLineSize : 8;
+ UINT32 Reserved : 4;
///
/// [Bits 15:12] L2 Associativity field. Supported values are in the range
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
///
- UINT32 L2Associativity:4;
+ UINT32 L2Associativity : 4;
///
/// [Bits 31:16] Cache size in 1K units.
///
- UINT32 CacheSize:16;
+ UINT32 CacheSize : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_CACHE_INFO_ECX;
///
@@ -3998,7 +3971,7 @@ typedef union { AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
@endcode
**/
-#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
/**
CPUID Extended Time Stamp Counter information EDX for CPUID leaf
@@ -4009,20 +3982,19 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bit 8] Invariant TSC available if 1.
///
- UINT32 InvariantTsc:1;
- UINT32 Reserved2:23;
+ UINT32 InvariantTsc : 1;
+ UINT32 Reserved2 : 23;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
-
/**
CPUID Linear Physical Address Size
@@ -4041,7 +4013,7 @@ typedef union { AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
@endcode
**/
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
/**
CPUID Linear Physical Address Size EAX for CPUID leaf
@@ -4059,17 +4031,17 @@ typedef union { /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
/// number supported should come from this field.
///
- UINT32 PhysicalAddressBits:8;
+ UINT32 PhysicalAddressBits : 8;
///
/// [Bits 15:8] Number of linear address bits.
///
- UINT32 LinearAddressBits:8;
- UINT32 Reserved:16;
+ UINT32 LinearAddressBits : 8;
+ UINT32 Reserved : 16;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
#endif
|