diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/CoreMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/CoreMsr.h | 284 |
1 files changed, 126 insertions, 158 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/CoreMsr.h b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h index 1e43bc13f5..71de1984d3 100644 --- a/MdePkg/Include/Register/Intel/Msr/CoreMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h @@ -52,8 +52,7 @@ @endcode
@note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
-#define MSR_CORE_P5_MC_ADDR 0x00000000
-
+#define MSR_CORE_P5_MC_ADDR 0x00000000
/**
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
@@ -71,8 +70,7 @@ @endcode
@note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
-#define MSR_CORE_P5_MC_TYPE 0x00000001
-
+#define MSR_CORE_P5_MC_TYPE 0x00000001
/**
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
@@ -93,7 +91,7 @@ @endcode
@note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
-#define MSR_CORE_EBL_CR_POWERON 0x0000002A
+#define MSR_CORE_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
@@ -103,87 +101,86 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Note: Not all processor implements R/W.
///
- UINT32 DataErrorCheckingEnable:1;
+ UINT32 DataErrorCheckingEnable : 1;
///
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
/// Note: Not all processor implements R/W.
///
- UINT32 ResponseErrorCheckingEnable:1;
+ UINT32 ResponseErrorCheckingEnable : 1;
///
/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
/// all processor implements R/W.
///
- UINT32 MCERR_DriveEnable:1;
+ UINT32 MCERR_DriveEnable : 1;
///
/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
/// Not all processor implements R/W.
///
- UINT32 AddressParityEnable:1;
- UINT32 Reserved2:2;
+ UINT32 AddressParityEnable : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
/// all processor implements R/W.
///
- UINT32 BINIT_DriverEnable:1;
+ UINT32 BINIT_DriverEnable : 1;
///
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 OutputTriStateEnable:1;
+ UINT32 OutputTriStateEnable : 1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 ExecuteBIST:1;
+ UINT32 ExecuteBIST : 1;
///
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 MCERR_ObservationEnabled:1;
- UINT32 Reserved3:1;
+ UINT32 MCERR_ObservationEnabled : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved4:1;
+ UINT32 BINIT_ObservationEnabled : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
///
- UINT32 ResetVector:1;
- UINT32 Reserved5:1;
+ UINT32 ResetVector : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bits 17:16] APIC Cluster ID (R/O).
///
- UINT32 APICClusterID:2;
+ UINT32 APICClusterID : 2;
///
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
///
- UINT32 SystemBusFrequency:1;
- UINT32 Reserved6:1;
+ UINT32 SystemBusFrequency : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O).
///
- UINT32 SymmetricArbitrationID:2;
+ UINT32 SymmetricArbitrationID : 2;
///
/// [Bits 26:22] Clock Frequency Ratio (R/O).
///
- UINT32 ClockFrequencyRatio:5;
- UINT32 Reserved7:5;
- UINT32 Reserved8:32;
+ UINT32 ClockFrequencyRatio : 5;
+ UINT32 Reserved7 : 5;
+ UINT32 Reserved8 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_EBL_CR_POWERON_REGISTER;
-
/**
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
the last branch record stack: bits 31-0 hold the 'from' address and bits
@@ -212,17 +209,16 @@ typedef union { MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
@{
**/
-#define MSR_CORE_LASTBRANCH_0 0x00000040
-#define MSR_CORE_LASTBRANCH_1 0x00000041
-#define MSR_CORE_LASTBRANCH_2 0x00000042
-#define MSR_CORE_LASTBRANCH_3 0x00000043
-#define MSR_CORE_LASTBRANCH_4 0x00000044
-#define MSR_CORE_LASTBRANCH_5 0x00000045
-#define MSR_CORE_LASTBRANCH_6 0x00000046
-#define MSR_CORE_LASTBRANCH_7 0x00000047
+#define MSR_CORE_LASTBRANCH_0 0x00000040
+#define MSR_CORE_LASTBRANCH_1 0x00000041
+#define MSR_CORE_LASTBRANCH_2 0x00000042
+#define MSR_CORE_LASTBRANCH_3 0x00000043
+#define MSR_CORE_LASTBRANCH_4 0x00000044
+#define MSR_CORE_LASTBRANCH_5 0x00000045
+#define MSR_CORE_LASTBRANCH_6 0x00000046
+#define MSR_CORE_LASTBRANCH_7 0x00000047
/// @}
-
/**
Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
clock speed:.
@@ -241,7 +237,7 @@ typedef union { @endcode
@note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
**/
-#define MSR_CORE_FSB_FREQ 0x000000CD
+#define MSR_CORE_FSB_FREQ 0x000000CD
/**
MSR information returned for MSR index #MSR_CORE_FSB_FREQ
@@ -261,21 +257,20 @@ typedef union { /// Speed when encoding is 101B. 166.67 MHz should be utilized if
/// performing calculation with System Bus Speed when encoding is 001B.
///
- UINT32 ScalableBusSpeed:3;
- UINT32 Reserved1:29;
- UINT32 Reserved2:32;
+ UINT32 ScalableBusSpeed : 3;
+ UINT32 Reserved1 : 29;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_FSB_FREQ_REGISTER;
-
/**
Shared.
@@ -294,7 +289,7 @@ typedef union { @endcode
@note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
-#define MSR_CORE_BBL_CR_CTL3 0x0000011E
+#define MSR_CORE_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
@@ -308,33 +303,32 @@ typedef union { /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
+ UINT32 L2HardwareEnabled : 1;
+ UINT32 Reserved1 : 7;
///
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
+ UINT32 L2Enabled : 1;
+ UINT32 Reserved2 : 14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
+ UINT32 L2NotPresent : 1;
+ UINT32 Reserved3 : 8;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_BBL_CR_CTL3_REGISTER;
-
/**
Unique.
@@ -353,7 +347,7 @@ typedef union { @endcode
@note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
-#define MSR_CORE_THERM2_CTL 0x0000019D
+#define MSR_CORE_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_CORE_THERM2_CTL
@@ -363,7 +357,7 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
@@ -371,21 +365,20 @@ typedef union { /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
+ UINT32 TM_SELECT : 1;
+ UINT32 Reserved2 : 15;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_THERM2_CTL_REGISTER;
-
/**
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -405,7 +398,7 @@ typedef union { @endcode
@note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
+#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
@@ -415,30 +408,30 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:3;
+ UINT32 Reserved1 : 3;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 2-2.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:2;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 2;
///
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
/// the processor to indicate a pending break event within the processor 0
/// = Indicates compatible FERR# signaling behavior This bit must be set
/// to 1 to support XAPIC interrupt model usage.
///
- UINT32 FERR:1;
+ UINT32 FERR : 1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
- UINT32 BTS:1;
- UINT32 Reserved4:1;
+ UINT32 BTS : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
/// thermal sensor indicates that the die temperature is at the
@@ -453,41 +446,40 @@ typedef union { /// out of spec if both this bit and the TM1 bit are set to disabled
/// states.
///
- UINT32 TM2:1;
- UINT32 Reserved5:2;
+ UINT32 TM2 : 1;
+ UINT32 Reserved5 : 2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
/// Enhanced Intel SpeedStep Technology enabled.
///
- UINT32 EIST:1;
- UINT32 Reserved6:1;
+ UINT32 EIST : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
- UINT32 MONITOR:1;
- UINT32 Reserved7:1;
- UINT32 Reserved8:2;
+ UINT32 MONITOR : 1;
+ UINT32 Reserved7 : 1;
+ UINT32 Reserved8 : 2;
///
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
/// bit may cause behavior in software that depends on the availability of
/// CPUID leaves greater than 2.
///
- UINT32 LimitCpuidMaxval:1;
- UINT32 Reserved9:9;
- UINT32 Reserved10:2;
+ UINT32 LimitCpuidMaxval : 1;
+ UINT32 Reserved9 : 9;
+ UINT32 Reserved10 : 2;
///
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
///
- UINT32 XD:1;
- UINT32 Reserved11:29;
+ UINT32 XD : 1;
+ UINT32 Reserved11 : 29;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
-
/**
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
that points to the MSR containing the most recent branch record. See
@@ -506,8 +498,7 @@ typedef union { @endcode
@note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
-#define MSR_CORE_LASTBRANCH_TOS 0x000001C9
-
+#define MSR_CORE_LASTBRANCH_TOS 0x000001C9
/**
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
@@ -526,8 +517,7 @@ typedef union { @endcode
@note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
-#define MSR_CORE_LER_FROM_LIP 0x000001DD
-
+#define MSR_CORE_LER_FROM_LIP 0x000001DD
/**
Unique. Last Exception Record To Linear IP (R) This area contains a pointer
@@ -547,7 +537,7 @@ typedef union { @endcode
@note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
-#define MSR_CORE_LER_TO_LIP 0x000001DE
+#define MSR_CORE_LER_TO_LIP 0x000001DE
/**
Unique.
@@ -573,17 +563,16 @@ typedef union { MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
@{
**/
-#define MSR_CORE_MTRRPHYSBASE0 0x00000200
-#define MSR_CORE_MTRRPHYSBASE1 0x00000202
-#define MSR_CORE_MTRRPHYSBASE2 0x00000204
-#define MSR_CORE_MTRRPHYSBASE3 0x00000206
-#define MSR_CORE_MTRRPHYSBASE4 0x00000208
-#define MSR_CORE_MTRRPHYSBASE5 0x0000020A
-#define MSR_CORE_MTRRPHYSMASK6 0x0000020D
-#define MSR_CORE_MTRRPHYSMASK7 0x0000020F
+#define MSR_CORE_MTRRPHYSBASE0 0x00000200
+#define MSR_CORE_MTRRPHYSBASE1 0x00000202
+#define MSR_CORE_MTRRPHYSBASE2 0x00000204
+#define MSR_CORE_MTRRPHYSBASE3 0x00000206
+#define MSR_CORE_MTRRPHYSBASE4 0x00000208
+#define MSR_CORE_MTRRPHYSBASE5 0x0000020A
+#define MSR_CORE_MTRRPHYSMASK6 0x0000020D
+#define MSR_CORE_MTRRPHYSMASK7 0x0000020F
/// @}
-
/**
Unique.
@@ -608,17 +597,16 @@ typedef union { MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
@{
**/
-#define MSR_CORE_MTRRPHYSMASK0 0x00000201
-#define MSR_CORE_MTRRPHYSMASK1 0x00000203
-#define MSR_CORE_MTRRPHYSMASK2 0x00000205
-#define MSR_CORE_MTRRPHYSMASK3 0x00000207
-#define MSR_CORE_MTRRPHYSMASK4 0x00000209
-#define MSR_CORE_MTRRPHYSMASK5 0x0000020B
-#define MSR_CORE_MTRRPHYSBASE6 0x0000020C
-#define MSR_CORE_MTRRPHYSBASE7 0x0000020E
+#define MSR_CORE_MTRRPHYSMASK0 0x00000201
+#define MSR_CORE_MTRRPHYSMASK1 0x00000203
+#define MSR_CORE_MTRRPHYSMASK2 0x00000205
+#define MSR_CORE_MTRRPHYSMASK3 0x00000207
+#define MSR_CORE_MTRRPHYSMASK4 0x00000209
+#define MSR_CORE_MTRRPHYSMASK5 0x0000020B
+#define MSR_CORE_MTRRPHYSBASE6 0x0000020C
+#define MSR_CORE_MTRRPHYSBASE7 0x0000020E
/// @}
-
/**
Unique.
@@ -635,8 +623,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
**/
-#define MSR_CORE_MTRRFIX64K_00000 0x00000250
-
+#define MSR_CORE_MTRRFIX64K_00000 0x00000250
/**
Unique.
@@ -654,8 +641,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
**/
-#define MSR_CORE_MTRRFIX16K_80000 0x00000258
-
+#define MSR_CORE_MTRRFIX16K_80000 0x00000258
/**
Unique.
@@ -673,8 +659,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
**/
-#define MSR_CORE_MTRRFIX16K_A0000 0x00000259
-
+#define MSR_CORE_MTRRFIX16K_A0000 0x00000259
/**
Unique.
@@ -692,8 +677,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_C0000 0x00000268
-
+#define MSR_CORE_MTRRFIX4K_C0000 0x00000268
/**
Unique.
@@ -711,8 +695,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_C8000 0x00000269
-
+#define MSR_CORE_MTRRFIX4K_C8000 0x00000269
/**
Unique.
@@ -730,8 +713,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
-
+#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
/**
Unique.
@@ -749,8 +731,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
-
+#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
/**
Unique.
@@ -768,8 +749,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
-
+#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
/**
Unique.
@@ -787,8 +767,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
-
+#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
/**
Unique.
@@ -806,8 +785,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
-
+#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
/**
Unique.
@@ -825,8 +803,7 @@ typedef union { @endcode
@note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
**/
-#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
-
+#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
/**
Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@@ -844,8 +821,7 @@ typedef union { @endcode
@note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
-#define MSR_CORE_MC4_CTL 0x0000040C
-
+#define MSR_CORE_MC4_CTL 0x0000040C
/**
Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@@ -863,8 +839,7 @@ typedef union { @endcode
@note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
-#define MSR_CORE_MC4_STATUS 0x0000040D
-
+#define MSR_CORE_MC4_STATUS 0x0000040D
/**
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
@@ -886,8 +861,7 @@ typedef union { @endcode
@note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
-#define MSR_CORE_MC4_ADDR 0x0000040E
-
+#define MSR_CORE_MC4_ADDR 0x0000040E
/**
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
@@ -909,8 +883,7 @@ typedef union { @endcode
@note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
-#define MSR_CORE_MC3_ADDR 0x00000412
-
+#define MSR_CORE_MC3_ADDR 0x00000412
/**
Unique.
@@ -928,8 +901,7 @@ typedef union { @endcode
@note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
**/
-#define MSR_CORE_MC3_MISC 0x00000413
-
+#define MSR_CORE_MC3_MISC 0x00000413
/**
Unique.
@@ -947,8 +919,7 @@ typedef union { @endcode
@note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
**/
-#define MSR_CORE_MC5_CTL 0x00000414
-
+#define MSR_CORE_MC5_CTL 0x00000414
/**
Unique.
@@ -966,8 +937,7 @@ typedef union { @endcode
@note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
**/
-#define MSR_CORE_MC5_STATUS 0x00000415
-
+#define MSR_CORE_MC5_STATUS 0x00000415
/**
Unique.
@@ -985,8 +955,7 @@ typedef union { @endcode
@note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
**/
-#define MSR_CORE_MC5_ADDR 0x00000416
-
+#define MSR_CORE_MC5_ADDR 0x00000416
/**
Unique.
@@ -1004,8 +973,7 @@ typedef union { @endcode
@note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
**/
-#define MSR_CORE_MC5_MISC 0x00000417
-
+#define MSR_CORE_MC5_MISC 0x00000417
/**
Unique. See Table 2-2.
@@ -1025,7 +993,7 @@ typedef union { @endcode
@note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
**/
-#define MSR_CORE_IA32_EFER 0xC0000080
+#define MSR_CORE_IA32_EFER 0xC0000080
/**
MSR information returned for MSR index #MSR_CORE_IA32_EFER
@@ -1035,22 +1003,22 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:11;
+ UINT32 Reserved1 : 11;
///
/// [Bit 11] Execute Disable Bit Enable.
///
- UINT32 NXE:1;
- UINT32 Reserved2:20;
- UINT32 Reserved3:32;
+ UINT32 NXE : 1;
+ UINT32 Reserved2 : 20;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_CORE_IA32_EFER_REGISTER;
#endif
|