diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h | 1177 |
1 files changed, 443 insertions, 734 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h index 6c8e29d2ac..2bcc20d3f2 100644 --- a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h @@ -60,7 +60,7 @@ @endcode
@note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
**/
-#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
/**
MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
@@ -75,26 +75,25 @@ typedef union { /// currently enabled (by either factory configuration or BIOS
/// configuration) in the physical package.
///
- UINT32 Core_Count:16;
+ UINT32 Core_Count : 16;
///
/// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
/// are currently enabled (by either factory configuration or BIOS
/// configuration) in the physical package.
///
- UINT32 Thread_Count:16;
- UINT32 Reserved:32;
+ UINT32 Thread_Count : 16;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
-
/**
Thread. A Hardware Assigned ID for the Logical Processor (RO).
@@ -112,7 +111,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
**/
-#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
/**
MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
@@ -128,21 +127,20 @@ typedef union { /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
/// a physical package.
///
- UINT32 Logical_Processor_ID:8;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
+ UINT32 Logical_Processor_ID : 8;
+ UINT32 Reserved1 : 24;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
-
/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
@@ -163,7 +161,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
-#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
@@ -182,56 +180,55 @@ typedef union { /// 011b: C6 (retention) 111b: No Package C state limits. All C states
/// supported by the processor are available.
///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
+ UINT32 Limit : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
+ UINT32 IO_MWAIT : 1;
+ UINT32 Reserved2 : 4;
///
/// [Bit 15] CFG Lock (R/WO).
///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
+ UINT32 CFGLock : 1;
+ UINT32 Reserved3 : 9;
///
/// [Bit 25] C3 State Auto Demotion Enable (R/W).
///
- UINT32 C3AutoDemotion:1;
+ UINT32 C3AutoDemotion : 1;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W).
///
- UINT32 C1AutoDemotion:1;
+ UINT32 C1AutoDemotion : 1;
///
/// [Bit 27] Enable C3 Undemotion (R/W).
///
- UINT32 C3Undemotion:1;
+ UINT32 C3Undemotion : 1;
///
/// [Bit 28] Enable C1 Undemotion (R/W).
///
- UINT32 C1Undemotion:1;
+ UINT32 C1Undemotion : 1;
///
/// [Bit 29] Package C State Demotion Enable (R/W).
///
- UINT32 CStateDemotion:1;
+ UINT32 CStateDemotion : 1;
///
/// [Bit 30] Package C State UnDemotion Enable (R/W).
///
- UINT32 CStateUndemotion:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:32;
+ UINT32 CStateUndemotion : 1;
+ UINT32 Reserved4 : 1;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
-
/**
Thread. Global Machine Check Capability (R/O).
@@ -249,7 +246,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
**/
-#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
+#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
/**
MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
@@ -262,54 +259,53 @@ typedef union { ///
/// [Bits 7:0] Count.
///
- UINT32 Count:8;
+ UINT32 Count : 8;
///
/// [Bit 8] MCG_CTL_P.
///
- UINT32 MCG_CTL_P:1;
+ UINT32 MCG_CTL_P : 1;
///
/// [Bit 9] MCG_EXT_P.
///
- UINT32 MCG_EXT_P:1;
+ UINT32 MCG_EXT_P : 1;
///
/// [Bit 10] MCP_CMCI_P.
///
- UINT32 MCP_CMCI_P:1;
+ UINT32 MCP_CMCI_P : 1;
///
/// [Bit 11] MCG_TES_P.
///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
+ UINT32 MCG_TES_P : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 23:16] MCG_EXT_CNT.
///
- UINT32 MCG_EXT_CNT:8;
+ UINT32 MCG_EXT_CNT : 8;
///
/// [Bit 24] MCG_SER_P.
///
- UINT32 MCG_SER_P:1;
+ UINT32 MCG_SER_P : 1;
///
/// [Bit 25] MCG_EM_P.
///
- UINT32 MCG_EM_P:1;
+ UINT32 MCG_EM_P : 1;
///
/// [Bit 26] MCG_ELOG_P.
///
- UINT32 MCG_ELOG_P:1;
- UINT32 Reserved2:5;
- UINT32 Reserved3:32;
+ UINT32 MCG_ELOG_P : 1;
+ UINT32 Reserved2 : 5;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
-
/**
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
Enhancement. Accessible only while in SMM.
@@ -329,7 +325,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
**/
-#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
+#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
/**
MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
@@ -339,29 +335,28 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 26;
///
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
/// SMM code access restriction is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 SMM_Code_Access_Chk:1;
+ UINT32 SMM_Code_Access_Chk : 1;
///
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
/// SMM long flow indicator is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
+ UINT32 Long_Flow_Indication : 1;
+ UINT32 Reserved3 : 4;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
-
/**
Package. MC Bank Error Configuration (R/W).
@@ -380,7 +375,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
**/
-#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
+#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
/**
MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
@@ -390,26 +385,25 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
/// to log additional info in bits 36:32.
///
- UINT32 MemErrorLogEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
+ UINT32 MemErrorLogEnable : 1;
+ UINT32 Reserved2 : 30;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -428,7 +422,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
@@ -442,50 +436,49 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
- UINT32 Maximum1C:8;
+ UINT32 Maximum1C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
- UINT32 Maximum2C:8;
+ UINT32 Maximum2C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
- UINT32 Maximum3C:8;
+ UINT32 Maximum3C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
- UINT32 Maximum4C:8;
+ UINT32 Maximum4C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
- UINT32 Maximum5C:8;
+ UINT32 Maximum5C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
- UINT32 Maximum6C:8;
+ UINT32 Maximum6C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
/// limit of 7 core active.
///
- UINT32 Maximum7C:8;
+ UINT32 Maximum7C : 8;
///
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
/// limit of 8 core active.
///
- UINT32 Maximum8C:8;
+ UINT32 Maximum8C : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -504,7 +497,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
/**
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
@@ -518,50 +511,49 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
/// limit of 9 core active.
///
- UINT32 Maximum9C:8;
+ UINT32 Maximum9C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
/// limit of 10 core active.
///
- UINT32 Maximum10C:8;
+ UINT32 Maximum10C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
/// limit of 11 core active.
///
- UINT32 Maximum11C:8;
+ UINT32 Maximum11C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
/// limit of 12 core active.
///
- UINT32 Maximum12C:8;
+ UINT32 Maximum12C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
/// limit of 13 core active.
///
- UINT32 Maximum13C:8;
+ UINT32 Maximum13C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
/// limit of 14 core active.
///
- UINT32 Maximum14C:8;
+ UINT32 Maximum14C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
/// limit of 15 core active.
///
- UINT32 Maximum15C:8;
+ UINT32 Maximum15C : 8;
///
/// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
/// limit of 16 core active.
///
- UINT32 Maximum16C:8;
+ UINT32 Maximum16C : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -580,7 +572,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
**/
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
/**
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
@@ -594,14 +586,14 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
/// limit of 17 core active.
///
- UINT32 Maximum17C:8;
+ UINT32 Maximum17C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
/// limit of 18 core active.
///
- UINT32 Maximum18C:8;
- UINT32 Reserved1:16;
- UINT32 Reserved2:31;
+ UINT32 Maximum18C : 8;
+ UINT32 Reserved1 : 16;
+ UINT32 Reserved2 : 31;
///
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
/// the processor uses override configuration specified in
@@ -609,15 +601,14 @@ typedef union { /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
/// configuration (Default).
///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
-
/**
Package. Unit Multipliers used in RAPL Interfaces (R/O).
@@ -635,7 +626,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
**/
-#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
+#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
/**
MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
@@ -648,35 +639,34 @@ typedef union { ///
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
+ UINT32 PowerUnits : 4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 12:8] Package. Energy Status Units Energy related information
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
/// micro-joules).
///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
+ UINT32 EnergyStatusUnits : 5;
+ UINT32 Reserved2 : 3;
///
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
/// Interfaces.".
///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
+ UINT32 TimeUnits : 4;
+ UINT32 Reserved3 : 12;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
-
/**
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
Domain.".
@@ -694,8 +684,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
**/
-#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
-
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
/**
Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
@@ -714,7 +703,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
-#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
/**
MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
@@ -728,20 +717,19 @@ typedef union { /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
/// to enable DRAM RAPL mode 0 (Direct VR).
///
- UINT32 Energy:32;
- UINT32 Reserved:32;
+ UINT32 Energy : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
-
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
RAPL Domain.".
@@ -758,8 +746,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
**/
-#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
-
+#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
/**
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -777,8 +764,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
**/
-#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
-
+#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
/**
Package. Configuration of PCIE PLL Relative to BCLK(R/W).
@@ -798,7 +784,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
**/
-#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
/**
MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
@@ -814,31 +800,30 @@ typedef union { /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
/// operation.
///
- UINT32 PCIERatio:2;
+ UINT32 PCIERatio : 2;
///
/// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
/// PCIE Ratio.
///
- UINT32 LPLLSelect:1;
+ UINT32 LPLLSelect : 1;
///
/// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
/// before re-locking Gen2/Gen3 PLLs.
///
- UINT32 LONGRESET:1;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 LONGRESET : 1;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
-
/**
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
fields represent the widest possible range of uncore frequencies. Writing to
@@ -859,7 +844,7 @@ typedef union { AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
-#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
@@ -873,24 +858,24 @@ typedef union { /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
- UINT32 MAX_RATIO:7;
- UINT32 Reserved1:1;
+ UINT32 MAX_RATIO : 7;
+ UINT32 Reserved1 : 1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
- UINT32 MIN_RATIO:7;
- UINT32 Reserved2:17;
- UINT32 Reserved3:32;
+ UINT32 MIN_RATIO : 7;
+ UINT32 Reserved2 : 17;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
/**
@@ -908,8 +893,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
-#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
-
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
/**
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
@@ -930,7 +914,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
**/
-#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
/**
MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
@@ -945,152 +929,151 @@ typedef union { /// reduced below the operating system request due to assertion of
/// external PROCHOT.
///
- UINT32 PROCHOT_Status:1;
+ UINT32 PROCHOT_Status : 1;
///
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
/// operating system request due to a thermal event.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 2] Power Budget Management Status (R0) When set, frequency is
/// reduced below the operating system request due to PBM limit.
///
- UINT32 PowerBudgetManagementStatus:1;
+ UINT32 PowerBudgetManagementStatus : 1;
///
/// [Bit 3] Platform Configuration Services Status (R0) When set,
/// frequency is reduced below the operating system request due to PCS
/// limit.
///
- UINT32 PlatformConfigurationServicesStatus:1;
- UINT32 Reserved1:1;
+ UINT32 PlatformConfigurationServicesStatus : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
/// When set, frequency is reduced below the operating system request
/// because the processor has detected that utilization is low.
///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;
///
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
/// below the operating system request due to a thermal alert from the
/// Voltage Regulator.
///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
+ UINT32 VRThermAlertStatus : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
/// reduced below the operating system request due to electrical design
/// point constraints (e.g. maximum electrical current consumption).
///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:1;
+ UINT32 ElectricalDesignPointStatus : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
/// below the operating system request due to Multi-Core Turbo limits.
///
- UINT32 MultiCoreTurboStatus:1;
- UINT32 Reserved4:2;
+ UINT32 MultiCoreTurboStatus : 1;
+ UINT32 Reserved4 : 2;
///
/// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
/// below max non-turbo P1.
///
- UINT32 FrequencyP1Status:1;
+ UINT32 FrequencyP1Status : 1;
///
/// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
/// set, frequency is reduced below max n-core turbo frequency.
///
- UINT32 TurboFrequencyLimitingStatus:1;
+ UINT32 TurboFrequencyLimitingStatus : 1;
///
/// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
/// reduced below the operating system request.
///
- UINT32 FrequencyLimitingStatus:1;
+ UINT32 FrequencyLimitingStatus : 1;
///
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 PROCHOT_Log:1;
+ UINT32 PROCHOT_Log : 1;
///
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 ThermalLog:1;
+ UINT32 ThermalLog : 1;
///
/// [Bit 18] Power Budget Management Log When set, indicates that the PBM
/// Status bit has asserted since the log bit was last cleared. This log
/// bit will remain set until cleared by software writing 0.
///
- UINT32 PowerBudgetManagementLog:1;
+ UINT32 PowerBudgetManagementLog : 1;
///
/// [Bit 19] Platform Configuration Services Log When set, indicates that
/// the PCS Status bit has asserted since the log bit was last cleared.
/// This log bit will remain set until cleared by software writing 0.
///
- UINT32 PlatformConfigurationServicesLog:1;
- UINT32 Reserved5:1;
+ UINT32 PlatformConfigurationServicesLog : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
/// indicates that the AUBFC Status bit has asserted since the log bit was
/// last cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;
///
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
/// Alert Status bit has asserted since the log bit was last cleared. This
/// log bit will remain set until cleared by software writing 0.
///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved6:1;
+ UINT32 VRThermAlertLog : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
/// Status bit has asserted since the log bit was last cleared. This log
/// bit will remain set until cleared by software writing 0.
///
- UINT32 ElectricalDesignPointLog:1;
- UINT32 Reserved7:1;
+ UINT32 ElectricalDesignPointLog : 1;
+ UINT32 Reserved7 : 1;
///
/// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
/// Turbo Status bit has asserted since the log bit was last cleared. This
/// log bit will remain set until cleared by software writing 0.
///
- UINT32 MultiCoreTurboLog:1;
- UINT32 Reserved8:2;
+ UINT32 MultiCoreTurboLog : 1;
+ UINT32 Reserved8 : 2;
///
/// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
/// Frequency P1 Status bit has asserted since the log bit was last
/// cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 CoreFrequencyP1Log:1;
+ UINT32 CoreFrequencyP1Log : 1;
///
/// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
/// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 TurboFrequencyLimitingLog:1;
+ UINT32 TurboFrequencyLimitingLog : 1;
///
/// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
/// Frequency Limiting Status bit has asserted since the log bit was last
/// cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 CoreFrequencyLimitingLog:1;
- UINT32 Reserved9:32;
+ UINT32 CoreFrequencyLimitingLog : 1;
+ UINT32 Reserved9 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
-
/**
THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
ECX=0):EBX.RDT-M[bit 12] = 1.
@@ -1110,7 +1093,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
**/
-#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
+#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
/**
MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
@@ -1124,21 +1107,20 @@ typedef union { /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
/// occupancy monitoring all other encoding reserved..
///
- UINT32 EventID:8;
- UINT32 Reserved1:24;
+ UINT32 EventID : 8;
+ UINT32 Reserved1 : 24;
///
/// [Bits 41:32] RMID (RW).
///
- UINT32 RMID:10;
- UINT32 Reserved2:22;
+ UINT32 RMID : 10;
+ UINT32 Reserved2 : 22;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
-
/**
THREAD. Resource Association Register (R/W)..
@@ -1157,7 +1139,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
**/
-#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
+#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
/**
MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
@@ -1170,21 +1152,20 @@ typedef union { ///
/// [Bits 9:0] RMID.
///
- UINT32 RMID:10;
- UINT32 Reserved1:22;
- UINT32 Reserved2:32;
+ UINT32 RMID : 10;
+ UINT32 Reserved1 : 22;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
-
/**
Package. Uncore perfmon per-socket global control.
@@ -1201,8 +1182,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
**/
-#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
-
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
/**
Package. Uncore perfmon per-socket global status.
@@ -1220,8 +1200,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
**/
-#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
-
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
/**
Package. Uncore perfmon per-socket global configuration.
@@ -1239,8 +1218,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
**/
-#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
-
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
/**
Package. Uncore U-box UCLK fixed counter control.
@@ -1258,8 +1236,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
-
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
/**
Package. Uncore U-box UCLK fixed counter.
@@ -1277,8 +1254,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
-
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
/**
Package. Uncore U-box perfmon event select for U-box counter 0.
@@ -1296,8 +1272,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
-
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
/**
Package. Uncore U-box perfmon event select for U-box counter 1.
@@ -1315,8 +1290,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
-
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
/**
Package. Uncore U-box perfmon U-box wide status.
@@ -1334,8 +1308,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
-
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
/**
Package. Uncore U-box perfmon counter 0.
@@ -1353,8 +1326,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
-
+#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
/**
Package. Uncore U-box perfmon counter 1.
@@ -1372,8 +1344,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
-
+#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
/**
Package. Uncore PCU perfmon for PCU-box-wide control.
@@ -1391,8 +1362,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
-
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
/**
Package. Uncore PCU perfmon event select for PCU counter 0.
@@ -1410,8 +1380,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
-
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
/**
Package. Uncore PCU perfmon event select for PCU counter 1.
@@ -1429,8 +1398,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
-
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
/**
Package. Uncore PCU perfmon event select for PCU counter 2.
@@ -1448,8 +1416,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
-
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
/**
Package. Uncore PCU perfmon event select for PCU counter 3.
@@ -1467,8 +1434,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
-
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
/**
Package. Uncore PCU perfmon box-wide filter.
@@ -1486,8 +1452,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
-
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
/**
Package. Uncore PCU perfmon box wide status.
@@ -1505,8 +1470,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
-
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
/**
Package. Uncore PCU perfmon counter 0.
@@ -1524,8 +1488,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
-
+#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
/**
Package. Uncore PCU perfmon counter 1.
@@ -1543,8 +1506,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
-
+#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
/**
Package. Uncore PCU perfmon counter 2.
@@ -1562,8 +1524,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
-
+#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
/**
Package. Uncore PCU perfmon counter 3.
@@ -1581,8 +1542,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
-
+#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
/**
Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
@@ -1600,8 +1560,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
-
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
/**
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
@@ -1619,8 +1578,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
-
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
/**
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
@@ -1638,8 +1596,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
-
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
/**
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
@@ -1657,8 +1614,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
-
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
/**
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
@@ -1676,8 +1632,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
-
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
/**
Package. Uncore SBo 0 perfmon box-wide filter.
@@ -1695,8 +1650,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
-
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
/**
Package. Uncore SBo 0 perfmon counter 0.
@@ -1714,8 +1668,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
-
+#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
/**
Package. Uncore SBo 0 perfmon counter 1.
@@ -1733,8 +1686,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
-
+#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
/**
Package. Uncore SBo 0 perfmon counter 2.
@@ -1752,8 +1704,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
-
+#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
/**
Package. Uncore SBo 0 perfmon counter 3.
@@ -1771,8 +1722,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
-
+#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
/**
Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
@@ -1790,8 +1740,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
-
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
/**
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
@@ -1809,8 +1758,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
-
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
/**
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
@@ -1828,8 +1776,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
-
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
/**
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
@@ -1847,8 +1794,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
-
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
/**
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
@@ -1866,8 +1812,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
-
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
/**
Package. Uncore SBo 1 perfmon box-wide filter.
@@ -1885,8 +1830,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
-
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
/**
Package. Uncore SBo 1 perfmon counter 0.
@@ -1904,8 +1848,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
-
+#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
/**
Package. Uncore SBo 1 perfmon counter 1.
@@ -1923,8 +1866,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
-
+#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
/**
Package. Uncore SBo 1 perfmon counter 2.
@@ -1942,8 +1884,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
-
+#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
/**
Package. Uncore SBo 1 perfmon counter 3.
@@ -1961,8 +1902,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
-
+#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
/**
Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
@@ -1980,8 +1920,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
-
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
/**
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
@@ -1999,8 +1938,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
-
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
/**
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
@@ -2018,8 +1956,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
-
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
/**
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
@@ -2037,8 +1974,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
-
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
/**
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
@@ -2056,8 +1992,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
-
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
/**
Package. Uncore SBo 2 perfmon box-wide filter.
@@ -2075,8 +2010,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
-
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
/**
Package. Uncore SBo 2 perfmon counter 0.
@@ -2094,8 +2028,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
-
+#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
/**
Package. Uncore SBo 2 perfmon counter 1.
@@ -2113,8 +2046,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
-
+#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
/**
Package. Uncore SBo 2 perfmon counter 2.
@@ -2132,8 +2064,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
-
+#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
/**
Package. Uncore SBo 2 perfmon counter 3.
@@ -2151,8 +2082,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
-
+#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
/**
Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
@@ -2170,8 +2100,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
-
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
/**
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
@@ -2189,8 +2118,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
-
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
/**
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
@@ -2208,8 +2136,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
-
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
/**
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
@@ -2227,8 +2154,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
-
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
/**
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
@@ -2246,8 +2172,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
-
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
/**
Package. Uncore SBo 3 perfmon box-wide filter.
@@ -2265,8 +2190,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
-
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
/**
Package. Uncore SBo 3 perfmon counter 0.
@@ -2284,8 +2208,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
-
+#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
/**
Package. Uncore SBo 3 perfmon counter 1.
@@ -2303,8 +2226,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
-
+#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
/**
Package. Uncore SBo 3 perfmon counter 2.
@@ -2322,8 +2244,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
-
+#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
/**
Package. Uncore SBo 3 perfmon counter 3.
@@ -2341,8 +2262,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
-
+#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
/**
Package. Uncore C-box 0 perfmon for box-wide control.
@@ -2360,8 +2280,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
-
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
/**
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
@@ -2379,8 +2298,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
-
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
/**
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
@@ -2398,8 +2316,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
-
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
/**
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
@@ -2417,8 +2334,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
-
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
/**
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
@@ -2436,8 +2352,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
-
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
/**
Package. Uncore C-box 0 perfmon box wide filter 0.
@@ -2455,8 +2370,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
-
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
/**
Package. Uncore C-box 0 perfmon box wide filter 1.
@@ -2474,8 +2388,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
-
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
/**
Package. Uncore C-box 0 perfmon box wide status.
@@ -2493,8 +2406,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
-
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
/**
Package. Uncore C-box 0 perfmon counter 0.
@@ -2512,8 +2424,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
-
+#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
/**
Package. Uncore C-box 0 perfmon counter 1.
@@ -2531,8 +2442,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
-
+#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
/**
Package. Uncore C-box 0 perfmon counter 2.
@@ -2550,8 +2460,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
-
+#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
/**
Package. Uncore C-box 0 perfmon counter 3.
@@ -2569,8 +2478,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
-
+#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
/**
Package. Uncore C-box 1 perfmon for box-wide control.
@@ -2588,8 +2496,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
-
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
/**
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
@@ -2607,8 +2514,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
-
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
/**
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
@@ -2626,8 +2532,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
-
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
/**
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
@@ -2645,8 +2550,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
-
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
/**
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
@@ -2664,8 +2568,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
-
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
/**
Package. Uncore C-box 1 perfmon box wide filter 0.
@@ -2683,8 +2586,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
-
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
/**
Package. Uncore C-box 1 perfmon box wide filter1.
@@ -2702,8 +2604,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
-
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
/**
Package. Uncore C-box 1 perfmon box wide status.
@@ -2721,8 +2622,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
-
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
/**
Package. Uncore C-box 1 perfmon counter 0.
@@ -2740,8 +2640,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
-
+#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
/**
Package. Uncore C-box 1 perfmon counter 1.
@@ -2759,8 +2658,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
-
+#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
/**
Package. Uncore C-box 1 perfmon counter 2.
@@ -2778,8 +2676,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
-
+#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
/**
Package. Uncore C-box 1 perfmon counter 3.
@@ -2797,8 +2694,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
-
+#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
/**
Package. Uncore C-box 2 perfmon for box-wide control.
@@ -2816,8 +2712,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
-
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
/**
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
@@ -2835,8 +2730,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
-
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
/**
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
@@ -2854,8 +2748,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
-
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
/**
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
@@ -2873,8 +2766,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
-
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
/**
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
@@ -2892,8 +2784,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
-
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
/**
Package. Uncore C-box 2 perfmon box wide filter 0.
@@ -2911,8 +2802,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
-
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
/**
Package. Uncore C-box 2 perfmon box wide filter1.
@@ -2930,8 +2820,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
-
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
/**
Package. Uncore C-box 2 perfmon box wide status.
@@ -2949,8 +2838,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
-
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
/**
Package. Uncore C-box 2 perfmon counter 0.
@@ -2968,8 +2856,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
-
+#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
/**
Package. Uncore C-box 2 perfmon counter 1.
@@ -2987,8 +2874,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
-
+#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
/**
Package. Uncore C-box 2 perfmon counter 2.
@@ -3006,8 +2892,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
-
+#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
/**
Package. Uncore C-box 2 perfmon counter 3.
@@ -3025,8 +2910,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
-
+#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
/**
Package. Uncore C-box 3 perfmon for box-wide control.
@@ -3044,8 +2928,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
-
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
/**
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
@@ -3063,8 +2946,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
-
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
/**
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
@@ -3082,8 +2964,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
-
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
/**
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
@@ -3101,8 +2982,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
-
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
/**
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
@@ -3120,8 +3000,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
-
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
/**
Package. Uncore C-box 3 perfmon box wide filter 0.
@@ -3139,8 +3018,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
-
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
/**
Package. Uncore C-box 3 perfmon box wide filter1.
@@ -3158,8 +3036,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
-
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
/**
Package. Uncore C-box 3 perfmon box wide status.
@@ -3177,8 +3054,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
-
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
/**
Package. Uncore C-box 3 perfmon counter 0.
@@ -3196,8 +3072,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
-
+#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
/**
Package. Uncore C-box 3 perfmon counter 1.
@@ -3215,8 +3090,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
-
+#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
/**
Package. Uncore C-box 3 perfmon counter 2.
@@ -3234,8 +3108,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
-
+#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
/**
Package. Uncore C-box 3 perfmon counter 3.
@@ -3253,8 +3126,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
-
+#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
/**
Package. Uncore C-box 4 perfmon for box-wide control.
@@ -3272,8 +3144,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
-
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
/**
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
@@ -3291,8 +3162,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
-
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
/**
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
@@ -3310,8 +3180,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
-
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
/**
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
@@ -3329,8 +3198,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
-
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
/**
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
@@ -3348,8 +3216,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
-
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
/**
Package. Uncore C-box 4 perfmon box wide filter 0.
@@ -3367,8 +3234,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
-
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
/**
Package. Uncore C-box 4 perfmon box wide filter1.
@@ -3386,8 +3252,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
-
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
/**
Package. Uncore C-box 4 perfmon box wide status.
@@ -3405,8 +3270,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
-
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
/**
Package. Uncore C-box 4 perfmon counter 0.
@@ -3424,8 +3288,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
-
+#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
/**
Package. Uncore C-box 4 perfmon counter 1.
@@ -3443,8 +3306,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
-
+#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
/**
Package. Uncore C-box 4 perfmon counter 2.
@@ -3462,8 +3324,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
-
+#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
/**
Package. Uncore C-box 4 perfmon counter 3.
@@ -3481,8 +3342,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
-
+#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
/**
Package. Uncore C-box 5 perfmon for box-wide control.
@@ -3500,8 +3360,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
-
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
/**
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
@@ -3519,8 +3378,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
-
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
/**
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
@@ -3538,8 +3396,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
-
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
/**
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
@@ -3557,8 +3414,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
-
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
/**
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
@@ -3576,8 +3432,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
-
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
/**
Package. Uncore C-box 5 perfmon box wide filter 0.
@@ -3595,8 +3450,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
-
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
/**
Package. Uncore C-box 5 perfmon box wide filter1.
@@ -3614,8 +3468,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
-
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
/**
Package. Uncore C-box 5 perfmon box wide status.
@@ -3633,8 +3486,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
-
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
/**
Package. Uncore C-box 5 perfmon counter 0.
@@ -3652,8 +3504,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
-
+#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
/**
Package. Uncore C-box 5 perfmon counter 1.
@@ -3671,8 +3522,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
-
+#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
/**
Package. Uncore C-box 5 perfmon counter 2.
@@ -3690,8 +3540,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
-
+#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
/**
Package. Uncore C-box 5 perfmon counter 3.
@@ -3709,8 +3558,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
-
+#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
/**
Package. Uncore C-box 6 perfmon for box-wide control.
@@ -3728,8 +3576,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
-
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
/**
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
@@ -3747,8 +3594,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
-
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
/**
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
@@ -3766,8 +3612,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
-
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
/**
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
@@ -3785,8 +3630,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
-
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
/**
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
@@ -3804,8 +3648,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
-
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
/**
Package. Uncore C-box 6 perfmon box wide filter 0.
@@ -3823,8 +3666,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
-
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
/**
Package. Uncore C-box 6 perfmon box wide filter1.
@@ -3842,8 +3684,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
-
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
/**
Package. Uncore C-box 6 perfmon box wide status.
@@ -3861,8 +3702,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
-
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
/**
Package. Uncore C-box 6 perfmon counter 0.
@@ -3880,8 +3720,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
-
+#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
/**
Package. Uncore C-box 6 perfmon counter 1.
@@ -3899,8 +3738,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
-
+#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
/**
Package. Uncore C-box 6 perfmon counter 2.
@@ -3918,8 +3756,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
-
+#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
/**
Package. Uncore C-box 6 perfmon counter 3.
@@ -3937,8 +3774,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
-
+#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
/**
Package. Uncore C-box 7 perfmon for box-wide control.
@@ -3956,8 +3792,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
-
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
/**
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
@@ -3975,8 +3810,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
-
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
/**
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
@@ -3994,8 +3828,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
-
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
/**
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
@@ -4013,8 +3846,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
-
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
/**
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
@@ -4032,8 +3864,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
-
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
/**
Package. Uncore C-box 7 perfmon box wide filter 0.
@@ -4051,8 +3882,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
-
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
/**
Package. Uncore C-box 7 perfmon box wide filter1.
@@ -4070,8 +3900,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
-
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
/**
Package. Uncore C-box 7 perfmon box wide status.
@@ -4089,8 +3918,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
-
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
/**
Package. Uncore C-box 7 perfmon counter 0.
@@ -4108,8 +3936,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
-
+#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
/**
Package. Uncore C-box 7 perfmon counter 1.
@@ -4127,8 +3954,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
-
+#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
/**
Package. Uncore C-box 7 perfmon counter 2.
@@ -4146,8 +3972,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
-
+#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
/**
Package. Uncore C-box 7 perfmon counter 3.
@@ -4165,8 +3990,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
-
+#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
/**
Package. Uncore C-box 8 perfmon local box wide control.
@@ -4184,8 +4008,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
-
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
@@ -4203,8 +4026,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
-
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
@@ -4222,8 +4044,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
-
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
@@ -4241,8 +4062,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
-
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
@@ -4260,8 +4080,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
-
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
/**
Package. Uncore C-box 8 perfmon box wide filter0.
@@ -4279,8 +4098,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
-
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
/**
Package. Uncore C-box 8 perfmon box wide filter1.
@@ -4298,8 +4116,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
-
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
/**
Package. Uncore C-box 8 perfmon box wide status.
@@ -4317,8 +4134,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
-
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
/**
Package. Uncore C-box 8 perfmon counter 0.
@@ -4336,8 +4152,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
-
+#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
/**
Package. Uncore C-box 8 perfmon counter 1.
@@ -4355,8 +4170,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
-
+#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
/**
Package. Uncore C-box 8 perfmon counter 2.
@@ -4374,8 +4188,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
-
+#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
/**
Package. Uncore C-box 8 perfmon counter 3.
@@ -4393,8 +4206,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
-
+#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
/**
Package. Uncore C-box 9 perfmon local box wide control.
@@ -4412,8 +4224,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
-
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
@@ -4431,8 +4242,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
-
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
@@ -4450,8 +4260,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
-
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
@@ -4469,8 +4278,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
-
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
@@ -4488,8 +4296,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
-
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
/**
Package. Uncore C-box 9 perfmon box wide filter0.
@@ -4507,8 +4314,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
-
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
/**
Package. Uncore C-box 9 perfmon box wide filter1.
@@ -4526,8 +4332,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
-
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
/**
Package. Uncore C-box 9 perfmon box wide status.
@@ -4545,8 +4350,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
-
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
/**
Package. Uncore C-box 9 perfmon counter 0.
@@ -4564,8 +4368,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
-
+#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
/**
Package. Uncore C-box 9 perfmon counter 1.
@@ -4583,8 +4386,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
-
+#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
/**
Package. Uncore C-box 9 perfmon counter 2.
@@ -4602,8 +4404,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
-
+#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
/**
Package. Uncore C-box 9 perfmon counter 3.
@@ -4621,8 +4422,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
-
+#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
/**
Package. Uncore C-box 10 perfmon local box wide control.
@@ -4640,8 +4440,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
-
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
@@ -4659,8 +4458,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
-
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
@@ -4678,8 +4476,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
-
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
@@ -4697,8 +4494,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
-
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
@@ -4716,8 +4512,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
-
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
/**
Package. Uncore C-box 10 perfmon box wide filter0.
@@ -4735,8 +4530,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
-
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
/**
Package. Uncore C-box 10 perfmon box wide filter1.
@@ -4754,8 +4548,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
-
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
/**
Package. Uncore C-box 10 perfmon box wide status.
@@ -4773,8 +4566,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
-
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
/**
Package. Uncore C-box 10 perfmon counter 0.
@@ -4792,8 +4584,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
-
+#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
/**
Package. Uncore C-box 10 perfmon counter 1.
@@ -4811,8 +4602,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
-
+#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
/**
Package. Uncore C-box 10 perfmon counter 2.
@@ -4830,8 +4620,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
-
+#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
/**
Package. Uncore C-box 10 perfmon counter 3.
@@ -4849,8 +4638,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
-
+#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
/**
Package. Uncore C-box 11 perfmon local box wide control.
@@ -4868,8 +4656,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
-
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
@@ -4887,8 +4674,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
-
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
@@ -4906,8 +4692,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
-
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
@@ -4925,8 +4710,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
-
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
@@ -4944,8 +4728,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
-
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
/**
Package. Uncore C-box 11 perfmon box wide filter0.
@@ -4963,8 +4746,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
-
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
/**
Package. Uncore C-box 11 perfmon box wide filter1.
@@ -4982,8 +4764,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
-
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
/**
Package. Uncore C-box 11 perfmon box wide status.
@@ -5001,8 +4782,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
-
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
/**
Package. Uncore C-box 11 perfmon counter 0.
@@ -5020,8 +4800,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
-
+#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
/**
Package. Uncore C-box 11 perfmon counter 1.
@@ -5039,8 +4818,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
-
+#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
/**
Package. Uncore C-box 11 perfmon counter 2.
@@ -5058,8 +4836,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
-
+#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
/**
Package. Uncore C-box 11 perfmon counter 3.
@@ -5077,8 +4854,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
-
+#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
/**
Package. Uncore C-box 12 perfmon local box wide control.
@@ -5096,8 +4872,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
-
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
@@ -5115,8 +4890,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
-
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
@@ -5134,8 +4908,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
-
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
@@ -5153,8 +4926,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
-
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
@@ -5172,8 +4944,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
-
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
/**
Package. Uncore C-box 12 perfmon box wide filter0.
@@ -5191,8 +4962,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
-
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
/**
Package. Uncore C-box 12 perfmon box wide filter1.
@@ -5210,8 +4980,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
-
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
/**
Package. Uncore C-box 12 perfmon box wide status.
@@ -5229,8 +4998,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
-
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
/**
Package. Uncore C-box 12 perfmon counter 0.
@@ -5248,8 +5016,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
-
+#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
/**
Package. Uncore C-box 12 perfmon counter 1.
@@ -5267,8 +5034,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
-
+#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
/**
Package. Uncore C-box 12 perfmon counter 2.
@@ -5286,8 +5052,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
-
+#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
/**
Package. Uncore C-box 12 perfmon counter 3.
@@ -5305,8 +5070,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
-
+#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
/**
Package. Uncore C-box 13 perfmon local box wide control.
@@ -5324,8 +5088,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
-
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
@@ -5343,8 +5106,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
-
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
@@ -5362,8 +5124,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
-
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
@@ -5381,8 +5142,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
-
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
@@ -5400,8 +5160,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
-
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
/**
Package. Uncore C-box 13 perfmon box wide filter0.
@@ -5419,8 +5178,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
-
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
/**
Package. Uncore C-box 13 perfmon box wide filter1.
@@ -5438,8 +5196,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
-
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
/**
Package. Uncore C-box 13 perfmon box wide status.
@@ -5457,8 +5214,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
-
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
/**
Package. Uncore C-box 13 perfmon counter 0.
@@ -5476,8 +5232,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
-
+#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
/**
Package. Uncore C-box 13 perfmon counter 1.
@@ -5495,8 +5250,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
-
+#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
/**
Package. Uncore C-box 13 perfmon counter 2.
@@ -5514,8 +5268,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
-
+#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
/**
Package. Uncore C-box 13 perfmon counter 3.
@@ -5533,8 +5286,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
-
+#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
/**
Package. Uncore C-box 14 perfmon local box wide control.
@@ -5552,8 +5304,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
-
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
@@ -5571,8 +5322,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
-
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
@@ -5590,8 +5340,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
-
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
@@ -5609,8 +5358,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
-
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
@@ -5628,8 +5376,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
-
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
/**
Package. Uncore C-box 14 perfmon box wide filter0.
@@ -5647,8 +5394,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
-
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
/**
Package. Uncore C-box 14 perfmon box wide filter1.
@@ -5666,8 +5412,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
-
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
/**
Package. Uncore C-box 14 perfmon box wide status.
@@ -5685,8 +5430,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
-
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
/**
Package. Uncore C-box 14 perfmon counter 0.
@@ -5704,8 +5448,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
-
+#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
/**
Package. Uncore C-box 14 perfmon counter 1.
@@ -5723,8 +5466,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
-
+#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
/**
Package. Uncore C-box 14 perfmon counter 2.
@@ -5742,8 +5484,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
-
+#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
/**
Package. Uncore C-box 14 perfmon counter 3.
@@ -5761,8 +5502,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
-
+#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
/**
Package. Uncore C-box 15 perfmon local box wide control.
@@ -5780,8 +5520,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
-
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
/**
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
@@ -5799,8 +5538,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
-
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
/**
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
@@ -5818,8 +5556,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
-
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
/**
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
@@ -5837,8 +5574,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
-
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
/**
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
@@ -5856,8 +5592,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
-
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
/**
Package. Uncore C-box 15 perfmon box wide filter0.
@@ -5875,8 +5610,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
-
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
/**
Package. Uncore C-box 15 perfmon box wide filter1.
@@ -5894,8 +5628,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
-
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
/**
Package. Uncore C-box 15 perfmon box wide status.
@@ -5913,8 +5646,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
-
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
/**
Package. Uncore C-box 15 perfmon counter 0.
@@ -5932,8 +5664,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
-
+#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
/**
Package. Uncore C-box 15 perfmon counter 1.
@@ -5951,8 +5682,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
-
+#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
/**
Package. Uncore C-box 15 perfmon counter 2.
@@ -5970,8 +5700,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
-
+#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
/**
Package. Uncore C-box 15 perfmon counter 3.
@@ -5989,8 +5718,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
-
+#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
/**
Package. Uncore C-box 16 perfmon for box-wide control.
@@ -6008,8 +5736,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
-
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
/**
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
@@ -6027,8 +5754,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
-
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
/**
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
@@ -6046,8 +5772,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
-
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
/**
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
@@ -6065,8 +5790,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
-
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
/**
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
@@ -6084,8 +5808,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
-
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
/**
Package. Uncore C-box 16 perfmon box wide filter 0.
@@ -6103,8 +5826,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
-
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
/**
Package. Uncore C-box 16 perfmon box wide filter 1.
@@ -6122,8 +5844,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
-
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
/**
Package. Uncore C-box 16 perfmon box wide status.
@@ -6141,8 +5862,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
-
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
/**
Package. Uncore C-box 16 perfmon counter 0.
@@ -6160,8 +5880,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
-
+#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
/**
Package. Uncore C-box 16 perfmon counter 1.
@@ -6179,8 +5898,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
-
+#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
/**
Package. Uncore C-box 16 perfmon counter 2.
@@ -6198,8 +5916,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
-
+#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
/**
Package. Uncore C-box 16 perfmon counter 3.
@@ -6217,8 +5934,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
**/
-#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
-
+#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
/**
Package. Uncore C-box 17 perfmon for box-wide control.
@@ -6236,8 +5952,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
-
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
/**
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
@@ -6255,8 +5970,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
-
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
/**
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
@@ -6274,8 +5988,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
-
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
/**
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
@@ -6293,8 +6006,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
-
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
/**
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
@@ -6312,8 +6024,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
-
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
/**
Package. Uncore C-box 17 perfmon box wide filter 0.
@@ -6331,8 +6042,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
-
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
/**
Package. Uncore C-box 17 perfmon box wide filter1.
@@ -6350,7 +6060,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
/**
Package. Uncore C-box 17 perfmon box wide status.
@@ -6368,8 +6078,7 @@ typedef union { @endcode
@note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
**/
-#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
-
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
/**
Package. Uncore C-box 17 perfmon counter n.
@@ -6391,10 +6100,10 @@ typedef union { MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
@{
**/
-#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
-#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
-#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
-#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B
+#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
+#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
+#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
+#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B
/// @}
#endif
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