diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h | 604 |
1 files changed, 245 insertions, 359 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h index bc8559d519..00779d4e59 100644 --- a/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h @@ -55,7 +55,7 @@ @endcode
@note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
**/
-#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
@@ -65,62 +65,61 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
/// MHz.
///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
+ UINT32 MaximumNonTurboRatio : 8;
+ UINT32 Reserved2 : 12;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
/// enabled, and when set to 0, indicates Programmable Ratio Limits for
/// Turbo mode is disabled.
///
- UINT32 RatioLimit:1;
+ UINT32 RatioLimit : 1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
/// and when set to 0, indicates TDP Limit for Turbo mode is not
/// programmable.
///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
+ UINT32 TDPLimit : 1;
+ UINT32 Reserved3 : 2;
///
/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
/// indicates that LPM is supported, and when set to 0, indicates LPM is
/// not supported.
///
- UINT32 LowPowerModeSupport:1;
+ UINT32 LowPowerModeSupport : 1;
///
/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
/// TDP level available. 01: One additional TDP level available. 02: Two
/// additional TDP level available. 11: Reserved.
///
- UINT32 ConfigTDPLevels:2;
- UINT32 Reserved4:5;
+ UINT32 ConfigTDPLevels : 2;
+ UINT32 Reserved4 : 5;
///
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
/// minimum ratio (maximum efficiency) that the processor can operates, in
/// units of 100MHz.
///
- UINT32 MaximumEfficiencyRatio:8;
+ UINT32 MaximumEfficiencyRatio : 8;
///
/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
/// minimum supported operating ratio in units of 100 MHz.
///
- UINT32 MinimumOperatingRatio:8;
- UINT32 Reserved5:8;
+ UINT32 MinimumOperatingRatio : 8;
+ UINT32 Reserved5 : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
-
/**
Core. C-State Configuration Control (R/W) Note: C-state values are
processor specific C-state code names, unrelated to MWAIT extension C-state
@@ -141,7 +140,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
-#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
@@ -160,57 +159,56 @@ typedef union { /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
/// This field cannot be used to limit package C-state to C3.
///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
+ UINT32 Limit : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
/// IO_read instructions sent to IO register specified by
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
+ UINT32 IO_MWAIT : 1;
+ UINT32 Reserved2 : 4;
///
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
/// until next reset.
///
- UINT32 CFGLock:1;
- UINT32 Reserved3:9;
+ UINT32 CFGLock : 1;
+ UINT32 Reserved3 : 9;
///
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
/// will conditionally demote C6/C7 requests to C3 based on uncore
/// auto-demote information.
///
- UINT32 C3AutoDemotion:1;
+ UINT32 C3AutoDemotion : 1;
///
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore
/// auto-demote information.
///
- UINT32 C1AutoDemotion:1;
+ UINT32 C1AutoDemotion : 1;
///
/// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
/// demoted C3.
///
- UINT32 C3Undemotion:1;
+ UINT32 C3Undemotion : 1;
///
/// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
/// demoted C1.
///
- UINT32 C1Undemotion:1;
- UINT32 Reserved4:3;
- UINT32 Reserved5:32;
+ UINT32 C1Undemotion : 1;
+ UINT32 Reserved4 : 3;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
-
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
@@ -227,8 +225,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
-
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
/**
Package. Base TDP Ratio (R/O).
@@ -247,7 +244,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
@@ -261,21 +258,20 @@ typedef union { /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
/// specific processor (in units of 100 MHz).
///
- UINT32 Config_TDP_Base:8;
- UINT32 Reserved1:24;
- UINT32 Reserved2:32;
+ UINT32 Config_TDP_Base : 8;
+ UINT32 Reserved1 : 24;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
-
/**
Package. ConfigTDP Level 1 ratio and power level (R/O).
@@ -293,7 +289,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
@@ -306,34 +302,33 @@ typedef union { ///
/// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
///
- UINT32 PKG_TDP_LVL1:15;
- UINT32 Reserved1:1;
+ UINT32 PKG_TDP_LVL1 : 15;
+ UINT32 Reserved1 : 1;
///
/// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
/// for this specific processor.
///
- UINT32 Config_TDP_LVL1_Ratio:8;
- UINT32 Reserved2:8;
+ UINT32 Config_TDP_LVL1_Ratio : 8;
+ UINT32 Reserved2 : 8;
///
/// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
/// Level 1.
///
- UINT32 PKG_MAX_PWR_LVL1:15;
- UINT32 Reserved3:1;
+ UINT32 PKG_MAX_PWR_LVL1 : 15;
+ UINT32 Reserved3 : 1;
///
/// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
/// Level 1.
///
- UINT32 PKG_MIN_PWR_LVL1:15;
- UINT32 Reserved4:1;
+ UINT32 PKG_MIN_PWR_LVL1 : 15;
+ UINT32 Reserved4 : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
-
/**
Package. ConfigTDP Level 2 ratio and power level (R/O).
@@ -351,7 +346,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
@@ -364,34 +359,33 @@ typedef union { ///
/// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
///
- UINT32 PKG_TDP_LVL2:15;
- UINT32 Reserved1:1;
+ UINT32 PKG_TDP_LVL2 : 15;
+ UINT32 Reserved1 : 1;
///
/// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
/// for this specific processor.
///
- UINT32 Config_TDP_LVL2_Ratio:8;
- UINT32 Reserved2:8;
+ UINT32 Config_TDP_LVL2_Ratio : 8;
+ UINT32 Reserved2 : 8;
///
/// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
/// Level 2.
///
- UINT32 PKG_MAX_PWR_LVL2:15;
- UINT32 Reserved3:1;
+ UINT32 PKG_MAX_PWR_LVL2 : 15;
+ UINT32 Reserved3 : 1;
///
/// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
/// Level 2.
///
- UINT32 PKG_MIN_PWR_LVL2:15;
- UINT32 Reserved4:1;
+ UINT32 PKG_MIN_PWR_LVL2 : 15;
+ UINT32 Reserved4 : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
-
/**
Package. ConfigTDP Control (R/W).
@@ -410,7 +404,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
**/
-#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
@@ -423,26 +417,25 @@ typedef union { ///
/// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
///
- UINT32 TDP_LEVEL:2;
- UINT32 Reserved1:29;
+ UINT32 TDP_LEVEL : 2;
+ UINT32 Reserved1 : 29;
///
/// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
/// this register is locked until a reset.
///
- UINT32 Config_TDP_Lock:1;
- UINT32 Reserved2:32;
+ UINT32 Config_TDP_Lock : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
-
/**
Package. ConfigTDP Control (R/W).
@@ -461,7 +454,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
**/
-#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
@@ -475,26 +468,25 @@ typedef union { /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
/// field.
///
- UINT32 MAX_NON_TURBO_RATIO:8;
- UINT32 Reserved1:23;
+ UINT32 MAX_NON_TURBO_RATIO : 8;
+ UINT32 Reserved1 : 23;
///
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
/// content of this register is locked until a reset.
///
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;
- UINT32 Reserved2:32;
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
-
/**
Package. Protected Processor Inventory Number Enable Control (R/W).
@@ -513,7 +505,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
+#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
@@ -533,28 +525,27 @@ typedef union { /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
/// prevent unauthorized modification to MSR_PPIN_CTL.
///
- UINT32 LockOut:1;
+ UINT32 LockOut : 1;
///
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
/// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
/// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
/// is 0.
///
- UINT32 Enable_PPIN:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 Enable_PPIN : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
-
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
Inventory Number (R/O) A unique value within a given CPUID
@@ -575,8 +566,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
**/
-#define MSR_IVY_BRIDGE_PPIN 0x0000004F
-
+#define MSR_IVY_BRIDGE_PPIN 0x0000004F
/**
Package. See http://biosbits.org.
@@ -596,7 +586,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
**/
-#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
@@ -606,14 +596,14 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
/// MHz.
///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:7;
+ UINT32 MaximumNonTurboRatio : 8;
+ UINT32 Reserved2 : 7;
///
/// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
/// Protected Processor Inventory Number (PPIN) capability can be enabled
@@ -621,45 +611,44 @@ typedef union { /// set to 0, PPIN capability is not supported. An attempt to access
/// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
///
- UINT32 PPIN_CAP:1;
- UINT32 Reserved3:4;
+ UINT32 PPIN_CAP : 1;
+ UINT32 Reserved3 : 4;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
/// enabled, and when set to 0, indicates Programmable Ratio Limits for
/// Turbo mode is disabled.
///
- UINT32 RatioLimit:1;
+ UINT32 RatioLimit : 1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
/// and when set to 0, indicates TDP Limit for Turbo mode is not
/// programmable.
///
- UINT32 TDPLimit:1;
+ UINT32 TDPLimit : 1;
///
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
/// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
/// specify an temperature offset.
///
- UINT32 TJOFFSET:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:8;
+ UINT32 TJOFFSET : 1;
+ UINT32 Reserved4 : 1;
+ UINT32 Reserved5 : 8;
///
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
/// minimum ratio (maximum efficiency) that the processor can operates, in
/// units of 100MHz.
///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved6:16;
+ UINT32 MaximumEfficiencyRatio : 8;
+ UINT32 Reserved6 : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
-
/**
Package. MC Bank Error Configuration (R/W).
@@ -678,7 +667,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
**/
-#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
+#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
@@ -688,26 +677,25 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
/// to log additional info in bits 36:32.
///
- UINT32 MemErrorLogEnable:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
+ UINT32 MemErrorLogEnable : 1;
+ UINT32 Reserved2 : 30;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
-
/**
Package.
@@ -726,7 +714,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
**/
-#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
@@ -736,33 +724,32 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bits 23:16] Temperature Target (RO) The minimum temperature at which
/// PROCHOT# will be asserted. The value is degree C.
///
- UINT32 TemperatureTarget:8;
+ UINT32 TemperatureTarget : 8;
///
/// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature
/// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
/// will assert at the offset target temperature. Write is permitted only
/// MSR_PLATFORM_INFO.[30] is set.
///
- UINT32 TCCActivationOffset:4;
- UINT32 Reserved2:4;
- UINT32 Reserved3:32;
+ UINT32 TCCActivationOffset : 4;
+ UINT32 Reserved2 : 4;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -781,7 +768,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
**/
-#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
@@ -795,53 +782,52 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
/// limit of 9 core active.
///
- UINT32 Maximum9C:8;
+ UINT32 Maximum9C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
/// limit of 10core active.
///
- UINT32 Maximum10C:8;
+ UINT32 Maximum10C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
/// limit of 11 core active.
///
- UINT32 Maximum11C:8;
+ UINT32 Maximum11C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
/// limit of 12 core active.
///
- UINT32 Maximum12C:8;
+ UINT32 Maximum12C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
/// limit of 13 core active.
///
- UINT32 Maximum13C:8;
+ UINT32 Maximum13C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
/// limit of 14 core active.
///
- UINT32 Maximum14C:8;
+ UINT32 Maximum14C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
/// limit of 15 core active.
///
- UINT32 Maximum15C:8;
- UINT32 Reserved:7;
+ UINT32 Maximum15C : 8;
+ UINT32 Reserved : 7;
///
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
/// the processor uses override configuration specified in
/// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
/// uses factory-set configuration (Default).
///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
-
/**
Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
@@ -859,7 +845,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
**/
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
@@ -872,29 +858,28 @@ typedef union { ///
/// [Bits 5:0] Recoverable Address LSB.
///
- UINT32 RecoverableAddressLSB:6;
+ UINT32 RecoverableAddressLSB : 6;
///
/// [Bits 8:6] Address Mode.
///
- UINT32 AddressMode:3;
- UINT32 Reserved1:7;
+ UINT32 AddressMode : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bits 31:16] PCI Express Requestor ID.
///
- UINT32 PCIExpressRequestorID:16;
+ UINT32 PCIExpressRequestorID : 16;
///
/// [Bits 39:32] PCI Express Segment Number.
///
- UINT32 PCIExpressSegmentNumber:8;
- UINT32 Reserved2:24;
+ UINT32 PCIExpressSegmentNumber : 8;
+ UINT32 Reserved2 : 24;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
-
/**
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
@@ -918,12 +903,11 @@ typedef union { MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
-#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
-#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
/// @}
-
/**
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
@@ -947,12 +931,11 @@ typedef union { MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
-#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
-#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
/// @}
-
/**
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
@@ -976,12 +959,11 @@ typedef union { MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
-#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
-#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
/// @}
-
/**
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
@@ -1005,12 +987,11 @@ typedef union { MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
-#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
-#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
/// @}
-
/**
Package. Package RAPL Perf Status (R/O).
@@ -1026,8 +1007,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
-
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
/**
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
@@ -1046,8 +1026,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
**/
-#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
-
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
/**
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -1064,8 +1043,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
-
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
@@ -1083,8 +1061,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
-
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
/**
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -1102,8 +1079,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
**/
-#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
-
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
/**
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@@ -1123,7 +1099,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
-#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
+#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
@@ -1136,45 +1112,44 @@ typedef union { ///
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
///
- UINT32 PEBS_EN_PMC0:1;
+ UINT32 PEBS_EN_PMC0 : 1;
///
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
///
- UINT32 PEBS_EN_PMC1:1;
+ UINT32 PEBS_EN_PMC1 : 1;
///
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
///
- UINT32 PEBS_EN_PMC2:1;
+ UINT32 PEBS_EN_PMC2 : 1;
///
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
///
- UINT32 PEBS_EN_PMC3:1;
- UINT32 Reserved1:28;
+ UINT32 PEBS_EN_PMC3 : 1;
+ UINT32 Reserved1 : 28;
///
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
///
- UINT32 LL_EN_PMC0:1;
+ UINT32 LL_EN_PMC0 : 1;
///
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
///
- UINT32 LL_EN_PMC1:1;
+ UINT32 LL_EN_PMC1 : 1;
///
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
///
- UINT32 LL_EN_PMC2:1;
+ UINT32 LL_EN_PMC2 : 1;
///
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
///
- UINT32 LL_EN_PMC3:1;
- UINT32 Reserved2:28;
+ UINT32 LL_EN_PMC3 : 1;
+ UINT32 Reserved2 : 28;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
-
/**
Package. Uncore perfmon per-socket global control.
@@ -1191,8 +1166,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
-
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
/**
Package. Uncore perfmon per-socket global status.
@@ -1210,8 +1184,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
-
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
/**
Package. Uncore perfmon per-socket global configuration.
@@ -1229,8 +1202,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
**/
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
-
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
/**
Package. Uncore U-box perfmon U-box wide status.
@@ -1248,8 +1220,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
-
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
/**
Package. Uncore PCU perfmon box wide status.
@@ -1267,8 +1238,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
**/
-#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
-
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
/**
Package. Uncore C-box 0 perfmon box wide filter1.
@@ -1286,8 +1256,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
-
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
/**
Package. Uncore C-box 1 perfmon box wide filter1.
@@ -1305,8 +1274,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
-
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
/**
Package. Uncore C-box 2 perfmon box wide filter1.
@@ -1324,8 +1292,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
-
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
/**
Package. Uncore C-box 3 perfmon box wide filter1.
@@ -1343,8 +1310,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
-
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
/**
Package. Uncore C-box 4 perfmon box wide filter1.
@@ -1362,8 +1328,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
-
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
/**
Package. Uncore C-box 5 perfmon box wide filter1.
@@ -1381,8 +1346,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
-
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
/**
Package. Uncore C-box 6 perfmon box wide filter1.
@@ -1400,8 +1364,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
-
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
/**
Package. Uncore C-box 7 perfmon box wide filter1.
@@ -1419,8 +1382,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
-
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
/**
Package. Uncore C-box 8 perfmon local box wide control.
@@ -1438,8 +1400,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
-
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
@@ -1457,8 +1418,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
-
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
@@ -1476,8 +1436,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
-
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
@@ -1495,8 +1454,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
-
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
/**
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
@@ -1514,8 +1472,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
-
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
/**
Package. Uncore C-box 8 perfmon box wide filter.
@@ -1533,8 +1490,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
-
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
/**
Package. Uncore C-box 8 perfmon counter 0.
@@ -1552,8 +1508,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
-
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
/**
Package. Uncore C-box 8 perfmon counter 1.
@@ -1571,8 +1526,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
-
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
/**
Package. Uncore C-box 8 perfmon counter 2.
@@ -1590,8 +1544,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
-
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
/**
Package. Uncore C-box 8 perfmon counter 3.
@@ -1609,8 +1562,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
-
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
/**
Package. Uncore C-box 8 perfmon box wide filter1.
@@ -1628,8 +1580,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
-
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
/**
Package. Uncore C-box 9 perfmon local box wide control.
@@ -1647,8 +1598,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
-
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
@@ -1666,8 +1616,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
-
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
@@ -1685,8 +1634,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
-
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
@@ -1704,8 +1652,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
-
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
/**
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
@@ -1723,8 +1670,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
-
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
/**
Package. Uncore C-box 9 perfmon box wide filter.
@@ -1742,8 +1688,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
-
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
/**
Package. Uncore C-box 9 perfmon counter 0.
@@ -1761,8 +1706,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
-
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
/**
Package. Uncore C-box 9 perfmon counter 1.
@@ -1780,8 +1724,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
-
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
/**
Package. Uncore C-box 9 perfmon counter 2.
@@ -1799,8 +1742,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
-
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
/**
Package. Uncore C-box 9 perfmon counter 3.
@@ -1818,8 +1760,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
-
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
/**
Package. Uncore C-box 9 perfmon box wide filter1.
@@ -1837,8 +1778,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
-
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
/**
Package. Uncore C-box 10 perfmon local box wide control.
@@ -1856,8 +1796,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
-
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
@@ -1875,8 +1814,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
-
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
@@ -1894,8 +1832,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
-
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
@@ -1913,8 +1850,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
-
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
/**
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
@@ -1932,8 +1868,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
-
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
/**
Package. Uncore C-box 10 perfmon box wide filter.
@@ -1951,8 +1886,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
-
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
/**
Package. Uncore C-box 10 perfmon counter 0.
@@ -1970,8 +1904,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
-
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
/**
Package. Uncore C-box 10 perfmon counter 1.
@@ -1989,8 +1922,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
-
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
/**
Package. Uncore C-box 10 perfmon counter 2.
@@ -2008,8 +1940,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
-
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
/**
Package. Uncore C-box 10 perfmon counter 3.
@@ -2027,8 +1958,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
-
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
/**
Package. Uncore C-box 10 perfmon box wide filter1.
@@ -2046,8 +1976,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
-
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
/**
Package. Uncore C-box 11 perfmon local box wide control.
@@ -2065,8 +1994,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
-
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
@@ -2084,8 +2012,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
-
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
@@ -2103,8 +2030,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
-
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
@@ -2122,8 +2048,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
-
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
/**
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
@@ -2141,8 +2066,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
-
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
/**
Package. Uncore C-box 11 perfmon box wide filter.
@@ -2160,8 +2084,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
-
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
/**
Package. Uncore C-box 11 perfmon counter 0.
@@ -2179,8 +2102,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
-
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
/**
Package. Uncore C-box 11 perfmon counter 1.
@@ -2198,8 +2120,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
-
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
/**
Package. Uncore C-box 11 perfmon counter 2.
@@ -2217,8 +2138,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
-
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
/**
Package. Uncore C-box 11 perfmon counter 3.
@@ -2236,8 +2156,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
-
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
/**
Package. Uncore C-box 11 perfmon box wide filter1.
@@ -2255,8 +2174,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
-
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
/**
Package. Uncore C-box 12 perfmon local box wide control.
@@ -2274,8 +2192,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
-
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
@@ -2293,8 +2210,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
-
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
@@ -2312,8 +2228,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
-
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
@@ -2331,8 +2246,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
-
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
/**
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
@@ -2350,8 +2264,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
-
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
/**
Package. Uncore C-box 12 perfmon box wide filter.
@@ -2369,8 +2282,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
-
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
/**
Package. Uncore C-box 12 perfmon counter 0.
@@ -2388,8 +2300,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
-
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
/**
Package. Uncore C-box 12 perfmon counter 1.
@@ -2407,8 +2318,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
-
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
/**
Package. Uncore C-box 12 perfmon counter 2.
@@ -2426,8 +2336,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
-
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
/**
Package. Uncore C-box 12 perfmon counter 3.
@@ -2445,8 +2354,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
-
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
/**
Package. Uncore C-box 12 perfmon box wide filter1.
@@ -2464,8 +2372,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
-
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
/**
Package. Uncore C-box 13 perfmon local box wide control.
@@ -2483,8 +2390,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
-
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
@@ -2502,8 +2408,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
-
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
@@ -2521,8 +2426,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
-
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
@@ -2540,8 +2444,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
-
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
/**
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
@@ -2559,8 +2462,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
-
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
/**
Package. Uncore C-box 13 perfmon box wide filter.
@@ -2578,8 +2480,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
-
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
/**
Package. Uncore C-box 13 perfmon counter 0.
@@ -2597,8 +2498,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
-
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
/**
Package. Uncore C-box 13 perfmon counter 1.
@@ -2616,8 +2516,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
-
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
/**
Package. Uncore C-box 13 perfmon counter 2.
@@ -2635,8 +2534,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
-
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
/**
Package. Uncore C-box 13 perfmon counter 3.
@@ -2654,8 +2552,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
-
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
/**
Package. Uncore C-box 13 perfmon box wide filter1.
@@ -2673,8 +2570,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
-
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
/**
Package. Uncore C-box 14 perfmon local box wide control.
@@ -2692,8 +2588,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
-
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
@@ -2711,8 +2606,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
-
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
@@ -2730,8 +2624,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
-
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
@@ -2749,8 +2642,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
-
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
/**
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
@@ -2768,8 +2660,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
-
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
/**
Package. Uncore C-box 14 perfmon box wide filter.
@@ -2787,8 +2678,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
-
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
/**
Package. Uncore C-box 14 perfmon counter 0.
@@ -2806,8 +2696,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
-
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
/**
Package. Uncore C-box 14 perfmon counter 1.
@@ -2825,8 +2714,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
-
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
/**
Package. Uncore C-box 14 perfmon counter 2.
@@ -2844,8 +2732,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
-
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
/**
Package. Uncore C-box 14 perfmon counter 3.
@@ -2863,8 +2750,7 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
-
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
/**
Package. Uncore C-box 14 perfmon box wide filter1.
@@ -2882,6 +2768,6 @@ typedef union { @endcode
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
**/
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA
#endif
|