diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h | 181 |
1 files changed, 82 insertions, 99 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h b/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h index 4a0e0ba3bd..c63a32f99c 100644 --- a/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h @@ -52,8 +52,7 @@ @endcode
@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
-#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
-
+#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.".
@@ -71,8 +70,7 @@ @endcode
@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
-#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
-
+#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
/**
Processor Hard Power-On Configuration (R/W) Enables and disables processor
@@ -93,7 +91,7 @@ @endcode
@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
-#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
+#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
@@ -103,93 +101,92 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
/// Pentium M processor.
///
- UINT32 DataErrorCheckingEnable:1;
+ UINT32 DataErrorCheckingEnable : 1;
///
/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
/// the Pentium M processor.
///
- UINT32 ResponseErrorCheckingEnable:1;
+ UINT32 ResponseErrorCheckingEnable : 1;
///
/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
- UINT32 MCERR_DriveEnable:1;
+ UINT32 MCERR_DriveEnable : 1;
///
/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
/// M processor.
///
- UINT32 AddressParityEnable:1;
- UINT32 Reserved2:2;
+ UINT32 AddressParityEnable : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
/// the Pentium M processor.
///
- UINT32 BINIT_DriverEnable:1;
+ UINT32 BINIT_DriverEnable : 1;
///
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 OutputTriStateEnable:1;
+ UINT32 OutputTriStateEnable : 1;
///
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
///
- UINT32 ExecuteBIST:1;
+ UINT32 ExecuteBIST : 1;
///
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
- UINT32 MCERR_ObservationEnabled:1;
- UINT32 Reserved3:1;
+ UINT32 MCERR_ObservationEnabled : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
/// Always 0 on the Pentium M processor.
///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved4:1;
+ UINT32 BINIT_ObservationEnabled : 1;
+ UINT32 Reserved4 : 1;
///
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
/// Always 0 on the Pentium M processor.
///
- UINT32 ResetVector:1;
- UINT32 Reserved5:1;
+ UINT32 ResetVector : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
/// processor.
///
- UINT32 APICClusterID:2;
+ UINT32 APICClusterID : 2;
///
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
/// 0 on the Pentium M processor.
///
- UINT32 SystemBusFrequency:1;
- UINT32 Reserved6:1;
+ UINT32 SystemBusFrequency : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
/// M processor.
///
- UINT32 SymmetricArbitrationID:2;
+ UINT32 SymmetricArbitrationID : 2;
///
/// [Bits 26:22] Clock Frequency Ratio (R/O).
///
- UINT32 ClockFrequencyRatio:5;
- UINT32 Reserved7:5;
- UINT32 Reserved8:32;
+ UINT32 ClockFrequencyRatio : 5;
+ UINT32 Reserved7 : 5;
+ UINT32 Reserved8 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
-
/**
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
@@ -218,17 +215,16 @@ typedef union { MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
@{
**/
-#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
-#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
-#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
-#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
-#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
-#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
-#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
-#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
+#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
+#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
+#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
+#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
+#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
+#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
+#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
+#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
/// @}
-
/**
Reserved.
@@ -245,8 +241,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
**/
-#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
-
+#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
/**
@@ -266,7 +261,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
-#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
+#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
@@ -280,41 +275,40 @@ typedef union { /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:4;
+ UINT32 L2HardwareEnabled : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
/// cache data bus. ECC is always generated on write cycles. 1. = Disabled
/// (default) 2. = Enabled For the Pentium M processor, ECC checking on
/// the cache data bus is always enabled.
///
- UINT32 ECCCheckEnable:1;
- UINT32 Reserved2:2;
+ UINT32 ECCCheckEnable : 1;
+ UINT32 Reserved2 : 2;
///
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
- UINT32 L2Enabled:1;
- UINT32 Reserved3:14;
+ UINT32 L2Enabled : 1;
+ UINT32 Reserved3 : 14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
- UINT32 L2NotPresent:1;
- UINT32 Reserved4:8;
- UINT32 Reserved5:32;
+ UINT32 L2NotPresent : 1;
+ UINT32 Reserved4 : 8;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
-
/**
@@ -333,7 +327,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
**/
-#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
+#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
/**
MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
@@ -343,7 +337,7 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the
@@ -351,21 +345,20 @@ typedef union { /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
///
- UINT32 TM_SELECT:1;
- UINT32 Reserved2:15;
- UINT32 Reserved3:32;
+ UINT32 TM_SELECT : 1;
+ UINT32 Reserved2 : 15;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
-
/**
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -385,7 +378,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
+#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
@@ -395,7 +388,7 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:3;
+ UINT32 Reserved1 : 3;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
/// this bit enables the thermal control circuit (TCC) portion of the
@@ -410,14 +403,14 @@ typedef union { /// this feature. The bit should not be confused with the on-demand
/// thermal control circuit enable bit.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance
/// monitoring enabled 0 = Performance monitoring disabled.
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:2;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 2;
///
/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
/// processor to indicate a pending break event within the processor 0 =
@@ -426,48 +419,47 @@ typedef union { /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
/// support branch trace storage (BTS) 0 = BTS is supported
///
- UINT32 FERR:1;
+ UINT32 FERR : 1;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO)
/// 1 = Processor doesn't support branch trace storage (BTS)
/// 0 = BTS is supported
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
/// Processor does not support processor event based sampling (PEBS); 0 =
/// PEBS is supported. The Pentium M processor does not support PEBS.
///
- UINT32 PEBS:1;
- UINT32 Reserved5:3;
+ UINT32 PEBS : 1;
+ UINT32 Reserved5 : 3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
/// processor, this bit may be configured to be read-only.
///
- UINT32 EIST:1;
- UINT32 Reserved6:6;
+ UINT32 EIST : 1;
+ UINT32 Reserved6 : 6;
///
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
/// disabled. xTPR messages are optional messages that allow the processor
/// to inform the chipset of its priority. The default is processor
/// specific.
///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:32;
+ UINT32 xTPR_Message_Disable : 1;
+ UINT32 Reserved7 : 8;
+ UINT32 Reserved8 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
-
/**
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
to the MSR containing the most recent branch record. See also: -
@@ -487,8 +479,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
-#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
-
+#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
/**
Debug Control (R/W) Controls how several debug features are used. Bit
@@ -508,8 +499,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
**/
-#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
-
+#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
/**
Last Exception Record To Linear IP (R) This area contains a pointer to the
@@ -531,8 +521,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
-#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
-
+#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
/**
Last Exception Record From Linear IP (R) Contains a pointer to the last
@@ -553,8 +542,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
-#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
-
+#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@@ -572,8 +560,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
-#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
-
+#define MSR_PENTIUM_M_MC4_CTL 0x0000040C
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@@ -591,8 +578,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
-#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
-
+#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
@@ -613,8 +599,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
-#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
-
+#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
/**
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
@@ -632,8 +617,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
**/
-#define MSR_PENTIUM_M_MC3_CTL 0x00000410
-
+#define MSR_PENTIUM_M_MC3_CTL 0x00000410
/**
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
@@ -651,8 +635,7 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
**/
-#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
-
+#define MSR_PENTIUM_M_MC3_STATUS 0x00000411
/**
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
@@ -673,6 +656,6 @@ typedef union { @endcode
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
-#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
+#define MSR_PENTIUM_M_MC3_ADDR 0x00000412
#endif
|