diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/PentiumMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/PentiumMsr.h | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h b/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h index 5907432b7b..ff8c9b3f9b 100644 --- a/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h @@ -54,8 +54,7 @@ @endcode
@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
**/
-#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
-
+#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
/**
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
@@ -73,8 +72,7 @@ @endcode
@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
**/
-#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
-
+#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
/**
See Section 17.17, "Time-Stamp Counter.".
@@ -92,8 +90,7 @@ @endcode
@note MSR_PENTIUM_TSC is defined as TSC in SDM.
**/
-#define MSR_PENTIUM_TSC 0x00000010
-
+#define MSR_PENTIUM_TSC 0x00000010
/**
See Section 18.6.9.1, "Control and Event Select Register (CESR).".
@@ -111,8 +108,7 @@ @endcode
@note MSR_PENTIUM_CESR is defined as CESR in SDM.
**/
-#define MSR_PENTIUM_CESR 0x00000011
-
+#define MSR_PENTIUM_CESR 0x00000011
/**
Section 18.6.9.3, "Events Counted.".
@@ -132,8 +128,8 @@ MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
@{
**/
-#define MSR_PENTIUM_CTR0 0x00000012
-#define MSR_PENTIUM_CTR1 0x00000013
+#define MSR_PENTIUM_CTR0 0x00000012
+#define MSR_PENTIUM_CTR1 0x00000013
/// @}
#endif
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