diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h | 447 |
1 files changed, 206 insertions, 241 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h b/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h index cc0dc03c7c..1880244639 100644 --- a/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h @@ -57,7 +57,7 @@ @endcode
@note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
**/
-#define MSR_SILVERMONT_PLATFORM_ID 0x00000017
+#define MSR_SILVERMONT_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
@@ -67,26 +67,25 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
///
- UINT32 MaximumQualifiedRatio:5;
- UINT32 Reserved2:19;
- UINT32 Reserved3:18;
+ UINT32 MaximumQualifiedRatio : 5;
+ UINT32 Reserved2 : 19;
+ UINT32 Reserved3 : 18;
///
/// [Bits 52:50] See Table 2-2.
///
- UINT32 PlatformId:3;
- UINT32 Reserved4:11;
+ UINT32 PlatformId : 3;
+ UINT32 Reserved4 : 11;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
-
/**
Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
@@ -105,7 +104,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
**/
-#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
+#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
/**
MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
@@ -115,20 +114,19 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:32;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
-
/**
Core. SMI Counter (R/O).
@@ -146,7 +144,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
**/
-#define MSR_SILVERMONT_SMI_COUNT 0x00000034
+#define MSR_SILVERMONT_SMI_COUNT 0x00000034
/**
MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
@@ -160,20 +158,19 @@ typedef union { /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
/// RESET.
///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
+ UINT32 SMICount : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_SMI_COUNT_REGISTER;
-
/**
Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
@@ -194,7 +191,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
**/
-#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A
/**
MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
@@ -207,26 +204,25 @@ typedef union { ///
/// [Bit 0] Lock (R/WL).
///
- UINT32 Lock:1;
- UINT32 Reserved1:1;
+ UINT32 Lock : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Enable VMX outside SMX operation (R/WL).
///
- UINT32 EnableVmxOutsideSmx:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
+ UINT32 EnableVmxOutsideSmx : 1;
+ UINT32 Reserved2 : 29;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
-
/**
Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The From_IP part of the
@@ -255,17 +251,16 @@ typedef union { MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
@{
**/
-#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
-#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
-#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
-#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
-#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
-#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
-#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
-#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
/// @}
-
/**
Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
record registers on the last branch record stack. The To_IP part of the
@@ -292,17 +287,16 @@ typedef union { MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
@{
**/
-#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
-#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
-#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
-#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
-#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
-#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
-#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
-#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
/// @}
-
/**
Module. Scalable Bus Speed(RO) This field indicates the intended scalable
bus clock speed for processors based on Silvermont microarchitecture:.
@@ -321,7 +315,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
**/
-#define MSR_SILVERMONT_FSB_FREQ 0x000000CD
+#define MSR_SILVERMONT_FSB_FREQ 0x000000CD
/**
MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
@@ -354,21 +348,20 @@ typedef union { /// 0111B: 088.9 MHz
/// 1000B: 087.5 MHz
///
- UINT32 ScalableBusSpeed:4;
- UINT32 Reserved1:28;
- UINT32 Reserved2:32;
+ UINT32 ScalableBusSpeed : 4;
+ UINT32 Reserved1 : 28;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_FSB_FREQ_REGISTER;
-
/**
Package. Platform Information: Contains power management and other model
specific features enumeration. See http://biosbits.org.
@@ -387,7 +380,7 @@ typedef union { AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
@endcode
**/
-#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE
/**
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
@@ -397,24 +390,24 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
/// of the maximum frequency that does not require turbo. Frequency =
/// ratio * Scalable Bus Frequency.
///
- UINT32 MaximumNon_TurboRatio:8;
- UINT32 Reserved2:16;
- UINT32 Reserved3:32;
+ UINT32 MaximumNon_TurboRatio : 8;
+ UINT32 Reserved2 : 16;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
/**
@@ -437,7 +430,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
-#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
@@ -455,34 +448,33 @@ typedef union { /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
/// 100b: C4 110b: C6 111b: C7 (Silvermont only).
///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
+ UINT32 Limit : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
/// IO_read instructions sent to IO register specified by
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
+ UINT32 IO_MWAIT : 1;
+ UINT32 Reserved2 : 4;
///
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
/// until next reset.
///
- UINT32 CFGLock:1;
- UINT32 Reserved3:16;
- UINT32 Reserved4:32;
+ UINT32 CFGLock : 1;
+ UINT32 Reserved3 : 16;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
-
/**
Module. Power Management IO Redirection in C-state (R/W) See
http://biosbits.org.
@@ -502,7 +494,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
**/
-#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
/**
MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
@@ -520,7 +512,7 @@ typedef union { /// address redirection is enabled, this is the IO port address reported
/// to the OS/software.
///
- UINT32 Lvl2Base:16;
+ UINT32 Lvl2Base : 16;
///
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
/// maximum C-State code name to be included when IO read to MWAIT
@@ -528,21 +520,20 @@ typedef union { /// is the max C-State to include 110b - C6 is the max C-State to include
/// 111b - C7 is the max C-State to include.
///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
- UINT32 Reserved2:32;
+ UINT32 CStateRange : 3;
+ UINT32 Reserved1 : 13;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
-
/**
Module.
@@ -561,7 +552,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
**/
-#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
+#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
/**
MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
@@ -575,33 +566,32 @@ typedef union { /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
/// Indicates if the L2 is hardware-disabled.
///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
+ UINT32 L2HardwareEnabled : 1;
+ UINT32 Reserved1 : 7;
///
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
/// Disabled (default) Until this bit is set the processor will not
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
+ UINT32 L2Enabled : 1;
+ UINT32 Reserved2 : 14;
///
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
+ UINT32 L2NotPresent : 1;
+ UINT32 Reserved3 : 8;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
-
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@@ -621,7 +611,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
-#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
+#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
@@ -640,21 +630,20 @@ typedef union { /// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 AESConfiguration : 2;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
-
/**
Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -674,7 +663,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
+#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
@@ -687,55 +676,55 @@ typedef union { ///
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
+ UINT32 FastStrings : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 2-2. Default value is 0.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 3;
///
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
/// Table 2-2.
///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
+ UINT32 PEBS : 1;
+ UINT32 Reserved4 : 3;
///
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 2-2.
///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
+ UINT32 EIST : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
+ UINT32 MONITOR : 1;
+ UINT32 Reserved6 : 3;
///
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
///
- UINT32 LimitCpuidMaxval:1;
+ UINT32 LimitCpuidMaxval : 1;
///
/// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
+ UINT32 xTPR_Message_Disable : 1;
+ UINT32 Reserved7 : 8;
+ UINT32 Reserved8 : 2;
///
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
///
- UINT32 XD:1;
- UINT32 Reserved9:3;
+ UINT32 XD : 1;
+ UINT32 Reserved9 : 3;
///
/// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
/// that support Intel Turbo Boost Technology, the turbo mode feature is
@@ -747,16 +736,15 @@ typedef union { /// in the processor. If power-on default value is 0, turbo mode is not
/// available.
///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved10:25;
+ UINT32 TurboModeDisable : 1;
+ UINT32 Reserved10 : 25;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
-
/**
Package.
@@ -775,7 +763,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
**/
-#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
+#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
/**
MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
@@ -785,34 +773,33 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bits 23:16] Temperature Target (R) The default thermal throttling or
/// PROCHOT# activation temperature in degree C, The effective temperature
/// for thermal throttling or PROCHOT# activation is "Temperature Target"
/// + "Target Offset".
///
- UINT32 TemperatureTarget:8;
+ UINT32 TemperatureTarget : 8;
///
/// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to
/// adjust the throttling and PROCHOT# activation temperature from the
/// default target specified in TEMPERATURE_TARGET (bits 23:16).
///
- UINT32 TargetOffset:6;
- UINT32 Reserved2:2;
- UINT32 Reserved3:32;
+ UINT32 TargetOffset : 6;
+ UINT32 Reserved2 : 2;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
-
/**
Miscellaneous Feature Control (R/W).
@@ -831,7 +818,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
**/
-#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4
/**
MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
@@ -846,28 +833,27 @@ typedef union { /// L2 hardware prefetcher, which fetches additional lines of code or data
/// into the L2 cache.
///
- UINT32 L2HardwarePrefetcherDisable:1;
- UINT32 Reserved1:1;
+ UINT32 L2HardwarePrefetcherDisable : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
/// the L1 data cache prefetcher, which fetches the next cache line into
/// L1 data cache.
///
- UINT32 DCUHardwarePrefetcherDisable:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
+ UINT32 DCUHardwarePrefetcherDisable : 1;
+ UINT32 Reserved2 : 29;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
-
/**
Module. Offcore Response Event Select Register (R/W).
@@ -884,8 +870,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
**/
-#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
-
+#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
/**
Module. Offcore Response Event Select Register (R/W).
@@ -903,8 +888,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
-#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
-
+#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode (RW).
@@ -924,7 +908,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
-#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
@@ -938,50 +922,49 @@ typedef union { /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
/// limit of 1 core active.
///
- UINT32 Maximum1C:8;
+ UINT32 Maximum1C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
/// limit of 2 core active.
///
- UINT32 Maximum2C:8;
+ UINT32 Maximum2C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
/// limit of 3 core active.
///
- UINT32 Maximum3C:8;
+ UINT32 Maximum3C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
/// limit of 4 core active.
///
- UINT32 Maximum4C:8;
+ UINT32 Maximum4C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
/// limit of 5 core active.
///
- UINT32 Maximum5C:8;
+ UINT32 Maximum5C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
/// limit of 6 core active.
///
- UINT32 Maximum6C:8;
+ UINT32 Maximum6C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
/// limit of 7 core active.
///
- UINT32 Maximum7C:8;
+ UINT32 Maximum7C : 8;
///
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
/// limit of 8 core active.
///
- UINT32 Maximum8C:8;
+ UINT32 Maximum8C : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
-
/**
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
"Filtering of Last Branch Records.".
@@ -1001,7 +984,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
**/
-#define MSR_SILVERMONT_LBR_SELECT 0x000001C8
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8
/**
MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
@@ -1014,53 +997,52 @@ typedef union { ///
/// [Bit 0] CPL_EQ_0.
///
- UINT32 CPL_EQ_0:1;
+ UINT32 CPL_EQ_0 : 1;
///
/// [Bit 1] CPL_NEQ_0.
///
- UINT32 CPL_NEQ_0:1;
+ UINT32 CPL_NEQ_0 : 1;
///
/// [Bit 2] JCC.
///
- UINT32 JCC:1;
+ UINT32 JCC : 1;
///
/// [Bit 3] NEAR_REL_CALL.
///
- UINT32 NEAR_REL_CALL:1;
+ UINT32 NEAR_REL_CALL : 1;
///
/// [Bit 4] NEAR_IND_CALL.
///
- UINT32 NEAR_IND_CALL:1;
+ UINT32 NEAR_IND_CALL : 1;
///
/// [Bit 5] NEAR_RET.
///
- UINT32 NEAR_RET:1;
+ UINT32 NEAR_RET : 1;
///
/// [Bit 6] NEAR_IND_JMP.
///
- UINT32 NEAR_IND_JMP:1;
+ UINT32 NEAR_IND_JMP : 1;
///
/// [Bit 7] NEAR_REL_JMP.
///
- UINT32 NEAR_REL_JMP:1;
+ UINT32 NEAR_REL_JMP : 1;
///
/// [Bit 8] FAR_BRANCH.
///
- UINT32 FAR_BRANCH:1;
- UINT32 Reserved1:23;
- UINT32 Reserved2:32;
+ UINT32 FAR_BRANCH : 1;
+ UINT32 Reserved1 : 23;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_LBR_SELECT_REGISTER;
-
/**
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
points to the MSR containing the most recent branch record. See
@@ -1079,8 +1061,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
-#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
-
+#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
/**
Core. Last Exception Record From Linear IP (R) Contains a pointer to the
@@ -1099,8 +1080,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
-#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
-
+#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
/**
Core. Last Exception Record To Linear IP (R) This area contains a pointer
@@ -1120,8 +1100,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
-#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
-
+#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
/**
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
@@ -1142,7 +1121,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
-#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
+#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
/**
MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
@@ -1155,21 +1134,20 @@ typedef union { ///
/// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
///
- UINT32 PEBS:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 PEBS : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
-
/**
Package. Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
@@ -1189,8 +1167,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
**/
-#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
-
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
/**
Core. Note: C-state values are processor specific C-state code names,
@@ -1211,8 +1188,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
**/
-#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
-
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@@ -1229,8 +1205,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
**/
-#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
-
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
/**
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
@@ -1248,8 +1223,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
**/
-#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
-
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
/**
Core. Note: C-state values are processor specific C-state code names,
@@ -1270,8 +1244,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
**/
-#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
-
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
/**
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
@@ -1291,7 +1264,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
**/
-#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
+#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
/**
MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
@@ -1307,35 +1280,34 @@ typedef union { /// represented by bits 3:0. Default value is 0101b, indicating power unit
/// is in 32 milliWatts increment.
///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
+ UINT32 PowerUnits : 4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 12:8] Energy Status Units. Energy related information (in
/// microJoules) is based on the multiplier, 2^ESU; where ESU is an
/// unsigned integer represented by bits 12:8. Default value is 00101b,
/// indicating energy unit is in 32 microJoules increment.
///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
+ UINT32 EnergyStatusUnits : 5;
+ UINT32 Reserved2 : 3;
///
/// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
/// one second.
///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
+ UINT32 TimeUnits : 4;
+ UINT32 Reserved3 : 12;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
-
/**
Package. PKG RAPL Power Limit Control (R/W).
@@ -1354,7 +1326,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
**/
-#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
+#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
/**
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
@@ -1368,36 +1340,35 @@ typedef union { /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
/// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
///
- UINT32 Limit:15;
+ UINT32 Limit : 15;
///
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
/// RAPL Domain.".
///
- UINT32 Enable:1;
+ UINT32 Enable : 1;
///
/// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
/// "Package RAPL Domain.".
///
- UINT32 ClampingLimit:1;
+ UINT32 ClampingLimit : 1;
///
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
/// If 0 is specified in bits [23:17], defaults to 1 second window.
///
- UINT32 Time:7;
- UINT32 Reserved1:8;
- UINT32 Reserved2:32;
+ UINT32 Time : 7;
+ UINT32 Reserved1 : 8;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
-
/**
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
and MSR_RAPL_POWER_UNIT in Table 2-8.
@@ -1414,8 +1385,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
**/
-#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
-
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
@@ -1433,8 +1403,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
-#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
-
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
/**
Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
@@ -1453,8 +1422,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
**/
-#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
-
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
/**
Package. Module C6 demotion policy config MSR. Controls module (i.e. two
@@ -1474,8 +1442,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
**/
-#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
-
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
/**
Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
@@ -1495,8 +1462,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
**/
-#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
-
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
/**
Package. PKG RAPL Parameter (R/0).
@@ -1515,7 +1481,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
**/
-#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
+#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
/**
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
@@ -1531,21 +1497,20 @@ typedef union { /// The unit of this field is specified by the "Power Units" field of
/// MSR_RAPL_POWER_UNIT.
///
- UINT32 ThermalSpecPower:15;
- UINT32 Reserved1:17;
- UINT32 Reserved2:32;
+ UINT32 ThermalSpecPower : 15;
+ UINT32 Reserved1 : 17;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
-
/**
Package. PP0 RAPL Power Limit Control (R/W).
@@ -1564,7 +1529,7 @@ typedef union { @endcode
@note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
**/
-#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
+#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
/**
MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
@@ -1578,13 +1543,13 @@ typedef union { /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
/// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
///
- UINT32 Limit:15;
+ UINT32 Limit : 15;
///
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
/// RAPL Domains.".
///
- UINT32 Enable:1;
- UINT32 Reserved1:1;
+ UINT32 Enable : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
/// duration over which the average power must remain below
@@ -1595,18 +1560,18 @@ typedef union { /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
/// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
///
- UINT32 Time:7;
- UINT32 Reserved2:8;
- UINT32 Reserved3:32;
+ UINT32 Time : 7;
+ UINT32 Reserved2 : 8;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
#endif
|