diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/XeonDMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/XeonDMsr.h | 410 |
1 files changed, 195 insertions, 215 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h b/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h index f742aeb163..0dd0d79d9e 100644 --- a/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h @@ -55,7 +55,7 @@ @endcode
@note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
**/
-#define MSR_XEON_D_PPIN_CTL 0x0000004E
+#define MSR_XEON_D_PPIN_CTL 0x0000004E
/**
MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
@@ -68,25 +68,24 @@ typedef union { ///
/// [Bit 0] LockOut (R/WO) See Table 2-25.
///
- UINT32 LockOut:1;
+ UINT32 LockOut : 1;
///
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
///
- UINT32 Enable_PPIN:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 Enable_PPIN : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_PPIN_CTL_REGISTER;
-
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
Inventory Number (R/O) See Table 2-25.
@@ -103,8 +102,7 @@ typedef union { @endcode
@note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
**/
-#define MSR_XEON_D_PPIN 0x0000004F
-
+#define MSR_XEON_D_PPIN 0x0000004F
/**
Package. See http://biosbits.org.
@@ -124,7 +122,7 @@ typedef union { @endcode
@note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
**/
-#define MSR_XEON_D_PLATFORM_INFO 0x000000CE
+#define MSR_XEON_D_PLATFORM_INFO 0x000000CE
/**
MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
@@ -134,46 +132,45 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:7;
+ UINT32 MaximumNonTurboRatio : 8;
+ UINT32 Reserved2 : 7;
///
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
///
- UINT32 PPIN_CAP:1;
- UINT32 Reserved3:4;
+ UINT32 PPIN_CAP : 1;
+ UINT32 Reserved3 : 4;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
/// Table 2-25.
///
- UINT32 RatioLimit:1;
+ UINT32 RatioLimit : 1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
/// Table 2-25.
///
- UINT32 TDPLimit:1;
+ UINT32 TDPLimit : 1;
///
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
///
- UINT32 TJOFFSET:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:8;
+ UINT32 TJOFFSET : 1;
+ UINT32 Reserved4 : 1;
+ UINT32 Reserved5 : 8;
///
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved6:16;
+ UINT32 MaximumEfficiencyRatio : 8;
+ UINT32 Reserved6 : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_PLATFORM_INFO_REGISTER;
-
/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
@@ -194,7 +191,7 @@ typedef union { @endcode
@note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
-#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
@@ -213,61 +210,60 @@ typedef union { /// 011b: C6 (retention) 111b: No Package C state limits. All C states
/// supported by the processor are available.
///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
+ UINT32 Limit : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
+ UINT32 IO_MWAIT : 1;
+ UINT32 Reserved2 : 4;
///
/// [Bit 15] CFG Lock (R/WO).
///
- UINT32 CFGLock:1;
+ UINT32 CFGLock : 1;
///
/// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
/// will convert HALT or MWAT(C1) to MWAIT(C6).
///
- UINT32 CStateConversion:1;
- UINT32 Reserved3:8;
+ UINT32 CStateConversion : 1;
+ UINT32 Reserved3 : 8;
///
/// [Bit 25] C3 State Auto Demotion Enable (R/W).
///
- UINT32 C3AutoDemotion:1;
+ UINT32 C3AutoDemotion : 1;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W).
///
- UINT32 C1AutoDemotion:1;
+ UINT32 C1AutoDemotion : 1;
///
/// [Bit 27] Enable C3 Undemotion (R/W).
///
- UINT32 C3Undemotion:1;
+ UINT32 C3Undemotion : 1;
///
/// [Bit 28] Enable C1 Undemotion (R/W).
///
- UINT32 C1Undemotion:1;
+ UINT32 C1Undemotion : 1;
///
/// [Bit 29] Package C State Demotion Enable (R/W).
///
- UINT32 CStateDemotion:1;
+ UINT32 CStateDemotion : 1;
///
/// [Bit 30] Package C State UnDemotion Enable (R/W).
///
- UINT32 CStateUndemotion:1;
- UINT32 Reserved4:1;
- UINT32 Reserved5:32;
+ UINT32 CStateUndemotion : 1;
+ UINT32 Reserved4 : 1;
+ UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;
-
/**
Thread. Global Machine Check Capability (R/O).
@@ -285,7 +281,7 @@ typedef union { @endcode
@note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
**/
-#define MSR_XEON_D_IA32_MCG_CAP 0x00000179
+#define MSR_XEON_D_IA32_MCG_CAP 0x00000179
/**
MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
@@ -298,54 +294,53 @@ typedef union { ///
/// [Bits 7:0] Count.
///
- UINT32 Count:8;
+ UINT32 Count : 8;
///
/// [Bit 8] MCG_CTL_P.
///
- UINT32 MCG_CTL_P:1;
+ UINT32 MCG_CTL_P : 1;
///
/// [Bit 9] MCG_EXT_P.
///
- UINT32 MCG_EXT_P:1;
+ UINT32 MCG_EXT_P : 1;
///
/// [Bit 10] MCP_CMCI_P.
///
- UINT32 MCP_CMCI_P:1;
+ UINT32 MCP_CMCI_P : 1;
///
/// [Bit 11] MCG_TES_P.
///
- UINT32 MCG_TES_P:1;
- UINT32 Reserved1:4;
+ UINT32 MCG_TES_P : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bits 23:16] MCG_EXT_CNT.
///
- UINT32 MCG_EXT_CNT:8;
+ UINT32 MCG_EXT_CNT : 8;
///
/// [Bit 24] MCG_SER_P.
///
- UINT32 MCG_SER_P:1;
+ UINT32 MCG_SER_P : 1;
///
/// [Bit 25] MCG_EM_P.
///
- UINT32 MCG_EM_P:1;
+ UINT32 MCG_EM_P : 1;
///
/// [Bit 26] MCG_ELOG_P.
///
- UINT32 MCG_ELOG_P:1;
- UINT32 Reserved2:5;
- UINT32 Reserved3:32;
+ UINT32 MCG_ELOG_P : 1;
+ UINT32 Reserved2 : 5;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_IA32_MCG_CAP_REGISTER;
-
/**
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
Enhancement. Accessible only while in SMM.
@@ -365,7 +360,7 @@ typedef union { @endcode
@note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
**/
-#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
+#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
/**
MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
@@ -375,29 +370,28 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 26;
///
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
/// SMM code access restriction is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 SMM_Code_Access_Chk:1;
+ UINT32 SMM_Code_Access_Chk : 1;
///
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
/// SMM long flow indicator is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
+ UINT32 Long_Flow_Indication : 1;
+ UINT32 Reserved3 : 4;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_SMM_MCA_CAP_REGISTER;
-
/**
Package.
@@ -416,7 +410,7 @@ typedef union { @endcode
@note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
**/
-#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
+#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
/**
MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
@@ -426,29 +420,28 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.
///
- UINT32 TemperatureTarget:8;
+ UINT32 TemperatureTarget : 8;
///
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
///
- UINT32 TCCActivationOffset:4;
- UINT32 Reserved2:4;
- UINT32 Reserved3:32;
+ UINT32 TCCActivationOffset : 4;
+ UINT32 Reserved2 : 4;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -467,7 +460,7 @@ typedef union { @endcode
@note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
+#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
@@ -480,43 +473,42 @@ typedef union { ///
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
///
- UINT32 Maximum1C:8;
+ UINT32 Maximum1C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
///
- UINT32 Maximum2C:8;
+ UINT32 Maximum2C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
///
- UINT32 Maximum3C:8;
+ UINT32 Maximum3C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
///
- UINT32 Maximum4C:8;
+ UINT32 Maximum4C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
///
- UINT32 Maximum5C:8;
+ UINT32 Maximum5C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
///
- UINT32 Maximum6C:8;
+ UINT32 Maximum6C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
///
- UINT32 Maximum7C:8;
+ UINT32 Maximum7C : 8;
///
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
///
- UINT32 Maximum8C:8;
+ UINT32 Maximum8C : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;
-
/**
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -535,7 +527,7 @@ typedef union { @endcode
@note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
/**
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
@@ -548,43 +540,42 @@ typedef union { ///
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
///
- UINT32 Maximum9C:8;
+ UINT32 Maximum9C : 8;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
///
- UINT32 Maximum10C:8;
+ UINT32 Maximum10C : 8;
///
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
///
- UINT32 Maximum11C:8;
+ UINT32 Maximum11C : 8;
///
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
///
- UINT32 Maximum12C:8;
+ UINT32 Maximum12C : 8;
///
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
///
- UINT32 Maximum13C:8;
+ UINT32 Maximum13C : 8;
///
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
///
- UINT32 Maximum14C:8;
+ UINT32 Maximum14C : 8;
///
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
///
- UINT32 Maximum15C:8;
+ UINT32 Maximum15C : 8;
///
/// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
///
- UINT32 Maximum16C:8;
+ UINT32 Maximum16C : 8;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;
-
/**
Package. Unit Multipliers used in RAPL Interfaces (R/O).
@@ -602,7 +593,7 @@ typedef union { @endcode
@note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
**/
-#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
+#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
/**
MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
@@ -615,35 +606,34 @@ typedef union { ///
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
+ UINT32 PowerUnits : 4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 12:8] Package. Energy Status Units Energy related information
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
/// micro-joules).
///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
+ UINT32 EnergyStatusUnits : 5;
+ UINT32 Reserved2 : 3;
///
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
/// Interfaces.".
///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
+ UINT32 TimeUnits : 4;
+ UINT32 Reserved3 : 12;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;
-
/**
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
Domain.".
@@ -661,8 +651,7 @@ typedef union { @endcode
@note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
**/
-#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
-
+#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
/**
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
@@ -681,7 +670,7 @@ typedef union { @endcode
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
-#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
/**
MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS
@@ -695,20 +684,19 @@ typedef union { /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
/// to enable DRAM RAPL mode 0 (Direct VR).
///
- UINT32 Energy:32;
- UINT32 Reserved:32;
+ UINT32 Energy : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;
-
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
RAPL Domain.".
@@ -725,8 +713,7 @@ typedef union { @endcode
@note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
**/
-#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
-
+#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
/**
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -744,8 +731,7 @@ typedef union { @endcode
@note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
**/
-#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
-
+#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
/**
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
@@ -767,7 +753,7 @@ typedef union { AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
-#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
@@ -781,24 +767,24 @@ typedef union { /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
- UINT32 MAX_RATIO:7;
- UINT32 Reserved1:1;
+ UINT32 MAX_RATIO : 7;
+ UINT32 Reserved1 : 1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
- UINT32 MIN_RATIO:7;
- UINT32 Reserved2:17;
- UINT32 Reserved3:32;
+ UINT32 MIN_RATIO : 7;
+ UINT32 Reserved2 : 17;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;
/**
@@ -816,8 +802,7 @@ typedef union { @endcode
@note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
-#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639
-
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639
/**
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
@@ -838,7 +823,7 @@ typedef union { @endcode
@note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
**/
-#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
/**
MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
@@ -853,152 +838,151 @@ typedef union { /// reduced below the operating system request due to assertion of
/// external PROCHOT.
///
- UINT32 PROCHOT_Status:1;
+ UINT32 PROCHOT_Status : 1;
///
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
/// operating system request due to a thermal event.
///
- UINT32 ThermalStatus:1;
+ UINT32 ThermalStatus : 1;
///
/// [Bit 2] Power Budget Management Status (R0) When set, frequency is
/// reduced below the operating system request due to PBM limit.
///
- UINT32 PowerBudgetManagementStatus:1;
+ UINT32 PowerBudgetManagementStatus : 1;
///
/// [Bit 3] Platform Configuration Services Status (R0) When set,
/// frequency is reduced below the operating system request due to PCS
/// limit.
///
- UINT32 PlatformConfigurationServicesStatus:1;
- UINT32 Reserved1:1;
+ UINT32 PlatformConfigurationServicesStatus : 1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
/// When set, frequency is reduced below the operating system request
/// because the processor has detected that utilization is low.
///
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;
///
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
/// below the operating system request due to a thermal alert from the
/// Voltage Regulator.
///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
+ UINT32 VRThermAlertStatus : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
/// reduced below the operating system request due to electrical design
/// point constraints (e.g. maximum electrical current consumption).
///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:1;
+ UINT32 ElectricalDesignPointStatus : 1;
+ UINT32 Reserved3 : 1;
///
/// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
/// below the operating system request due to Multi-Core Turbo limits.
///
- UINT32 MultiCoreTurboStatus:1;
- UINT32 Reserved4:2;
+ UINT32 MultiCoreTurboStatus : 1;
+ UINT32 Reserved4 : 2;
///
/// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
/// below max non-turbo P1.
///
- UINT32 FrequencyP1Status:1;
+ UINT32 FrequencyP1Status : 1;
///
/// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
/// set, frequency is reduced below max n-core turbo frequency.
///
- UINT32 TurboFrequencyLimitingStatus:1;
+ UINT32 TurboFrequencyLimitingStatus : 1;
///
/// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
/// reduced below the operating system request.
///
- UINT32 FrequencyLimitingStatus:1;
+ UINT32 FrequencyLimitingStatus : 1;
///
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 PROCHOT_Log:1;
+ UINT32 PROCHOT_Log : 1;
///
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 ThermalLog:1;
+ UINT32 ThermalLog : 1;
///
/// [Bit 18] Power Budget Management Log When set, indicates that the PBM
/// Status bit has asserted since the log bit was last cleared. This log
/// bit will remain set until cleared by software writing 0.
///
- UINT32 PowerBudgetManagementLog:1;
+ UINT32 PowerBudgetManagementLog : 1;
///
/// [Bit 19] Platform Configuration Services Log When set, indicates that
/// the PCS Status bit has asserted since the log bit was last cleared.
/// This log bit will remain set until cleared by software writing 0.
///
- UINT32 PlatformConfigurationServicesLog:1;
- UINT32 Reserved5:1;
+ UINT32 PlatformConfigurationServicesLog : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
/// indicates that the AUBFC Status bit has asserted since the log bit was
/// last cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;
///
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
/// Alert Status bit has asserted since the log bit was last cleared. This
/// log bit will remain set until cleared by software writing 0.
///
- UINT32 VRThermAlertLog:1;
- UINT32 Reserved6:1;
+ UINT32 VRThermAlertLog : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
/// Status bit has asserted since the log bit was last cleared. This log
/// bit will remain set until cleared by software writing 0.
///
- UINT32 ElectricalDesignPointLog:1;
- UINT32 Reserved7:1;
+ UINT32 ElectricalDesignPointLog : 1;
+ UINT32 Reserved7 : 1;
///
/// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
/// Turbo Status bit has asserted since the log bit was last cleared. This
/// log bit will remain set until cleared by software writing 0.
///
- UINT32 MultiCoreTurboLog:1;
- UINT32 Reserved8:2;
+ UINT32 MultiCoreTurboLog : 1;
+ UINT32 Reserved8 : 2;
///
/// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
/// Frequency P1 Status bit has asserted since the log bit was last
/// cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 CoreFrequencyP1Log:1;
+ UINT32 CoreFrequencyP1Log : 1;
///
/// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
/// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
/// has asserted since the log bit was last cleared. This log bit will
/// remain set until cleared by software writing 0.
///
- UINT32 TurboFrequencyLimitingLog:1;
+ UINT32 TurboFrequencyLimitingLog : 1;
///
/// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
/// Frequency Limiting Status bit has asserted since the log bit was last
/// cleared. This log bit will remain set until cleared by software
/// writing 0.
///
- UINT32 CoreFrequencyLimitingLog:1;
- UINT32 Reserved9:32;
+ UINT32 CoreFrequencyLimitingLog : 1;
+ UINT32 Reserved9 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;
-
/**
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
ECX=0):EBX.RDT-M[bit 12] = 1.
@@ -1018,7 +1002,7 @@ typedef union { @endcode
@note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
**/
-#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
+#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
/**
MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
@@ -1033,21 +1017,20 @@ typedef union { /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
/// Local memory bandwidth monitoring All other encoding reserved.
///
- UINT32 EventID:8;
- UINT32 Reserved1:24;
+ UINT32 EventID : 8;
+ UINT32 Reserved1 : 24;
///
/// [Bits 41:32] RMID (RW).
///
- UINT32 RMID:10;
- UINT32 Reserved2:22;
+ UINT32 RMID : 10;
+ UINT32 Reserved2 : 22;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;
-
/**
THREAD. Resource Association Register (R/W).
@@ -1066,7 +1049,7 @@ typedef union { @endcode
@note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
**/
-#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
+#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
/**
MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
@@ -1079,21 +1062,20 @@ typedef union { ///
/// [Bits 9:0] RMID.
///
- UINT32 RMID:10;
- UINT32 Reserved1:22;
+ UINT32 RMID : 10;
+ UINT32 Reserved1 : 22;
///
/// [Bits 51:32] COS (R/W).
///
- UINT32 COS:20;
- UINT32 Reserved2:12;
+ UINT32 COS : 20;
+ UINT32 Reserved2 : 12;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;
-
/**
Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
ECX=1):EDX.COS_MAX[15:0] >= n.
@@ -1129,22 +1111,22 @@ typedef union { MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
@{
**/
-#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
-#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
-#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
-#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
-#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
-#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
-#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
-#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
-#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
-#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
-#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
-#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
-#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
-#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
-#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
-#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
/// @}
/**
@@ -1159,21 +1141,20 @@ typedef union { ///
/// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
///
- UINT32 CBM:20;
- UINT32 Reserved2:12;
- UINT32 Reserved3:32;
+ UINT32 CBM : 20;
+ UINT32 Reserved2 : 12;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;
-
/**
Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
RW if MSR_PLATFORM_INFO.[28] = 1.
@@ -1192,7 +1173,7 @@ typedef union { @endcode
@note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.
**/
-#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
/**
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
@@ -1202,23 +1183,22 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:31;
+ UINT32 Reserved1 : 32;
+ UINT32 Reserved2 : 31;
///
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
/// the processor uses override configuration specified in
/// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
/// uses factory-set configuration (Default).
///
- UINT32 TurboRatioLimitConfigurationSemaphore:1;
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;
-
/**
Package. Cache Allocation Technology Configuration (R/W).
@@ -1237,7 +1217,7 @@ typedef union { @endcode
@note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
**/
-#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
+#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
/**
MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
@@ -1250,18 +1230,18 @@ typedef union { ///
/// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
///
- UINT32 CAT:1;
- UINT32 Reserved1:31;
- UINT32 Reserved2:32;
+ UINT32 CAT : 1;
+ UINT32 Reserved1 : 31;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;
#endif
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