diff options
Diffstat (limited to 'MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h')
| -rw-r--r-- | MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h | 435 |
1 files changed, 196 insertions, 239 deletions
diff --git a/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h b/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h index b4dbb52ca5..2a82f7bab1 100644 --- a/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h @@ -54,7 +54,7 @@ @endcode
@note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
**/
-#define MSR_XEON_PHI_SMI_COUNT 0x00000034
+#define MSR_XEON_PHI_SMI_COUNT 0x00000034
/**
MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
@@ -67,17 +67,17 @@ typedef union { ///
/// [Bits 31:0] SMI Count (R/O).
///
- UINT32 SMICount:32;
- UINT32 Reserved:32;
+ UINT32 SMICount : 32;
+ UINT32 Reserved : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
/**
@@ -97,7 +97,7 @@ typedef union { AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
@endcode
**/
-#define MSR_XEON_PHI_PPIN_CTL 0x0000004E
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E
/**
MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
@@ -117,28 +117,27 @@ typedef union { /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
/// prevent unauthorized modification to MSR_PPIN_CTL.
///
- UINT32 LockOut:1;
+ UINT32 LockOut : 1;
///
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
/// Default is 0.
///
- UINT32 Enable_PPIN:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 Enable_PPIN : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_PPIN_CTL_REGISTER;
-
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
Inventory Number (R/O) A unique value within a given CPUID
@@ -158,7 +157,7 @@ typedef union { Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
@endcode
**/
-#define MSR_XEON_PHI_PPIN 0x0000004F
+#define MSR_XEON_PHI_PPIN 0x0000004F
/**
Package. Platform Information Contains power management and other model
@@ -179,7 +178,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
**/
-#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
+#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
/**
MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
@@ -189,45 +188,44 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:8;
+ UINT32 Reserved1 : 8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100
/// MHz.
///
- UINT32 MaximumNonTurboRatio:8;
- UINT32 Reserved2:12;
+ UINT32 MaximumNonTurboRatio : 8;
+ UINT32 Reserved2 : 12;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
/// enabled, and when set to 0, indicates Programmable Ratio Limits for
/// Turbo mode is disabled.
///
- UINT32 RatioLimit:1;
+ UINT32 RatioLimit : 1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,
/// and when set to 0, indicates TDP Limit for Turbo mode is not
/// programmable.
///
- UINT32 TDPLimit:1;
- UINT32 Reserved3:2;
- UINT32 Reserved4:8;
+ UINT32 TDPLimit : 1;
+ UINT32 Reserved3 : 2;
+ UINT32 Reserved4 : 8;
///
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
/// minimum ratio (maximum efficiency) that the processor can operates, in
/// units of 100MHz.
///
- UINT32 MaximumEfficiencyRatio:8;
- UINT32 Reserved5:16;
+ UINT32 MaximumEfficiencyRatio : 8;
+ UINT32 Reserved5 : 16;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
-
/**
Module. C-State Configuration Control (R/W).
@@ -246,7 +244,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
-#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
/**
MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
@@ -261,49 +259,48 @@ typedef union { /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
/// Retention 011b: C6 Retention 111b: No limit.
///
- UINT32 Limit:3;
- UINT32 Reserved1:7;
+ UINT32 Limit : 3;
+ UINT32 Reserved1 : 7;
///
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).
///
- UINT32 IO_MWAIT:1;
- UINT32 Reserved2:4;
+ UINT32 IO_MWAIT : 1;
+ UINT32 Reserved2 : 4;
///
/// [Bit 15] CFG Lock (R/WO).
///
- UINT32 CFGLock:1;
- UINT32 Reserved5:10;
+ UINT32 CFGLock : 1;
+ UINT32 Reserved5 : 10;
///
/// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore
/// auto-demote information.
///
- UINT32 C1StateAutoDemotionEnable:1;
- UINT32 Reserved6:1;
+ UINT32 C1StateAutoDemotionEnable : 1;
+ UINT32 Reserved6 : 1;
///
/// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
/// Undemotion from Demoted C1.
///
- UINT32 C1StateAutoUndemotionEnable:1;
+ UINT32 C1StateAutoUndemotionEnable : 1;
///
/// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
/// Package C state demotion.
///
- UINT32 PKGC_StateAutoDemotionEnable:1;
- UINT32 Reserved7:2;
- UINT32 Reserved4:32;
+ UINT32 PKGC_StateAutoDemotionEnable : 1;
+ UINT32 Reserved7 : 2;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
-
/**
Module. Power Management IO Redirection in C-state (R/W).
@@ -322,7 +319,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
**/
-#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
/**
MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
@@ -335,27 +332,26 @@ typedef union { ///
/// [Bits 15:0] LVL_2 Base Address (R/W).
///
- UINT32 Lvl2Base:16;
+ UINT32 Lvl2Base : 16;
///
/// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
/// IO-redirection will be executed (0-127). Should be programmed based on
/// the number of LVLx registers existing in the chipset.
///
- UINT32 CStateRange:7;
- UINT32 Reserved3:9;
- UINT32 Reserved2:32;
+ UINT32 CStateRange : 7;
+ UINT32 Reserved3 : 9;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
-
/**
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
handler to handle unsuccessful read of this MSR.
@@ -375,7 +371,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
-#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
+#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
/**
MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
@@ -394,21 +390,20 @@ typedef union { /// 01b, AES instruction can be mis-configured if a privileged agent
/// unintentionally writes 11b.
///
- UINT32 AESConfiguration:2;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 AESConfiguration : 2;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
-
/**
Thread. MISC_FEATURE_ENABLES.
@@ -426,7 +421,7 @@ typedef union { AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
@endcode
**/
-#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
/**
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
@@ -436,7 +431,7 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
+ UINT32 Reserved1 : 1;
///
/// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
/// MWAIT instructions do not cause invalid-opcode exceptions when
@@ -445,18 +440,18 @@ typedef union { /// other than C0 or C1, the instruction operates as if EAX indicated the
/// C-state C1.
///
- UINT32 UserModeMonitorAndMwait:1;
- UINT32 Reserved2:30;
- UINT32 Reserved3:32;
+ UINT32 UserModeMonitorAndMwait : 1;
+ UINT32 Reserved2 : 30;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
/**
@@ -478,7 +473,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
**/
-#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
/**
MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
@@ -493,38 +488,37 @@ typedef union { /// set, that bank supports Enhanced MCA (Default all 0; does not support
/// EMCA).
///
- UINT32 BankSupport:32;
- UINT32 Reserved4:24;
+ UINT32 BankSupport : 32;
+ UINT32 Reserved4 : 24;
///
/// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
///
- UINT32 TargetedSMI:1;
+ UINT32 TargetedSMI : 1;
///
/// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
/// is supported.
///
- UINT32 SMM_CPU_SVRSTR:1;
+ UINT32 SMM_CPU_SVRSTR : 1;
///
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
/// SMM code access restriction is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 SMM_Code_Access_Chk:1;
+ UINT32 SMM_Code_Access_Chk : 1;
///
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
/// SMM long flow indicator is supported and a host-space interface
/// available to SMM handler.
///
- UINT32 Long_Flow_Indication:1;
- UINT32 Reserved3:4;
+ UINT32 Long_Flow_Indication : 1;
+ UINT32 Reserved3 : 4;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
-
/**
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -544,7 +538,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
-#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
+#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
/**
MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
@@ -557,66 +551,65 @@ typedef union { ///
/// [Bit 0] Fast-Strings Enable.
///
- UINT32 FastStrings:1;
- UINT32 Reserved1:2;
+ UINT32 FastStrings : 1;
+ UINT32 Reserved1 : 2;
///
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
/// is 1.
///
- UINT32 AutomaticThermalControlCircuit:1;
- UINT32 Reserved2:3;
+ UINT32 AutomaticThermalControlCircuit : 1;
+ UINT32 Reserved2 : 3;
///
/// [Bit 7] Performance Monitoring Available (R).
///
- UINT32 PerformanceMonitoring:1;
- UINT32 Reserved3:3;
+ UINT32 PerformanceMonitoring : 1;
+ UINT32 Reserved3 : 3;
///
/// [Bit 11] Branch Trace Storage Unavailable (RO).
///
- UINT32 BTS:1;
+ UINT32 BTS : 1;
///
/// [Bit 12] Processor Event Based Sampling Unavailable (RO).
///
- UINT32 PEBS:1;
- UINT32 Reserved4:3;
+ UINT32 PEBS : 1;
+ UINT32 Reserved4 : 3;
///
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
///
- UINT32 EIST:1;
- UINT32 Reserved5:1;
+ UINT32 EIST : 1;
+ UINT32 Reserved5 : 1;
///
/// [Bit 18] ENABLE MONITOR FSM (R/W).
///
- UINT32 MONITOR:1;
- UINT32 Reserved6:3;
+ UINT32 MONITOR : 1;
+ UINT32 Reserved6 : 3;
///
/// [Bit 22] Limit CPUID Maxval (R/W).
///
- UINT32 LimitCpuidMaxval:1;
+ UINT32 LimitCpuidMaxval : 1;
///
/// [Bit 23] xTPR Message Disable (R/W).
///
- UINT32 xTPR_Message_Disable:1;
- UINT32 Reserved7:8;
- UINT32 Reserved8:2;
+ UINT32 xTPR_Message_Disable : 1;
+ UINT32 Reserved7 : 8;
+ UINT32 Reserved8 : 2;
///
/// [Bit 34] XD Bit Disable (R/W).
///
- UINT32 XD:1;
- UINT32 Reserved9:3;
+ UINT32 XD : 1;
+ UINT32 Reserved9 : 3;
///
/// [Bit 38] Turbo Mode Disable (R/W).
///
- UINT32 TurboModeDisable:1;
- UINT32 Reserved10:25;
+ UINT32 TurboModeDisable : 1;
+ UINT32 Reserved10 : 25;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
-
/**
Package.
@@ -635,7 +628,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
**/
-#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
+#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
/**
MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
@@ -645,29 +638,28 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved1:16;
+ UINT32 Reserved1 : 16;
///
/// [Bits 23:16] Temperature Target (R).
///
- UINT32 TemperatureTarget:8;
+ UINT32 TemperatureTarget : 8;
///
/// [Bits 29:24] Target Offset (R/W).
///
- UINT32 TargetOffset:6;
- UINT32 Reserved2:2;
- UINT32 Reserved3:32;
+ UINT32 TargetOffset : 6;
+ UINT32 Reserved2 : 2;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
-
/**
Miscellaneous Feature Control (R/W).
@@ -686,7 +678,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
**/
-#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
/**
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
@@ -700,26 +692,25 @@ typedef union { /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
/// L1 data cache prefetcher.
///
- UINT32 DCUHardwarePrefetcherDisable:1;
+ UINT32 DCUHardwarePrefetcherDisable : 1;
///
/// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
/// L2 hardware prefetcher.
///
- UINT32 L2HardwarePrefetcherDisable:1;
- UINT32 Reserved1:30;
- UINT32 Reserved2:32;
+ UINT32 L2HardwarePrefetcherDisable : 1;
+ UINT32 Reserved1 : 30;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
-
/**
Shared. Offcore Response Event Select Register (R/W).
@@ -736,8 +727,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
**/
-#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
-
+#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
/**
Shared. Offcore Response Event Select Register (R/W).
@@ -755,8 +745,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
-#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
-
+#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
/**
Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
@@ -776,7 +765,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
**/
-#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
/**
MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
@@ -786,105 +775,104 @@ typedef union { /// Individual bit fields
///
struct {
- UINT32 Reserved:1;
+ UINT32 Reserved : 1;
///
/// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
/// processor cores which operates under the maximum ratio limit for group
/// 0.
///
- UINT32 MaxCoresGroup0:7;
+ UINT32 MaxCoresGroup0 : 7;
///
/// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
/// ratio limit when the number of active cores are not more than the
/// group 0 maximum core count.
///
- UINT32 MaxRatioLimitGroup0:8;
+ UINT32 MaxRatioLimitGroup0 : 8;
///
/// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
/// Group 1, which includes the specified number of additional cores plus
/// the cores in group 0, operates under the group 1 turbo max ratio limit
/// = "group 0 Max ratio limit" - "group ratio delta for group 1".
///
- UINT32 MaxIncrementalCoresGroup1:5;
+ UINT32 MaxIncrementalCoresGroup1 : 5;
///
/// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// to Group 0.
///
- UINT32 DeltaRatioGroup1:3;
+ UINT32 DeltaRatioGroup1 : 3;
///
/// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
/// Group 2, which includes the specified number of additional cores plus
/// all the cores in group 1, operates under the group 2 turbo max ratio
/// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
///
- UINT32 MaxIncrementalCoresGroup2:5;
+ UINT32 MaxIncrementalCoresGroup2 : 5;
///
/// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// for Group 1.
///
- UINT32 DeltaRatioGroup2:3;
+ UINT32 DeltaRatioGroup2 : 3;
///
/// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
/// Group 3, which includes the specified number of additional cores plus
/// all the cores in group 2, operates under the group 3 turbo max ratio
/// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
///
- UINT32 MaxIncrementalCoresGroup3:5;
+ UINT32 MaxIncrementalCoresGroup3 : 5;
///
/// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// for Group 2.
///
- UINT32 DeltaRatioGroup3:3;
+ UINT32 DeltaRatioGroup3 : 3;
///
/// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
/// Group 4, which includes the specified number of additional cores plus
/// all the cores in group 3, operates under the group 4 turbo max ratio
/// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
///
- UINT32 MaxIncrementalCoresGroup4:5;
+ UINT32 MaxIncrementalCoresGroup4 : 5;
///
/// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// for Group 3.
///
- UINT32 DeltaRatioGroup4:3;
+ UINT32 DeltaRatioGroup4 : 3;
///
/// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
/// Group 5, which includes the specified number of additional cores plus
/// all the cores in group 4, operates under the group 5 turbo max ratio
/// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
///
- UINT32 MaxIncrementalCoresGroup5:5;
+ UINT32 MaxIncrementalCoresGroup5 : 5;
///
/// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// for Group 4.
///
- UINT32 DeltaRatioGroup5:3;
+ UINT32 DeltaRatioGroup5 : 3;
///
/// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
/// Group 6, which includes the specified number of additional cores plus
/// all the cores in group 5, operates under the group 6 turbo max ratio
/// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
///
- UINT32 MaxIncrementalCoresGroup6:5;
+ UINT32 MaxIncrementalCoresGroup6 : 5;
///
/// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
/// integer specifying the ratio decrement relative to the Max ratio limit
/// for Group 5.
///
- UINT32 DeltaRatioGroup6:3;
+ UINT32 DeltaRatioGroup6 : 3;
} Bits;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
-
/**
Thread. Last Branch Record Filtering Select Register (R/W).
@@ -901,8 +889,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
**/
-#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
-
+#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
/**
MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
@@ -915,50 +902,50 @@ typedef union { ///
/// [Bit 0] CPL_EQ_0.
///
- UINT32 CPL_EQ_0:1;
+ UINT32 CPL_EQ_0 : 1;
///
/// [Bit 1] CPL_NEQ_0.
///
- UINT32 CPL_NEQ_0:1;
+ UINT32 CPL_NEQ_0 : 1;
///
/// [Bit 2] JCC.
///
- UINT32 JCC:1;
+ UINT32 JCC : 1;
///
/// [Bit 3] NEAR_REL_CALL.
///
- UINT32 NEAR_REL_CALL:1;
+ UINT32 NEAR_REL_CALL : 1;
///
/// [Bit 4] NEAR_IND_CALL.
///
- UINT32 NEAR_IND_CALL:1;
+ UINT32 NEAR_IND_CALL : 1;
///
/// [Bit 5] NEAR_RET.
///
- UINT32 NEAR_RET:1;
+ UINT32 NEAR_RET : 1;
///
/// [Bit 6] NEAR_IND_JMP.
///
- UINT32 NEAR_IND_JMP:1;
+ UINT32 NEAR_IND_JMP : 1;
///
/// [Bit 7] NEAR_REL_JMP.
///
- UINT32 NEAR_REL_JMP:1;
+ UINT32 NEAR_REL_JMP : 1;
///
/// [Bit 8] FAR_BRANCH.
///
- UINT32 FAR_BRANCH:1;
- UINT32 Reserved1:23;
- UINT32 Reserved2:32;
+ UINT32 FAR_BRANCH : 1;
+ UINT32 Reserved1 : 23;
+ UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_LBR_SELECT_REGISTER;
/**
@@ -977,8 +964,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
-#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
-
+#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
/**
Thread. Last Exception Record From Linear IP (R).
@@ -995,8 +981,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
-#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
-
+#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
/**
Thread. Last Exception Record To Linear IP (R).
@@ -1013,8 +998,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
-#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
-
+#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
/**
Thread. See Table 2-2.
@@ -1032,8 +1016,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
-#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
-
+#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
/**
Package. Note: C-state values are processor specific C-state code names,
@@ -1053,8 +1036,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
-
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
/**
Package. Package C6 Residency Counter. (R/O).
@@ -1072,8 +1054,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
-
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
/**
Package. Package C7 Residency Counter. (R/O).
@@ -1091,8 +1072,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
-
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
/**
Module. Note: C-state values are processor specific C-state code names,
@@ -1112,8 +1092,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
-
+#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
/**
Module. Module C6 Residency Counter. (R/O).
@@ -1131,8 +1110,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
-
+#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
/**
Core. Note: C-state values are processor specific C-state code names,
@@ -1152,8 +1130,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
-
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@@ -1170,8 +1147,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
**/
-#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
-
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
/**
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
@@ -1189,8 +1165,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
**/
-#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
-
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
/**
Package. Unit Multipliers used in RAPL Interfaces (R/O).
@@ -1209,7 +1184,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
**/
-#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
+#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
/**
MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
@@ -1222,35 +1197,34 @@ typedef union { ///
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
///
- UINT32 PowerUnits:4;
- UINT32 Reserved1:4;
+ UINT32 PowerUnits : 4;
+ UINT32 Reserved1 : 4;
///
/// [Bits 12:8] Package. Energy Status Units Energy related information
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
/// micro-joules).
///
- UINT32 EnergyStatusUnits:5;
- UINT32 Reserved2:3;
+ UINT32 EnergyStatusUnits : 5;
+ UINT32 Reserved2 : 3;
///
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
/// Interfaces.".
///
- UINT32 TimeUnits:4;
- UINT32 Reserved3:12;
- UINT32 Reserved4:32;
+ UINT32 TimeUnits : 4;
+ UINT32 Reserved3 : 12;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
-
/**
Package. Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
@@ -1269,8 +1243,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
**/
-#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
-
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
/**
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
@@ -1289,8 +1262,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
**/
-#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
-
+#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
/**
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
@@ -1307,8 +1279,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
**/
-#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
-
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
/**
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
@@ -1325,8 +1296,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
**/
-#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
-
+#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
/**
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
@@ -1345,8 +1315,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
**/
-#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
-
+#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
/**
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
@@ -1365,8 +1334,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
**/
-#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
-
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
/**
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -1383,8 +1351,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
-#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
-
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
@@ -1402,8 +1369,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
**/
-#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
-
+#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
/**
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
@@ -1421,8 +1387,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
**/
-#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
-
+#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
/**
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
@@ -1444,7 +1409,7 @@ typedef union { AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
@endcode
**/
-#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
/**
MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
@@ -1458,27 +1423,26 @@ typedef union { /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
/// LLC/Ring.
///
- UINT32 MAX_RATIO:7;
- UINT32 Reserved1:1;
+ UINT32 MAX_RATIO : 7;
+ UINT32 Reserved1 : 1;
///
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
/// possible ratio of the LLC/Ring.
///
- UINT32 MIN_RATIO:7;
- UINT32 Reserved2:17;
- UINT32 Reserved3:32;
+ UINT32 MIN_RATIO : 7;
+ UINT32 Reserved2 : 17;
+ UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
-
/**
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
RAPL Domains.".
@@ -1496,8 +1460,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
**/
-#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
-
+#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
@@ -1515,8 +1478,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
**/
-#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
-
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
/**
Package. Base TDP Ratio (R/O) See Table 2-24.
@@ -1533,8 +1495,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
**/
-#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
-
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
/**
Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
@@ -1551,8 +1512,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
**/
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
-
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
/**
Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
@@ -1569,8 +1529,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
**/
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
-
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
/**
Package. ConfigTDP Control (R/W) See Table 2-24.
@@ -1588,8 +1547,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
**/
-#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
-
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
/**
Package. ConfigTDP Control (R/W) See Table 2-24.
@@ -1607,8 +1565,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
**/
-#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
-
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
/**
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
@@ -1629,7 +1586,7 @@ typedef union { @endcode
@note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
**/
-#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
/**
MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
@@ -1642,32 +1599,32 @@ typedef union { ///
/// [Bit 0] PROCHOT Status (R0).
///
- UINT32 PROCHOT_Status:1;
+ UINT32 PROCHOT_Status : 1;
///
/// [Bit 1] Thermal Status (R0).
///
- UINT32 ThermalStatus:1;
- UINT32 Reserved1:4;
+ UINT32 ThermalStatus : 1;
+ UINT32 Reserved1 : 4;
///
/// [Bit 6] VR Therm Alert Status (R0).
///
- UINT32 VRThermAlertStatus:1;
- UINT32 Reserved2:1;
+ UINT32 VRThermAlertStatus : 1;
+ UINT32 Reserved2 : 1;
///
/// [Bit 8] Electrical Design Point Status (R0).
///
- UINT32 ElectricalDesignPointStatus:1;
- UINT32 Reserved3:23;
- UINT32 Reserved4:32;
+ UINT32 ElectricalDesignPointStatus : 1;
+ UINT32 Reserved3 : 23;
+ UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
- UINT32 Uint32;
+ UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
#endif
|