diff options
Diffstat (limited to 'MdePkg/Library/BaseLib/Ia32')
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/ARShiftU64.S | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S | 32 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/EnableCache.S | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c | 6 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/GccInline.c | 160 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S | 20 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/LRotU64.S | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/LShiftU64.S | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/MultU64x64.S | 20 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/RRotU64.S | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/RShiftU64.S | 4 |
11 files changed, 131 insertions, 131 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/ARShiftU64.S b/MdePkg/Library/BaseLib/Ia32/ARShiftU64.S index 9138c423fc..5e993e44b5 100644 --- a/MdePkg/Library/BaseLib/Ia32/ARShiftU64.S +++ b/MdePkg/Library/BaseLib/Ia32/ARShiftU64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -37,7 +37,7 @@ ASM_PFX(InternalMathARShiftU64): jnz L0
movl %eax, %edx
movl 4(%esp), %eax
-L0:
+L0:
shrdl %cl, %edx, %eax
sar %cl, %edx
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S b/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S index f4df094195..9ec61b134b 100644 --- a/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S +++ b/MdePkg/Library/BaseLib/Ia32/DivU64x64Remainder.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -57,22 +57,22 @@ L2: shrl %ecx
jnz L2
divl %ebx
- movl %eax, %ebx # ebx <- quotient
- movl 28(%esp), %ecx # ecx <- high dword of divisor
+ movl %eax, %ebx # ebx <- quotient
+ movl 28(%esp), %ecx # ecx <- high dword of divisor
mull 24(%esp) # edx:eax <- quotient * divisor[0..31]
- imull %ebx, %ecx # ecx <- quotient * divisor[32..63]
- addl %ecx, %edx # edx <- (quotient * divisor)[32..63]
- mov 32(%esp), %ecx # ecx <- addr for Remainder
- jc TooLarge # product > 2^64
- cmpl %edx, %edi # compare high 32 bits
- ja Correct
- jb TooLarge # product > dividend
- cmpl %eax, %esi
- jae Correct # product <= dividend
+ imull %ebx, %ecx # ecx <- quotient * divisor[32..63]
+ addl %ecx, %edx # edx <- (quotient * divisor)[32..63]
+ mov 32(%esp), %ecx # ecx <- addr for Remainder
+ jc TooLarge # product > 2^64
+ cmpl %edx, %edi # compare high 32 bits
+ ja Correct
+ jb TooLarge # product > dividend
+ cmpl %eax, %esi
+ jae Correct # product <= dividend
TooLarge:
- decl %ebx # adjust quotient by -1
- jecxz Return # return if Remainder == NULL
- sub 24(%esp), %eax
+ decl %ebx # adjust quotient by -1
+ jecxz Return # return if Remainder == NULL
+ sub 24(%esp), %eax
sbb 28(%esp), %edx # edx:eax <- (quotient - 1) * divisor
Correct:
jecxz Return
@@ -81,7 +81,7 @@ Correct: movl %esi, (%ecx)
movl %edi, 4(%ecx)
Return:
- movl %ebx, %eax # eax <- quotient
+ movl %ebx, %eax # eax <- quotient
xorl %edx, %edx # quotient is 32 bits long
pop %edi
pop %esi
diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.S b/MdePkg/Library/BaseLib/Ia32/EnableCache.S index bc3aa2fc1d..b41dd0d22a 100644 --- a/MdePkg/Library/BaseLib/Ia32/EnableCache.S +++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -15,7 +15,7 @@ #
# Abstract:
#
-# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
+# Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
# the NW bit of CR0 to 0
#
# Notes:
diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c index 7ac4af353f..9f854e1dc7 100644 --- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c +++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c @@ -1,7 +1,7 @@ /** @file
AsmFlushCacheLine function
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -37,7 +37,7 @@ AsmFlushCacheLine ( )
{
//
- // If the CPU does not support CLFLUSH instruction,
+ // If the CPU does not support CLFLUSH instruction,
// then promote flush range to flush entire cache.
//
_asm {
@@ -52,7 +52,7 @@ NoClflush: wbinvd
Done:
}
-
+
return LinearAddress;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c index f52a1fe171..05d7de3d95 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -1,7 +1,7 @@ /** @file
GCC inline implementation of BaseLib processor specific functions.
-
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -32,7 +32,7 @@ MemoryFence ( )
{
// This is a little bit of overkill and it is more about the compiler that it is
- // actually processor synchronization. This is like the _ReadWriteBarrier
+ // actually processor synchronization. This is like the _ReadWriteBarrier
// Microsoft specific intrinsic
__asm__ __volatile__ ("":::"memory");
}
@@ -65,7 +65,7 @@ EFIAPI DisableInterrupts (
VOID
)
-{
+{
__asm__ __volatile__ ("cli"::: "memory");
}
@@ -128,13 +128,13 @@ AsmReadMsr64 ( )
{
UINT64 Data;
-
+
__asm__ __volatile__ (
"rdmsr"
: "=A" (Data) // %0
: "c" (Index) // %1
);
-
+
return Data;
}
@@ -168,7 +168,7 @@ AsmWriteMsr64 ( : "c" (Index),
"A" (Value)
);
-
+
return Value;
}
@@ -191,13 +191,13 @@ AsmReadEflags ( )
{
UINTN Eflags;
-
+
__asm__ __volatile__ (
"pushfl \n\t"
"popl %0 "
: "=r" (Eflags)
);
-
+
return Eflags;
}
@@ -220,12 +220,12 @@ AsmReadCr0 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
- "movl %%cr0,%0"
+ "movl %%cr0,%0"
: "=a" (Data)
);
-
+
return Data;
}
@@ -247,12 +247,12 @@ AsmReadCr2 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
- "movl %%cr2, %0"
+ "movl %%cr2, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -273,12 +273,12 @@ AsmReadCr3 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%cr3, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -300,12 +300,12 @@ AsmReadCr4 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%cr4, %0"
: "=a" (Data)
);
-
+
return Data;
}
@@ -431,12 +431,12 @@ AsmReadDr0 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr0, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -458,12 +458,12 @@ AsmReadDr1 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr1, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -485,12 +485,12 @@ AsmReadDr2 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr2, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -512,12 +512,12 @@ AsmReadDr3 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr3, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -539,12 +539,12 @@ AsmReadDr4 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr4, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -566,12 +566,12 @@ AsmReadDr5 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr5, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -593,12 +593,12 @@ AsmReadDr6 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr6, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -620,12 +620,12 @@ AsmReadDr7 ( )
{
UINTN Data;
-
+
__asm__ __volatile__ (
"movl %%dr7, %0"
: "=r" (Data)
);
-
+
return Data;
}
@@ -854,12 +854,12 @@ AsmReadCs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%cs, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -880,12 +880,12 @@ AsmReadDs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%ds, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -906,12 +906,12 @@ AsmReadEs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%es, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -932,12 +932,12 @@ AsmReadFs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%fs, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -958,12 +958,12 @@ AsmReadGs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%gs, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -984,12 +984,12 @@ AsmReadSs ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"mov %%ds, %0"
:"=a" (Data)
);
-
+
return Data;
}
@@ -1010,12 +1010,12 @@ AsmReadTr ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"str %0"
: "=a" (Data)
);
-
+
return Data;
}
@@ -1062,7 +1062,7 @@ InternalX86WriteGdtr ( :
: "m" (*Gdtr)
);
-
+
}
@@ -1127,12 +1127,12 @@ AsmReadLdtr ( )
{
UINT16 Data;
-
+
__asm__ __volatile__ (
"sldt %0"
: "=g" (Data) // %0
);
-
+
return Data;
}
@@ -1180,7 +1180,7 @@ InternalX86FxSave ( "fxsave %0"
:
: "m" (*Buffer) // %0
- );
+ );
}
@@ -1233,7 +1233,7 @@ AsmReadMm0 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1263,7 +1263,7 @@ AsmReadMm1 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1293,7 +1293,7 @@ AsmReadMm2 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1323,7 +1323,7 @@ AsmReadMm3 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1353,7 +1353,7 @@ AsmReadMm4 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1383,7 +1383,7 @@ AsmReadMm5 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1413,7 +1413,7 @@ AsmReadMm6 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1443,7 +1443,7 @@ AsmReadMm7 ( "pop %%edx \n\t"
: "=A" (Data) // %0
);
-
+
return Data;
}
@@ -1465,7 +1465,7 @@ AsmWriteMm0 ( {
__asm__ __volatile__ (
"movq %0, %%mm0" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1488,7 +1488,7 @@ AsmWriteMm1 ( {
__asm__ __volatile__ (
"movq %0, %%mm1" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1511,7 +1511,7 @@ AsmWriteMm2 ( {
__asm__ __volatile__ (
"movq %0, %%mm2" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1534,7 +1534,7 @@ AsmWriteMm3 ( {
__asm__ __volatile__ (
"movq %0, %%mm3" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1557,7 +1557,7 @@ AsmWriteMm4 ( {
__asm__ __volatile__ (
"movq %0, %%mm4" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1580,7 +1580,7 @@ AsmWriteMm5 ( {
__asm__ __volatile__ (
"movq %0, %%mm5" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1603,7 +1603,7 @@ AsmWriteMm6 ( {
__asm__ __volatile__ (
"movq %0, %%mm6" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1626,7 +1626,7 @@ AsmWriteMm7 ( {
__asm__ __volatile__ (
"movq %0, %%mm7" // %0
- :
+ :
: "m" (Value)
);
}
@@ -1648,13 +1648,13 @@ AsmReadTsc ( )
{
UINT64 Data;
-
+
__asm__ __volatile__ (
"rdtsc"
: "=A" (Data)
);
-
- return Data;
+
+ return Data;
}
@@ -1676,14 +1676,14 @@ AsmReadPmc ( )
{
UINT64 Data;
-
+
__asm__ __volatile__ (
"rdpmc"
: "=A" (Data)
: "c" (Index)
);
-
- return Data;
+
+ return Data;
}
@@ -1720,7 +1720,7 @@ AsmInvd ( )
{
__asm__ __volatile__ ("invd":::"memory");
-
+
}
@@ -1748,7 +1748,7 @@ AsmFlushCacheLine ( UINT32 RegEdx;
//
- // If the CPU does not support CLFLUSH instruction,
+ // If the CPU does not support CLFLUSH instruction,
// then promote flush range to flush entire cache.
//
AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
@@ -1760,11 +1760,11 @@ AsmFlushCacheLine ( __asm__ __volatile__ (
"clflush (%0)"
- : "+a" (LinearAddress)
- :
+ : "+a" (LinearAddress)
+ :
: "memory"
);
-
+
return LinearAddress;
}
diff --git a/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S b/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S index dc0cbd4834..027379efd7 100644 --- a/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S +++ b/MdePkg/Library/BaseLib/Ia32/InternalSwitchStack.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2011, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -34,15 +34,15 @@ ASM_GLOBAL ASM_PFX(InternalSwitchStack) #------------------------------------------------------------------------------
ASM_PFX(InternalSwitchStack):
pushl %ebp
- movl %esp, %ebp
+ movl %esp, %ebp
- movl 20(%ebp), %esp # switch stack
- subl $8, %esp
+ movl 20(%ebp), %esp # switch stack
+ subl $8, %esp
- movl 16(%ebp), %eax
- movl %eax, 4(%esp)
- movl 12(%ebp), %eax
- movl %eax, (%esp)
- pushl $0 # keeps gdb from unwinding stack
- jmp *8(%ebp) # call and never return
+ movl 16(%ebp), %eax
+ movl %eax, 4(%esp)
+ movl 12(%ebp), %eax
+ movl %eax, (%esp)
+ pushl $0 # keeps gdb from unwinding stack
+ jmp *8(%ebp) # call and never return
diff --git a/MdePkg/Library/BaseLib/Ia32/LRotU64.S b/MdePkg/Library/BaseLib/Ia32/LRotU64.S index ff450fa1f5..accac8b89d 100644 --- a/MdePkg/Library/BaseLib/Ia32/LRotU64.S +++ b/MdePkg/Library/BaseLib/Ia32/LRotU64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -43,6 +43,6 @@ ASM_PFX(InternalMathLRotU64): movl %eax, %ecx
movl %edx, %eax
movl %ecx, %edx
-L0:
+L0:
pop %ebx
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/LShiftU64.S b/MdePkg/Library/BaseLib/Ia32/LShiftU64.S index dcdbeae1d7..90baed001c 100644 --- a/MdePkg/Library/BaseLib/Ia32/LShiftU64.S +++ b/MdePkg/Library/BaseLib/Ia32/LShiftU64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -37,7 +37,7 @@ ASM_PFX(InternalMathLShiftU64): jnz L0
movl %edx, %eax
movl 0x8(%esp), %edx
-L0:
+L0:
shld %cl, %eax, %edx
shl %cl, %eax
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/MultU64x64.S b/MdePkg/Library/BaseLib/Ia32/MultU64x64.S index 48f4ae037e..4e4fe710a7 100644 --- a/MdePkg/Library/BaseLib/Ia32/MultU64x64.S +++ b/MdePkg/Library/BaseLib/Ia32/MultU64x64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -30,15 +30,15 @@ ASM_GLOBAL ASM_PFX(InternalMathMultU64x64) # );
#------------------------------------------------------------------------------
ASM_PFX(InternalMathMultU64x64):
- push %ebx
- movl 8(%esp), %ebx # ebx <- M1[0..31]
- movl 16(%esp), %edx # edx <- M2[0..31]
- movl %ebx, %ecx
- movl %edx, %eax
- imull 20(%esp), %ebx # ebx <- M1[0..31] * M2[32..63]
- imull 12(%esp), %edx # edx <- M1[32..63] * M2[0..31]
- addl %edx, %ebx # carries are abandoned
+ push %ebx
+ movl 8(%esp), %ebx # ebx <- M1[0..31]
+ movl 16(%esp), %edx # edx <- M2[0..31]
+ movl %ebx, %ecx
+ movl %edx, %eax
+ imull 20(%esp), %ebx # ebx <- M1[0..31] * M2[32..63]
+ imull 12(%esp), %edx # edx <- M1[32..63] * M2[0..31]
+ addl %edx, %ebx # carries are abandoned
mull %ecx # edx:eax <- M1[0..31] * M2[0..31]
- addl %ebx, %edx # carries are abandoned
+ addl %ebx, %edx # carries are abandoned
pop %ebx
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/RRotU64.S b/MdePkg/Library/BaseLib/Ia32/RRotU64.S index f42f450189..426fcd6de3 100644 --- a/MdePkg/Library/BaseLib/Ia32/RRotU64.S +++ b/MdePkg/Library/BaseLib/Ia32/RRotU64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -43,6 +43,6 @@ ASM_PFX(InternalMathRRotU64): movl %eax, %ecx # switch eax & edx if Count >= 32
movl %edx, %eax
movl %ecx, %edx
-L0:
+L0:
pop %ebx
ret
diff --git a/MdePkg/Library/BaseLib/Ia32/RShiftU64.S b/MdePkg/Library/BaseLib/Ia32/RShiftU64.S index 0bf9292281..28102303f2 100644 --- a/MdePkg/Library/BaseLib/Ia32/RShiftU64.S +++ b/MdePkg/Library/BaseLib/Ia32/RShiftU64.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------
#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -40,7 +40,7 @@ ASM_PFX(InternalMathRShiftU64): jnz L0
movl %eax, %edx
movl 0x4(%esp), %eax
-L0:
+L0:
shrdl %cl, %edx, %eax
shr %cl, %edx
ret
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