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Diffstat (limited to 'MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c')
-rw-r--r--MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c b/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
index 60f5c7f36b..50ffe8e3aa 100644
--- a/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
+++ b/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
@@ -1,7 +1,7 @@
/** @file
Internal function to get spin lock alignment.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -19,7 +19,7 @@
requirements for optimal spin lock performance.
@return The architecture specific spin lock alignment.
-
+
**/
UINTN
InternalGetSpinLockProperties (
@@ -48,7 +48,7 @@ InternalGetSpinLockProperties (
if (FamilyId == 0x0f) {
//
// In processors based on Intel NetBurst microarchitecture, use two cache lines
- //
+ //
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
if (ModelId <= 0x04 || ModelId == 0x06) {
CacheLineSize *= 2;