diff options
Diffstat (limited to 'OvmfPkg/Bhyve/PlatformPei/MemDetect.c')
| -rw-r--r-- | OvmfPkg/Bhyve/PlatformPei/MemDetect.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/OvmfPkg/Bhyve/PlatformPei/MemDetect.c b/OvmfPkg/Bhyve/PlatformPei/MemDetect.c index 1949e586a0..29cbb9e3dc 100644 --- a/OvmfPkg/Bhyve/PlatformPei/MemDetect.c +++ b/OvmfPkg/Bhyve/PlatformPei/MemDetect.c @@ -58,7 +58,7 @@ Q35TsegMbytesInitialization ( DEBUG_ERROR,
"%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
"only DID=0x%04x (Q35) is supported\n",
- __FUNCTION__,
+ __func__,
mHostBridgeDevId,
INTEL_Q35_MCH_DEVICE_ID
));
@@ -92,7 +92,7 @@ Q35TsegMbytesInitialization ( DEBUG ((
DEBUG_INFO,
"%a: QEMU offers an extended TSEG (%d MB)\n",
- __FUNCTION__,
+ __func__,
ExtendedTsegMbytes
));
PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
@@ -185,7 +185,7 @@ GetFirstNonAddress ( DEBUG ((
DEBUG_INFO,
"%a: disabling 64-bit PCI host aperture\n",
- __FUNCTION__
+ __func__
));
PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
ASSERT_RETURN_ERROR (PcdStatus);
@@ -228,7 +228,7 @@ GetFirstNonAddress ( DEBUG ((
DEBUG_INFO,
"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
- __FUNCTION__,
+ __func__,
Pci64Base,
Pci64Size
));
@@ -392,7 +392,7 @@ PublishPeiMemory ( DEBUG ((
DEBUG_INFO,
"%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
- __FUNCTION__,
+ __func__,
mPhysMemAddressWidth,
PeiMemoryCap >> 10
));
@@ -441,7 +441,7 @@ QemuInitializeRam ( MTRR_SETTINGS MtrrSettings;
EFI_STATUS Status;
- DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a called\n", __func__));
//
// Determine total memory size available
|