diff options
Diffstat (limited to 'OvmfPkg/PlatformPei/Platform.c')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 242 |
1 files changed, 135 insertions, 107 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index df2d9ad015..3000176efd 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -40,7 +40,7 @@ #include "Platform.h"
#include "Cmos.h"
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMasterBootModePpiGuid,
@@ -48,27 +48,26 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = { }
};
+UINT16 mHostBridgeDevId;
-UINT16 mHostBridgeDevId;
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+BOOLEAN mS3Supported = FALSE;
-BOOLEAN mS3Supported = FALSE;
-
-UINT32 mMaxCpuCount;
+UINT32 mMaxCpuCount;
VOID
AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -76,23 +75,23 @@ AddIoMemoryBaseSizeHob ( VOID
AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize,
- BOOLEAN Cacheable
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize,
+ BOOLEAN Cacheable
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- (Cacheable ?
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
- 0
- ) |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ (Cacheable ?
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
+ 0
+ ) |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
@@ -100,57 +99,54 @@ AddReservedMemoryBaseSizeHob ( VOID
AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-
VOID
AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
MemoryBase,
MemorySize
);
}
-
VOID
AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
)
{
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-
VOID
MemMapInitialization (
VOID
)
{
- UINT64 PciIoBase;
- UINT64 PciIoSize;
- RETURN_STATUS PcdStatus;
- UINT32 TopOfLowRam;
- UINT64 PciExBarBase;
- UINT32 PciBase;
- UINT32 PciSize;
+ UINT64 PciIoBase;
+ UINT64 PciIoSize;
+ RETURN_STATUS PcdStatus;
+ UINT32 TopOfLowRam;
+ UINT64 PciExBarBase;
+ UINT32 PciBase;
+ UINT32 PciSize;
PciIoBase = 0xC000;
PciIoSize = 0x4000;
@@ -167,7 +163,7 @@ MemMapInitialization ( return;
}
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();
PciExBarBase = 0;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
@@ -229,10 +225,14 @@ MemMapInitialization ( // uncacheable reserved memory right here.
//
AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
- BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
- EfiReservedMemoryType);
+ BuildMemoryAllocationHob (
+ PciExBarBase,
+ SIZE_256MB,
+ EfiReservedMemoryType
+ );
}
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);
//
// On Q35, the IO Port space is available for PCI resource allocations from
@@ -286,8 +286,8 @@ PciExBarInitialization ( )
{
union {
- UINT64 Uint64;
- UINT32 Uint32[2];
+ UINT64 Uint64;
+ UINT32 Uint32[2];
} PciExBarBase;
//
@@ -326,13 +326,13 @@ MiscInitialization ( VOID
)
{
- UINTN PmCmd;
- UINTN Pmba;
- UINT32 PmbaAndVal;
- UINT32 PmbaOrVal;
- UINTN AcpiCtlReg;
- UINT8 AcpiEnBit;
- RETURN_STATUS PcdStatus;
+ UINTN PmCmd;
+ UINTN Pmba;
+ UINT32 PmbaAndVal;
+ UINT32 PmbaOrVal;
+ UINTN AcpiCtlReg;
+ UINT8 AcpiEnBit;
+ RETURN_STATUS PcdStatus;
//
// Disable A20 Mask
@@ -368,16 +368,23 @@ MiscInitialization ( break;
case 0xffff: /* microvm */
DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId,
- MICROVM_PSEUDO_DEVICE_ID);
+ PcdStatus = PcdSet16S (
+ PcdOvmfHostBridgePciDevId,
+ MICROVM_PSEUDO_DEVICE_ID
+ );
ASSERT_RETURN_ERROR (PcdStatus);
return;
default:
- DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
- __FUNCTION__, mHostBridgeDevId));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Unknown Host Bridge Device ID: 0x%04x\n",
+ __FUNCTION__,
+ mHostBridgeDevId
+ ));
ASSERT (FALSE);
return;
}
+
PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
ASSERT_RETURN_ERROR (PcdStatus);
@@ -420,17 +427,17 @@ MiscInitialization ( }
}
-
VOID
BootModeInitialization (
VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (CmosRead8 (0xF) == 0xFE) {
mBootMode = BOOT_ON_S3_RESUME;
}
+
CmosWrite8 (0xF, 0x00);
Status = PeiServicesSetBootMode (mBootMode);
@@ -440,13 +447,12 @@ BootModeInitialization ( ASSERT_EFI_ERROR (Status);
}
-
VOID
ReserveEmuVariableNvStore (
)
{
- EFI_PHYSICAL_ADDRESS VariableStore;
- RETURN_STATUS PcdStatus;
+ EFI_PHYSICAL_ADDRESS VariableStore;
+ RETURN_STATUS PcdStatus;
//
// Allocate storage for NV variables early on so it will be
@@ -456,25 +462,25 @@ ReserveEmuVariableNvStore ( //
VariableStore =
(EFI_PHYSICAL_ADDRESS)(UINTN)
- AllocateRuntimePages (
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
- );
- DEBUG ((DEBUG_INFO,
- "Reserved variable store memory: 0x%lX; size: %dkb\n",
- VariableStore,
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
- ));
+ AllocateRuntimePages (
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
+ );
+ DEBUG ((
+ DEBUG_INFO,
+ "Reserved variable store memory: 0x%lX; size: %dkb\n",
+ VariableStore,
+ (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
+ ));
PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
ASSERT_RETURN_ERROR (PcdStatus);
}
-
VOID
DebugDumpCmos (
VOID
)
{
- UINT32 Loop;
+ UINT32 Loop;
DEBUG ((DEBUG_INFO, "CMOS:\n"));
@@ -482,6 +488,7 @@ DebugDumpCmos ( if ((Loop % 0x10) == 0) {
DEBUG ((DEBUG_INFO, "%02x:", Loop));
}
+
DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
if ((Loop % 0x10) == 0xf) {
DEBUG ((DEBUG_INFO, "\n"));
@@ -489,27 +496,34 @@ DebugDumpCmos ( }
}
-
VOID
S3Verification (
VOID
)
{
-#if defined (MDE_CPU_X64)
+ #if defined (MDE_CPU_X64)
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
- DEBUG ((DEBUG_ERROR,
- "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",
+ __FUNCTION__
+ ));
+ DEBUG ((
+ DEBUG_ERROR,
"%a: Please disable S3 on the QEMU command line (see the README),\n",
- __FUNCTION__));
- DEBUG ((DEBUG_ERROR,
- "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
+ __FUNCTION__
+ ));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",
+ __FUNCTION__
+ ));
ASSERT (FALSE);
CpuDeadLoop ();
}
-#endif
-}
+ #endif
+}
VOID
Q35BoardVerification (
@@ -532,7 +546,6 @@ Q35BoardVerification ( CpuDeadLoop ();
}
-
/**
Fetch the boot CPU count and the possible CPU count from QEMU, and expose
them to UefiCpuPkg modules. Set the mMaxCpuCount variable.
@@ -542,8 +555,8 @@ MaxCpuCountInitialization ( VOID
)
{
- UINT16 BootCpuCount;
- RETURN_STATUS PcdStatus;
+ UINT16 BootCpuCount;
+ RETURN_STATUS PcdStatus;
//
// Try to fetch the boot CPU count.
@@ -566,8 +579,8 @@ MaxCpuCountInitialization ( //
// Now try to fetch the possible CPU count.
//
- UINTN CpuHpBase;
- UINT32 CmdData2;
+ UINTN CpuHpBase;
+ UINT32 CmdData2;
CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?
ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);
@@ -616,16 +629,19 @@ MaxCpuCountInitialization ( // QEMU doesn't support the modern CPU hotplug interface. Assume that the
// possible CPU count equals the boot CPU count (precluding hotplug).
//
- DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: modern CPU hotplug interface unavailable\n",
+ __FUNCTION__
+ ));
mMaxCpuCount = BootCpuCount;
} else {
//
// Grab the possible CPU count from the modern CPU hotplug interface.
//
- UINT32 Present, Possible, Selected;
+ UINT32 Present, Possible, Selected;
- Present = 0;
+ Present = 0;
Possible = 0;
//
@@ -637,7 +653,7 @@ MaxCpuCountInitialization ( IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);
do {
- UINT8 CpuStatus;
+ UINT8 CpuStatus;
//
// Read the status of the currently selected CPU. This will help with a
@@ -647,6 +663,7 @@ MaxCpuCountInitialization ( if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {
++Present;
}
+
//
// Attempt to select the next CPU.
//
@@ -666,8 +683,14 @@ MaxCpuCountInitialization ( // return the same boot CPU count.
//
if (BootCpuCount != Present) {
- DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
- "Present=%u\n", __FUNCTION__, BootCpuCount, Present));
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: QEMU v2.7 reset bug: BootCpuCount=%d "
+ "Present=%u\n",
+ __FUNCTION__,
+ BootCpuCount,
+ Present
+ ));
//
// The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus
// platform reset (including S3), was corrected in QEMU commit
@@ -681,8 +704,13 @@ MaxCpuCountInitialization ( }
}
- DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,
- BootCpuCount, mMaxCpuCount));
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: BootCpuCount=%d mMaxCpuCount=%u\n",
+ __FUNCTION__,
+ BootCpuCount,
+ mMaxCpuCount
+ ));
ASSERT (BootCpuCount <= mMaxCpuCount);
PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
@@ -691,7 +719,6 @@ MaxCpuCountInitialization ( ASSERT_RETURN_ERROR (PcdStatus);
}
-
/**
Perform Platform PEI initialization.
@@ -708,7 +735,7 @@ InitializePlatform ( IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
@@ -717,7 +744,7 @@ InitializePlatform ( if (QemuFwCfgS3Enabled ()) {
DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
mS3Supported = TRUE;
- Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
ASSERT_EFI_ERROR (Status);
}
@@ -748,6 +775,7 @@ InitializePlatform ( if (!FeaturePcdGet (PcdSmmSmramRequire)) {
ReserveEmuVariableNvStore ();
}
+
PeiFvInitialization ();
MemTypeInfoInitialization ();
MemMapInitialization ();
|