summaryrefslogtreecommitdiffstats
path: root/OvmfPkg/SmmAccess
diff options
context:
space:
mode:
Diffstat (limited to 'OvmfPkg/SmmAccess')
-rw-r--r--OvmfPkg/SmmAccess/SmmAccess2Dxe.c23
-rw-r--r--OvmfPkg/SmmAccess/SmmAccessPei.c168
-rw-r--r--OvmfPkg/SmmAccess/SmramInternal.c63
-rw-r--r--OvmfPkg/SmmAccess/SmramInternal.h26
4 files changed, 169 insertions, 111 deletions
diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c b/OvmfPkg/SmmAccess/SmmAccess2Dxe.c
index 3691a6cd1f..4b9e6df37f 100644
--- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c
+++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.c
@@ -114,14 +114,18 @@ SmmAccess2DxeGetCapabilities (
IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
)
{
- return SmramAccessGetCapabilities (This->LockState, This->OpenState,
- SmramMapSize, SmramMap);
+ return SmramAccessGetCapabilities (
+ This->LockState,
+ This->OpenState,
+ SmramMapSize,
+ SmramMap
+ );
}
//
// LockState and OpenState will be filled in by the entry point.
//
-STATIC EFI_SMM_ACCESS2_PROTOCOL mAccess2 = {
+STATIC EFI_SMM_ACCESS2_PROTOCOL mAccess2 = {
&SmmAccess2DxeOpen,
&SmmAccess2DxeClose,
&SmmAccess2DxeLock,
@@ -134,8 +138,8 @@ STATIC EFI_SMM_ACCESS2_PROTOCOL mAccess2 = {
EFI_STATUS
EFIAPI
SmmAccess2DxeEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
//
@@ -152,7 +156,10 @@ SmmAccess2DxeEntryPoint (
//
InitQ35SmramAtDefaultSmbase ();
- return gBS->InstallMultipleProtocolInterfaces (&ImageHandle,
- &gEfiSmmAccess2ProtocolGuid, &mAccess2,
- NULL);
+ return gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiSmmAccess2ProtocolGuid,
+ &mAccess2,
+ NULL
+ );
}
diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c
index ec4e9a2761..4be5f2423e 100644
--- a/OvmfPkg/SmmAccess/SmmAccessPei.c
+++ b/OvmfPkg/SmmAccess/SmmAccessPei.c
@@ -59,9 +59,9 @@ STATIC
EFI_STATUS
EFIAPI
SmmAccessPeiOpen (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_SMM_ACCESS_PPI *This,
- IN UINTN DescriptorIndex
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
)
{
if (DescriptorIndex >= DescIdxCount) {
@@ -97,9 +97,9 @@ STATIC
EFI_STATUS
EFIAPI
SmmAccessPeiClose (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_SMM_ACCESS_PPI *This,
- IN UINTN DescriptorIndex
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
)
{
if (DescriptorIndex >= DescIdxCount) {
@@ -134,9 +134,9 @@ STATIC
EFI_STATUS
EFIAPI
SmmAccessPeiLock (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_SMM_ACCESS_PPI *This,
- IN UINTN DescriptorIndex
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
)
{
if (DescriptorIndex >= DescIdxCount) {
@@ -171,42 +171,44 @@ STATIC
EFI_STATUS
EFIAPI
SmmAccessPeiGetCapabilities (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_SMM_ACCESS_PPI *This,
- IN OUT UINTN *SmramMapSize,
- IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_ACCESS_PPI *This,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
)
{
- return SmramAccessGetCapabilities (This->LockState, This->OpenState,
- SmramMapSize, SmramMap);
+ return SmramAccessGetCapabilities (
+ This->LockState,
+ This->OpenState,
+ SmramMapSize,
+ SmramMap
+ );
}
//
// LockState and OpenState will be filled in by the entry point.
//
-STATIC PEI_SMM_ACCESS_PPI mAccess = {
+STATIC PEI_SMM_ACCESS_PPI mAccess = {
&SmmAccessPeiOpen,
&SmmAccessPeiClose,
&SmmAccessPeiLock,
&SmmAccessPeiGetCapabilities
};
-
-STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
+STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gPeiSmmAccessPpiGuid, &mAccess
}
};
-
//
// Utility functions.
//
STATIC
UINT8
CmosRead8 (
- IN UINT8 Index
+ IN UINT8 Index
)
{
IoWrite8 (0x70, Index);
@@ -219,8 +221,8 @@ GetSystemMemorySizeBelow4gb (
VOID
)
{
- UINT32 Cmos0x34;
- UINT32 Cmos0x35;
+ UINT32 Cmos0x34;
+ UINT32 Cmos0x35;
Cmos0x34 = CmosRead8 (0x34);
Cmos0x35 = CmosRead8 (0x35);
@@ -228,7 +230,6 @@ GetSystemMemorySizeBelow4gb (
return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;
}
-
//
// Entry point of this driver.
//
@@ -239,14 +240,14 @@ SmmAccessPeiEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- UINT16 HostBridgeDevId;
- UINT8 EsmramcVal;
- UINT8 RegMask8;
- UINT32 TopOfLowRam, TopOfLowRamMb;
- EFI_STATUS Status;
- UINTN SmramMapSize;
- EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];
- VOID *GuidHob;
+ UINT16 HostBridgeDevId;
+ UINT8 EsmramcVal;
+ UINT8 RegMask8;
+ UINT32 TopOfLowRam, TopOfLowRamMb;
+ EFI_STATUS Status;
+ UINTN SmramMapSize;
+ EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];
+ VOID *GuidHob;
//
// This module should only be included if SMRAM support is required.
@@ -258,9 +259,14 @@ SmmAccessPeiEntryPoint (
//
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
- DEBUG ((DEBUG_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "
- "DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,
- INTEL_Q35_MCH_DEVICE_ID));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: no SMRAM with host bridge DID=0x%04x; only "
+ "DID=0x%04x (Q35) is supported\n",
+ __FUNCTION__,
+ HostBridgeDevId,
+ INTEL_Q35_MCH_DEVICE_ID
+ ));
goto WrongConfig;
}
@@ -272,10 +278,13 @@ SmmAccessPeiEntryPoint (
// bits are hard-coded as 1 by QEMU.
//
EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
- RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;
+ RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;
if ((EsmramcVal & RegMask8) != RegMask8) {
- DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMRAM\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: this Q35 implementation lacks SMRAM\n",
+ __FUNCTION__
+ ));
goto WrongConfig;
}
@@ -297,24 +306,32 @@ SmmAccessPeiEntryPoint (
//
// Set Top of Low Usable DRAM.
//
- PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),
- (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));
+ PciWrite16 (
+ DRAMC_REGISTER_Q35 (MCH_TOLUD),
+ (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT)
+ );
//
// Given the zero graphics memory sizes configured above, set the
// graphics-related stolen memory bases to the same as TOLUD.
//
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),
- TopOfLowRamMb << MCH_GBSM_MB_SHIFT);
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),
- TopOfLowRamMb << MCH_BGSM_MB_SHIFT);
+ PciWrite32 (
+ DRAMC_REGISTER_Q35 (MCH_GBSM),
+ TopOfLowRamMb << MCH_GBSM_MB_SHIFT
+ );
+ PciWrite32 (
+ DRAMC_REGISTER_Q35 (MCH_BGSM),
+ TopOfLowRamMb << MCH_BGSM_MB_SHIFT
+ );
//
// Set TSEG Memory Base.
//
InitQ35TsegMbytes ();
- PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),
- (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);
+ PciWrite32 (
+ DRAMC_REGISTER_Q35 (MCH_TSEGMB),
+ (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT
+ );
//
// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the
@@ -333,44 +350,71 @@ SmmAccessPeiEntryPoint (
// TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME
// (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.
//
- PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),
- (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);
+ PciAndThenOr8 (
+ DRAMC_REGISTER_Q35 (MCH_SMRAM),
+ (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff),
+ MCH_SMRAM_G_SMRAME
+ );
//
// Create the GUID HOB and point it to the first SMRAM range.
//
GetStates (&mAccess.LockState, &mAccess.OpenState);
SmramMapSize = sizeof SmramMap;
- Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,
- &SmramMapSize, SmramMap);
+ Status = SmramAccessGetCapabilities (
+ mAccess.LockState,
+ mAccess.OpenState,
+ &SmramMapSize,
+ SmramMap
+ );
ASSERT_EFI_ERROR (Status);
DEBUG_CODE_BEGIN ();
{
- UINTN Count;
- UINTN Idx;
+ UINTN Count;
+ UINTN Idx;
Count = SmramMapSize / sizeof SmramMap[0];
- DEBUG ((DEBUG_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,
- (INT32)Count));
- DEBUG ((DEBUG_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",
- "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: SMRAM map follows, %d entries\n",
+ __FUNCTION__,
+ (INT32)Count
+ ));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "% 20a % 20a % 20a % 20a\n",
+ "PhysicalStart(0x)",
+ "PhysicalSize(0x)",
+ "CpuStart(0x)",
+ "RegionState(0x)"
+ ));
for (Idx = 0; Idx < Count; ++Idx) {
- DEBUG ((DEBUG_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",
- SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,
- SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "% 20Lx % 20Lx % 20Lx % 20Lx\n",
+ SmramMap[Idx].PhysicalStart,
+ SmramMap[Idx].PhysicalSize,
+ SmramMap[Idx].CpuStart,
+ SmramMap[Idx].RegionState
+ ));
}
}
DEBUG_CODE_END ();
- GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,
- sizeof SmramMap[DescIdxSmmS3ResumeState]);
+ GuidHob = BuildGuidHob (
+ &gEfiAcpiVariableGuid,
+ sizeof SmramMap[DescIdxSmmS3ResumeState]
+ );
if (GuidHob == NULL) {
return EFI_OUT_OF_RESOURCES;
}
- CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],
- sizeof SmramMap[DescIdxSmmS3ResumeState]);
+ CopyMem (
+ GuidHob,
+ &SmramMap[DescIdxSmmS3ResumeState],
+ sizeof SmramMap[DescIdxSmmS3ResumeState]
+ );
//
// SmramAccessLock() depends on "mQ35SmramAtDefaultSmbase"; init the latter
diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c
index 0b07dc667b..d391ddc9ae 100644
--- a/OvmfPkg/SmmAccess/SmramInternal.c
+++ b/OvmfPkg/SmmAccess/SmramInternal.c
@@ -19,13 +19,13 @@
//
// The value of PcdQ35TsegMbytes is saved into this variable at module startup.
//
-UINT16 mQ35TsegMbytes;
+UINT16 mQ35TsegMbytes;
//
// The value of PcdQ35SmramAtDefaultSmbase is saved into this variable at
// module startup.
//
-STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
+STATIC BOOLEAN mQ35SmramAtDefaultSmbase;
/**
Save PcdQ35TsegMbytes into mQ35TsegMbytes.
@@ -65,11 +65,11 @@ InitQ35SmramAtDefaultSmbase (
**/
VOID
GetStates (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
-)
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
+ )
{
- UINT8 SmramVal, EsmramcVal;
+ UINT8 SmramVal, EsmramcVal;
SmramVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));
EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
@@ -91,27 +91,30 @@ GetStates (
EFI_STATUS
SmramAccessOpen (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
)
{
//
// Open TSEG by clearing T_EN.
//
- PciAnd8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
- (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff));
+ PciAnd8 (
+ DRAMC_REGISTER_Q35 (MCH_ESMRAMC),
+ (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff)
+ );
GetStates (LockState, OpenState);
if (!*OpenState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessClose (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
)
{
//
@@ -123,13 +126,14 @@ SmramAccessClose (
if (*OpenState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessLock (
- OUT BOOLEAN *LockState,
- IN OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ IN OUT BOOLEAN *OpenState
)
{
if (*OpenState) {
@@ -140,35 +144,38 @@ SmramAccessLock (
// Close & lock TSEG by setting T_EN and D_LCK.
//
PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);
- PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
+ PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM), MCH_SMRAM_D_LCK);
//
// Close & lock the SMRAM at the default SMBASE, if it exists.
//
if (mQ35SmramAtDefaultSmbase) {
- PciWrite8 (DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
- MCH_DEFAULT_SMBASE_LCK);
+ PciWrite8 (
+ DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),
+ MCH_DEFAULT_SMBASE_LCK
+ );
}
GetStates (LockState, OpenState);
if (*OpenState || !*LockState) {
return EFI_DEVICE_ERROR;
}
+
return EFI_SUCCESS;
}
EFI_STATUS
SmramAccessGetCapabilities (
- IN BOOLEAN LockState,
- IN BOOLEAN OpenState,
- IN OUT UINTN *SmramMapSize,
- IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ IN BOOLEAN LockState,
+ IN BOOLEAN OpenState,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
)
{
- UINTN OriginalSize;
- UINT32 TsegMemoryBaseMb, TsegMemoryBase;
- UINT64 CommonRegionState;
- UINT8 TsegSizeBits;
+ UINTN OriginalSize;
+ UINT32 TsegMemoryBaseMb, TsegMemoryBase;
+ UINT64 CommonRegionState;
+ UINT8 TsegSizeBits;
OriginalSize = *SmramMapSize;
*SmramMapSize = DescIdxCount * sizeof *SmramMap;
@@ -180,7 +187,7 @@ SmramAccessGetCapabilities (
// Read the TSEG Memory Base register.
//
TsegMemoryBaseMb = PciRead32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB));
- TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
+ TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
//
// Precompute the region state bits that will be set for all regions.
@@ -198,7 +205,7 @@ SmramAccessGetCapabilities (
SmramMap[DescIdxSmmS3ResumeState].CpuStart = TsegMemoryBase;
SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =
EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
- SmramMap[DescIdxSmmS3ResumeState].RegionState =
+ SmramMap[DescIdxSmmS3ResumeState].RegionState =
CommonRegionState | EFI_ALLOCATED;
//
@@ -213,7 +220,7 @@ SmramAccessGetCapabilities (
SmramMap[DescIdxMain].PhysicalStart =
SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
- SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
+ SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
SmramMap[DescIdxMain].PhysicalSize =
(TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
diff --git a/OvmfPkg/SmmAccess/SmramInternal.h b/OvmfPkg/SmmAccess/SmramInternal.h
index a4d8827adf..da5b7bbca1 100644
--- a/OvmfPkg/SmmAccess/SmramInternal.h
+++ b/OvmfPkg/SmmAccess/SmramInternal.h
@@ -28,7 +28,7 @@ typedef enum {
//
// The value of PcdQ35TsegMbytes is saved into this variable at module startup.
//
-extern UINT16 mQ35TsegMbytes;
+extern UINT16 mQ35TsegMbytes;
/**
Save PcdQ35TsegMbytes into mQ35TsegMbytes.
@@ -62,8 +62,8 @@ InitQ35SmramAtDefaultSmbase (
**/
VOID
GetStates (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
);
//
@@ -79,26 +79,26 @@ GetStates (
EFI_STATUS
SmramAccessOpen (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
);
EFI_STATUS
SmramAccessClose (
- OUT BOOLEAN *LockState,
- OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ OUT BOOLEAN *OpenState
);
EFI_STATUS
SmramAccessLock (
- OUT BOOLEAN *LockState,
- IN OUT BOOLEAN *OpenState
+ OUT BOOLEAN *LockState,
+ IN OUT BOOLEAN *OpenState
);
EFI_STATUS
SmramAccessGetCapabilities (
- IN BOOLEAN LockState,
- IN BOOLEAN OpenState,
- IN OUT UINTN *SmramMapSize,
- IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ IN BOOLEAN LockState,
+ IN BOOLEAN OpenState,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 12:21:19 +0000