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diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
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+/** @file
+PCI express expansion ports
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PcieExpansionPrt_asi
+#define PcieExpansionPrt_asi
+
+Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
+{
+ Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
+
+ OperationRegion (PES0,PCI_Config,0x40,0xA0)
+ Field (PES0, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x1A), // SLSTS - Slot Status Register
+ ABP0, 1, // Bit 0, Attention Button Pressed
+ , 2,
+ PDC0, 1, // Bit 3, Presence Detect Changed
+ , 2,
+ PDS0, 1, // Bit 6, Presence Detect State
+ , 1,
+ LSC0, 1, // Bit 8, Link Active State Changed
+ offset (0x20),
+ , 16,
+ PMS0, 1, // Bit 16, PME Status
+ offset (0x98),
+ , 30,
+ HPE0, 1, // Bit 30, Hot Plug SCI Enable
+ PCE0, 1, // Bit 31, Power Management SCI Enable.
+ , 30,
+ HPS0, 1, // Bit 30, Hot Plug SCI Status
+ PCS0, 1, // Bit 31, Power Management SCI Status.
+ }
+
+ Method(_PRT,0,NotSerialized) {
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
+ }
+ )
+ }
+ else // IOAPIC Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
+ Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
+ Package() {0x0000ffff, 1, 0, 21},
+ Package() {0x0000ffff, 2, 0, 22},
+ Package() {0x0000ffff, 3, 0, 23},
+ }
+ )
+ }
+ }
+}
+
+Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
+{
+ Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
+ OperationRegion (PES1,PCI_Config,0x40,0xA0)
+ Field (PES1, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x1A), // SLSTS - Slot Status Register
+ ABP1, 1, // Bit 0, Attention Button Pressed
+ , 2,
+ PDC1, 1, // Bit 3, Presence Detect Changed
+ , 2,
+ PDS1, 1, // Bit 6, Presence Detect State
+ , 1,
+ LSC1, 1, // Bit 8, Link Active State Changed
+ offset (0x20),
+ , 16,
+ PMS1, 1, // Bit 16, PME Status
+ offset (0x98),
+ , 30,
+ HPE1, 1, // Bit 30, Hot Plug SCI Enable
+ PCE1, 1, // Bit 31, Power Management SCI Enable.
+ , 30,
+ HPS1, 1, // Bit 30, Hot Plug SCI Status
+ PCS1, 1, // Bit 31, Power Management SCI Status.
+ }
+ Method(_PRT,0,NotSerialized) {
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
+ }
+ )
+ }
+ else // IOAPIC Routing
+ {
+ Return (
+ Package()
+ {
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
+ Package() {0x0000ffff, 0, 0, 21},
+ Package() {0x0000ffff, 1, 0, 22},
+ Package() {0x0000ffff, 2, 0, 23},
+ Package() {0x0000ffff, 3, 0, 20},
+ }
+ )
+ }
+ }
+}
+
+#endif