diff options
Diffstat (limited to 'StdLib/Include/Arm/machine')
| -rw-r--r-- | StdLib/Include/Arm/machine/_math.h | 18 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/ansi.h | 106 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/asm.h | 167 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/atomic.h | 102 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/cpufunc.h | 558 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/float.h | 31 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/frame.h | 123 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/ieee.h | 13 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/lock.h | 89 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/math.h | 3 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/mcontext.h | 114 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/proc.h | 55 | ||||
| -rw-r--r-- | StdLib/Include/Arm/machine/signal.h | 22 |
13 files changed, 1401 insertions, 0 deletions
diff --git a/StdLib/Include/Arm/machine/_math.h b/StdLib/Include/Arm/machine/_math.h new file mode 100644 index 0000000000..67cf98c30d --- /dev/null +++ b/StdLib/Include/Arm/machine/_math.h @@ -0,0 +1,18 @@ +/**
+
+Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MACHINE_MATH_H
+#define _MACHINE_MATH_H
+
+//#define __HUGE_VAL ???????????.?????????????
+
+#endif /* _MACHINE_MATH_H */
diff --git a/StdLib/Include/Arm/machine/ansi.h b/StdLib/Include/Arm/machine/ansi.h new file mode 100644 index 0000000000..e06f111355 --- /dev/null +++ b/StdLib/Include/Arm/machine/ansi.h @@ -0,0 +1,106 @@ +/* $NetBSD: ansi.h,v 1.7 2006/10/04 13:51:59 tnozaki Exp $ */
+
+/*
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)ansi.h 8.2 (Berkeley) 1/4/94
+ */
+
+#ifndef _ANSI_H_
+#define _ANSI_H_
+
+#include <sys/cdefs.h>
+
+#include <machine/int_types.h>
+
+/*
+ * Types which are fundamental to the implementation and may appear in
+ * more than one standard header are defined here. Standard headers
+ * then use:
+ * #ifdef _BSD_SIZE_T_
+ * typedef _BSD_SIZE_T_ size_t;
+ * #undef _BSD_SIZE_T_
+ * #endif
+ */
+#ifdef __ELF__
+#define _BSD_CLOCK_T_ unsigned int /* clock() */
+#define _BSD_PTRDIFF_T_ long int /* ptr1 - ptr2 */
+#define _BSD_SIZE_T_ unsigned long int /* sizeof() */
+#define _BSD_SSIZE_T_ long int /* byte count or error */
+#define _BSD_TIME_T_ int /* time() */
+#else
+#define _BSD_CLOCK_T_ unsigned long /* clock() */
+#define _BSD_PTRDIFF_T_ int /* ptr1 - ptr2 */
+#define _BSD_SIZE_T_ unsigned int /* sizeof() */
+#define _BSD_SSIZE_T_ int /* byte count or error */
+#define _BSD_TIME_T_ long /* time() */
+#endif
+#if __GNUC_PREREQ__(2, 96)
+#define _BSD_VA_LIST_ __builtin_va_list /* GCC built-in type */
+#else
+#define _BSD_VA_LIST_ char * /* va_list */
+#endif
+#define _BSD_CLOCKID_T_ int /* clockid_t */
+#define _BSD_TIMER_T_ int /* timer_t */
+#define _BSD_SUSECONDS_T_ int /* suseconds_t */
+#define _BSD_USECONDS_T_ unsigned int /* useconds_t */
+
+/*
+ * NOTE: rune_t is not covered by ANSI nor other standards, and should not
+ * be instantiated outside of lib/libc/locale. use wchar_t.
+ *
+ * Runes (wchar_t) is declared to be an ``int'' instead of the more natural
+ * ``unsigned long'' or ``long''. Two things are happening here. It is not
+ * unsigned so that EOF (-1) can be naturally assigned to it and used. Also,
+ * it looks like 10646 will be a 31 bit standard. This means that if your
+ * ints cannot hold 32 bits, you will be in trouble. The reason an int was
+ * chosen over a long is that the is*() and to*() routines take ints (says
+ * ANSI C), but they use _RUNE_T_ instead of int. By changing it here, you
+ * lose a bit of ANSI conformance, but your programs will still work.
+ *
+ * Note that _WCHAR_T_ and _RUNE_T_ must be of the same type. When wchar_t
+ * and rune_t are typedef'd, _WCHAR_T_ will be undef'd, but _RUNE_T remains
+ * defined for ctype.h.
+ */
+#define _BSD_WCHAR_T_ int /* wchar_t */
+#define _BSD_WINT_T_ int /* wint_t */
+#define _BSD_RUNE_T_ int /* rune_t */
+#define _BSD_WCTRANS_T_ void * /* wctrans_t */
+#define _BSD_WCTYPE_T_ void * /* wctype_t */
+
+/*
+ * mbstate_t is an opaque object to keep conversion state, during multibyte
+ * stream conversions. The content must not be referenced by user programs.
+ */
+typedef union {
+ __int64_t __mbstateL; /* for alignment */
+ char __mbstate8[128];
+} __mbstate_t;
+#define _BSD_MBSTATE_T_ __mbstate_t /* mbstate_t */
+
+#endif /* _ANSI_H_ */
diff --git a/StdLib/Include/Arm/machine/asm.h b/StdLib/Include/Arm/machine/asm.h new file mode 100644 index 0000000000..b15698eb9f --- /dev/null +++ b/StdLib/Include/Arm/machine/asm.h @@ -0,0 +1,167 @@ +/* $NetBSD: asm.h,v 1.8 2006/01/20 22:02:40 christos Exp $ */
+
+/*
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: @(#)asm.h 5.5 (Berkeley) 5/7/91
+ */
+
+#ifndef _ARM32_ASM_H_
+#define _ARM32_ASM_H_
+
+#ifdef __ELF__
+# define _C_LABEL(x) x
+#else
+# ifdef __STDC__
+# define _C_LABEL(x) _ ## x
+# else
+# define _C_LABEL(x) _/**/x
+# endif
+#endif
+#define _ASM_LABEL(x) x
+
+#ifdef __STDC__
+# define __CONCAT(x,y) x ## y
+# define __STRING(x) #x
+#else
+# define __CONCAT(x,y) x/**/y
+# define __STRING(x) "x"
+#endif
+
+#ifndef _ALIGN_TEXT
+# define _ALIGN_TEXT .align 0
+#endif
+
+/*
+ * gas/arm uses @ as a single comment character and thus cannot be used here
+ * Instead it recognised the # instead of an @ symbols in .type directives
+ * We define a couple of macros so that assembly code will not be dependant
+ * on one or the other.
+ */
+#define _ASM_TYPE_FUNCTION #function
+#define _ASM_TYPE_OBJECT #object
+#define _ENTRY(x) \
+ .text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x:
+
+#ifdef GPROF
+# ifdef __ELF__
+# define _PROF_PROLOGUE \
+ mov ip, lr; bl __mcount
+# else
+# define _PROF_PROLOGUE \
+ mov ip,lr; bl mcount
+# endif
+#else
+# define _PROF_PROLOGUE
+#endif
+
+#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
+#define ENTRY_NP(y) _ENTRY(_C_LABEL(y))
+#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
+#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y))
+
+#define ASMSTR .asciz
+
+#if defined(__ELF__) && defined(PIC)
+#ifdef __STDC__
+#define PIC_SYM(x,y) x ## ( ## y ## )
+#else
+#define PIC_SYM(x,y) x/**/(/**/y/**/)
+#endif
+#else
+#define PIC_SYM(x,y) x
+#endif
+
+#ifdef __ELF__
+#define RCSID(x) .section ".ident"; .asciz x
+#else
+#define RCSID(x) .text; .asciz x
+#endif
+
+#ifdef __ELF__
+#define WEAK_ALIAS(alias,sym) \
+ .weak alias; \
+ alias = sym
+#endif
+
+/*
+ * STRONG_ALIAS: create a strong alias.
+ */
+#define STRONG_ALIAS(alias,sym) \
+ .globl alias; \
+ alias = sym
+
+#ifdef __STDC__
+#define WARN_REFERENCES(sym,msg) \
+ .stabs msg ## ,30,0,0,0 ; \
+ .stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0
+#elif defined(__ELF__)
+#define WARN_REFERENCES(sym,msg) \
+ .stabs msg,30,0,0,0 ; \
+ .stabs __STRING(sym),1,0,0,0
+#else
+#define WARN_REFERENCES(sym,msg) \
+ .stabs msg,30,0,0,0 ; \
+ .stabs __STRING(_/**/sym),1,0,0,0
+#endif /* __STDC__ */
+
+#if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__)
+#define _ARM_ARCH_6
+#endif
+
+#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5__) || \
+ defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5TE__) || \
+ defined (__ARM_ARCH_5TEJ__)
+#define _ARM_ARCH_5
+#endif
+
+#if defined (_ARM_ARCH_5) || defined (__ARM_ARCH_4T__)
+#define _ARM_ARCH_4T
+#endif
+
+
+#if defined (_ARM_ARCH_4T)
+# define RET bx lr
+# ifdef __STDC__
+# define RETc(c) bx##c lr
+# else
+# define RETc(c) bx/**/c lr
+# endif
+#else
+# define RET mov pc, lr
+# ifdef __STDC__
+# define RETc(c) mov##c pc, lr
+# else
+# define RETc(c) mov/**/c pc, lr
+# endif
+#endif
+
+#endif /* !_ARM_ASM_H_ */
diff --git a/StdLib/Include/Arm/machine/atomic.h b/StdLib/Include/Arm/machine/atomic.h new file mode 100644 index 0000000000..ffd83c7375 --- /dev/null +++ b/StdLib/Include/Arm/machine/atomic.h @@ -0,0 +1,102 @@ +/* $NetBSD: atomic.h,v 1.5 2005/12/28 19:09:29 perry Exp $ */
+
+/*
+ * Copyright (C) 1994-1997 Mark Brinicombe
+ * Copyright (C) 1994 Brini
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Brini.
+ * 4. The name of Brini may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ATOMIC_H_
+#define _ARM_ATOMIC_H_
+
+#ifndef ATOMIC_SET_BIT_NONINLINE_REQUIRED
+
+#if defined(__PROG26) || defined(ATOMIC_SET_BIT_NOINLINE)
+#define ATOMIC_SET_BIT_NONINLINE_REQUIRED
+#endif
+
+#endif /* ATOMIC_SET_BIT_NONINLINE_REQUIRED */
+
+
+#ifndef _LOCORE
+
+#include <sys/types.h>
+#include <arm/armreg.h> /* I32_bit */
+
+#ifdef ATOMIC_SET_BIT_NONINLINE_REQUIRED
+void atomic_set_bit( u_int *, u_int );
+void atomic_clear_bit( u_int *, u_int );
+#endif
+
+#ifdef __PROG32
+#define __with_interrupts_disabled(expr) \
+ do { \
+ u_int cpsr_save, tmp; \
+ \
+ __asm volatile( \
+ "mrs %0, cpsr;" \
+ "orr %1, %0, %2;" \
+ "msr cpsr_all, %1;" \
+ : "=r" (cpsr_save), "=r" (tmp) \
+ : "I" (I32_bit) \
+ : "cc" ); \
+ (expr); \
+ __asm volatile( \
+ "msr cpsr_all, %0" \
+ : /* no output */ \
+ : "r" (cpsr_save) \
+ : "cc" ); \
+ } while(0)
+
+static __inline void
+inline_atomic_set_bit( u_int *address, u_int setmask )
+{
+ __with_interrupts_disabled( *address |= setmask );
+}
+
+static __inline void
+inline_atomic_clear_bit( u_int *address, u_int clearmask )
+{
+ __with_interrupts_disabled( *address &= ~clearmask );
+}
+
+#if !defined(ATOMIC_SET_BIT_NOINLINE)
+
+#define atomic_set_bit(a,m) inline_atomic_set_bit(a,m)
+#define atomic_clear_bit(a,m) inline_atomic_clear_bit(a,m)
+
+#endif
+
+#endif /* __PROG32 */
+
+#undef __with_interrupts_disabled
+
+#endif /* _LOCORE */
+#endif /* _ARM_ATOMIC_H_ */
diff --git a/StdLib/Include/Arm/machine/cpufunc.h b/StdLib/Include/Arm/machine/cpufunc.h new file mode 100644 index 0000000000..c94a30a9e7 --- /dev/null +++ b/StdLib/Include/Arm/machine/cpufunc.h @@ -0,0 +1,558 @@ +/* $NetBSD: cpufunc.h,v 1.37.24.1 2007/02/21 18:36:02 snj Exp $ */
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Causality Limited.
+ * 4. The name of Causality Limited may not be used to endorse or promote
+ * products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * cpufunc.h
+ *
+ * Prototypes for cpu, mmu and tlb related functions.
+ */
+
+#ifndef _ARM32_CPUFUNC_H_
+#define _ARM32_CPUFUNC_H_
+
+#ifdef _KERNEL
+
+#include <sys/types.h>
+#include <arm/cpuconf.h>
+
+struct cpu_functions {
+
+ /* CPU functions */
+
+ u_int (*cf_id) __P((void));
+ void (*cf_cpwait) __P((void));
+
+ /* MMU functions */
+
+ u_int (*cf_control) __P((u_int, u_int));
+ void (*cf_domains) __P((u_int));
+ void (*cf_setttb) __P((u_int));
+ u_int (*cf_faultstatus) __P((void));
+ u_int (*cf_faultaddress) __P((void));
+
+ /* TLB functions */
+
+ void (*cf_tlb_flushID) __P((void));
+ void (*cf_tlb_flushID_SE) __P((u_int));
+ void (*cf_tlb_flushI) __P((void));
+ void (*cf_tlb_flushI_SE) __P((u_int));
+ void (*cf_tlb_flushD) __P((void));
+ void (*cf_tlb_flushD_SE) __P((u_int));
+
+ /*
+ * Cache operations:
+ *
+ * We define the following primitives:
+ *
+ * icache_sync_all Synchronize I-cache
+ * icache_sync_range Synchronize I-cache range
+ *
+ * dcache_wbinv_all Write-back and Invalidate D-cache
+ * dcache_wbinv_range Write-back and Invalidate D-cache range
+ * dcache_inv_range Invalidate D-cache range
+ * dcache_wb_range Write-back D-cache range
+ *
+ * idcache_wbinv_all Write-back and Invalidate D-cache,
+ * Invalidate I-cache
+ * idcache_wbinv_range Write-back and Invalidate D-cache,
+ * Invalidate I-cache range
+ *
+ * Note that the ARM term for "write-back" is "clean". We use
+ * the term "write-back" since it's a more common way to describe
+ * the operation.
+ *
+ * There are some rules that must be followed:
+ *
+ * I-cache Synch (all or range):
+ * The goal is to synchronize the instruction stream,
+ * so you may beed to write-back dirty D-cache blocks
+ * first. If a range is requested, and you can't
+ * synchronize just a range, you have to hit the whole
+ * thing.
+ *
+ * D-cache Write-Back and Invalidate range:
+ * If you can't WB-Inv a range, you must WB-Inv the
+ * entire D-cache.
+ *
+ * D-cache Invalidate:
+ * If you can't Inv the D-cache, you must Write-Back
+ * and Invalidate. Code that uses this operation
+ * MUST NOT assume that the D-cache will not be written
+ * back to memory.
+ *
+ * D-cache Write-Back:
+ * If you can't Write-back without doing an Inv,
+ * that's fine. Then treat this as a WB-Inv.
+ * Skipping the invalidate is merely an optimization.
+ *
+ * All operations:
+ * Valid virtual addresses must be passed to each
+ * cache operation.
+ */
+ void (*cf_icache_sync_all) __P((void));
+ void (*cf_icache_sync_range) __P((vaddr_t, vsize_t));
+
+ void (*cf_dcache_wbinv_all) __P((void));
+ void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t));
+ void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t));
+ void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t));
+
+ void (*cf_idcache_wbinv_all) __P((void));
+ void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t));
+
+ /* Other functions */
+
+ void (*cf_flush_prefetchbuf) __P((void));
+ void (*cf_drain_writebuf) __P((void));
+ void (*cf_flush_brnchtgt_C) __P((void));
+ void (*cf_flush_brnchtgt_E) __P((u_int));
+
+ void (*cf_sleep) __P((int mode));
+
+ /* Soft functions */
+
+ int (*cf_dataabt_fixup) __P((void *));
+ int (*cf_prefetchabt_fixup) __P((void *));
+
+ void (*cf_context_switch) __P((void));
+
+ void (*cf_setup) __P((char *));
+};
+
+extern struct cpu_functions cpufuncs;
+extern u_int cputype;
+
+#define cpu_id() cpufuncs.cf_id()
+#define cpu_cpwait() cpufuncs.cf_cpwait()
+
+#define cpu_control(c, e) cpufuncs.cf_control(c, e)
+#define cpu_domains(d) cpufuncs.cf_domains(d)
+#define cpu_setttb(t) cpufuncs.cf_setttb(t)
+#define cpu_faultstatus() cpufuncs.cf_faultstatus()
+#define cpu_faultaddress() cpufuncs.cf_faultaddress()
+
+#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
+#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
+#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
+#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
+#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
+#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
+
+#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
+#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
+
+#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
+#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
+#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
+#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
+
+#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
+#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
+
+#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
+#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
+#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
+#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
+
+#define cpu_sleep(m) cpufuncs.cf_sleep(m)
+
+#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
+#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
+#define ABORT_FIXUP_OK 0 /* fixup succeeded */
+#define ABORT_FIXUP_FAILED 1 /* fixup failed */
+#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
+
+#define cpu_setup(a) cpufuncs.cf_setup(a)
+
+int set_cpufuncs __P((void));
+#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
+#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
+
+void cpufunc_nullop __P((void));
+int cpufunc_null_fixup __P((void *));
+int early_abort_fixup __P((void *));
+int late_abort_fixup __P((void *));
+u_int cpufunc_id __P((void));
+u_int cpufunc_control __P((u_int, u_int));
+void cpufunc_domains __P((u_int));
+u_int cpufunc_faultstatus __P((void));
+u_int cpufunc_faultaddress __P((void));
+
+#ifdef CPU_ARM3
+u_int arm3_control __P((u_int, u_int));
+void arm3_cache_flush __P((void));
+#endif /* CPU_ARM3 */
+
+#if defined(CPU_ARM6) || defined(CPU_ARM7)
+void arm67_setttb __P((u_int));
+void arm67_tlb_flush __P((void));
+void arm67_tlb_purge __P((u_int));
+void arm67_cache_flush __P((void));
+void arm67_context_switch __P((void));
+#endif /* CPU_ARM6 || CPU_ARM7 */
+
+#ifdef CPU_ARM6
+void arm6_setup __P((char *));
+#endif /* CPU_ARM6 */
+
+#ifdef CPU_ARM7
+void arm7_setup __P((char *));
+#endif /* CPU_ARM7 */
+
+#ifdef CPU_ARM7TDMI
+int arm7_dataabt_fixup __P((void *));
+void arm7tdmi_setup __P((char *));
+void arm7tdmi_setttb __P((u_int));
+void arm7tdmi_tlb_flushID __P((void));
+void arm7tdmi_tlb_flushID_SE __P((u_int));
+void arm7tdmi_cache_flushID __P((void));
+void arm7tdmi_context_switch __P((void));
+#endif /* CPU_ARM7TDMI */
+
+#ifdef CPU_ARM8
+void arm8_setttb __P((u_int));
+void arm8_tlb_flushID __P((void));
+void arm8_tlb_flushID_SE __P((u_int));
+void arm8_cache_flushID __P((void));
+void arm8_cache_flushID_E __P((u_int));
+void arm8_cache_cleanID __P((void));
+void arm8_cache_cleanID_E __P((u_int));
+void arm8_cache_purgeID __P((void));
+void arm8_cache_purgeID_E __P((u_int entry));
+
+void arm8_cache_syncI __P((void));
+void arm8_cache_cleanID_rng __P((vaddr_t, vsize_t));
+void arm8_cache_cleanD_rng __P((vaddr_t, vsize_t));
+void arm8_cache_purgeID_rng __P((vaddr_t, vsize_t));
+void arm8_cache_purgeD_rng __P((vaddr_t, vsize_t));
+void arm8_cache_syncI_rng __P((vaddr_t, vsize_t));
+
+void arm8_context_switch __P((void));
+
+void arm8_setup __P((char *));
+
+u_int arm8_clock_config __P((u_int, u_int));
+#endif
+
+#ifdef CPU_SA110
+void sa110_setup __P((char *));
+void sa110_context_switch __P((void));
+#endif /* CPU_SA110 */
+
+#if defined(CPU_SA1100) || defined(CPU_SA1110)
+void sa11x0_drain_readbuf __P((void));
+
+void sa11x0_context_switch __P((void));
+void sa11x0_cpu_sleep __P((int));
+
+void sa11x0_setup __P((char *));
+#endif
+
+#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
+void sa1_setttb __P((u_int));
+
+void sa1_tlb_flushID_SE __P((u_int));
+
+void sa1_cache_flushID __P((void));
+void sa1_cache_flushI __P((void));
+void sa1_cache_flushD __P((void));
+void sa1_cache_flushD_SE __P((u_int));
+
+void sa1_cache_cleanID __P((void));
+void sa1_cache_cleanD __P((void));
+void sa1_cache_cleanD_E __P((u_int));
+
+void sa1_cache_purgeID __P((void));
+void sa1_cache_purgeID_E __P((u_int));
+void sa1_cache_purgeD __P((void));
+void sa1_cache_purgeD_E __P((u_int));
+
+void sa1_cache_syncI __P((void));
+void sa1_cache_cleanID_rng __P((vaddr_t, vsize_t));
+void sa1_cache_cleanD_rng __P((vaddr_t, vsize_t));
+void sa1_cache_purgeID_rng __P((vaddr_t, vsize_t));
+void sa1_cache_purgeD_rng __P((vaddr_t, vsize_t));
+void sa1_cache_syncI_rng __P((vaddr_t, vsize_t));
+
+#endif
+
+#ifdef CPU_ARM9
+void arm9_setttb __P((u_int));
+
+void arm9_tlb_flushID_SE __P((u_int));
+
+void arm9_icache_sync_all __P((void));
+void arm9_icache_sync_range __P((vaddr_t, vsize_t));
+
+void arm9_dcache_wbinv_all __P((void));
+void arm9_dcache_wbinv_range __P((vaddr_t, vsize_t));
+void arm9_dcache_inv_range __P((vaddr_t, vsize_t));
+void arm9_dcache_wb_range __P((vaddr_t, vsize_t));
+
+void arm9_idcache_wbinv_all __P((void));
+void arm9_idcache_wbinv_range __P((vaddr_t, vsize_t));
+
+void arm9_context_switch __P((void));
+
+void arm9_setup __P((char *));
+
+extern unsigned arm9_dcache_sets_max;
+extern unsigned arm9_dcache_sets_inc;
+extern unsigned arm9_dcache_index_max;
+extern unsigned arm9_dcache_index_inc;
+#endif
+
+#if defined(CPU_ARM9E) || defined(CPU_ARM10)
+void arm10_tlb_flushID_SE __P((u_int));
+void arm10_tlb_flushI_SE __P((u_int));
+
+void arm10_context_switch __P((void));
+
+void arm10_setup __P((char *));
+#endif
+
+#ifdef CPU_ARM11
+void arm11_setttb __P((u_int));
+
+void arm11_tlb_flushID_SE __P((u_int));
+void arm11_tlb_flushI_SE __P((u_int));
+
+void arm11_context_switch __P((void));
+
+void arm11_setup __P((char *string));
+void arm11_tlb_flushID __P((void));
+void arm11_tlb_flushI __P((void));
+void arm11_tlb_flushD __P((void));
+void arm11_tlb_flushD_SE __P((u_int va));
+
+void arm11_drain_writebuf __P((void));
+#endif
+
+#if defined(CPU_ARM9E) || defined (CPU_ARM10)
+void armv5_ec_setttb __P((u_int));
+
+void armv5_ec_icache_sync_all __P((void));
+void armv5_ec_icache_sync_range __P((vaddr_t, vsize_t));
+
+void armv5_ec_dcache_wbinv_all __P((void));
+void armv5_ec_dcache_wbinv_range __P((vaddr_t, vsize_t));
+void armv5_ec_dcache_inv_range __P((vaddr_t, vsize_t));
+void armv5_ec_dcache_wb_range __P((vaddr_t, vsize_t));
+
+void armv5_ec_idcache_wbinv_all __P((void));
+void armv5_ec_idcache_wbinv_range __P((vaddr_t, vsize_t));
+#endif
+
+#if defined (CPU_ARM10) || defined (CPU_ARM11)
+void armv5_setttb __P((u_int));
+
+void armv5_icache_sync_all __P((void));
+void armv5_icache_sync_range __P((vaddr_t, vsize_t));
+
+void armv5_dcache_wbinv_all __P((void));
+void armv5_dcache_wbinv_range __P((vaddr_t, vsize_t));
+void armv5_dcache_inv_range __P((vaddr_t, vsize_t));
+void armv5_dcache_wb_range __P((vaddr_t, vsize_t));
+
+void armv5_idcache_wbinv_all __P((void));
+void armv5_idcache_wbinv_range __P((vaddr_t, vsize_t));
+
+extern unsigned armv5_dcache_sets_max;
+extern unsigned armv5_dcache_sets_inc;
+extern unsigned armv5_dcache_index_max;
+extern unsigned armv5_dcache_index_inc;
+#endif
+
+#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
+ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
+
+void armv4_tlb_flushID __P((void));
+void armv4_tlb_flushI __P((void));
+void armv4_tlb_flushD __P((void));
+void armv4_tlb_flushD_SE __P((u_int));
+
+void armv4_drain_writebuf __P((void));
+#endif
+
+#if defined(CPU_IXP12X0)
+void ixp12x0_drain_readbuf __P((void));
+void ixp12x0_context_switch __P((void));
+void ixp12x0_setup __P((char *));
+#endif
+
+#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
+ defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
+void xscale_cpwait __P((void));
+
+void xscale_cpu_sleep __P((int));
+
+u_int xscale_control __P((u_int, u_int));
+
+void xscale_setttb __P((u_int));
+
+void xscale_tlb_flushID_SE __P((u_int));
+
+void xscale_cache_flushID __P((void));
+void xscale_cache_flushI __P((void));
+void xscale_cache_flushD __P((void));
+void xscale_cache_flushD_SE __P((u_int));
+
+void xscale_cache_cleanID __P((void));
+void xscale_cache_cleanD __P((void));
+void xscale_cache_cleanD_E __P((u_int));
+
+void xscale_cache_clean_minidata __P((void));
+
+void xscale_cache_purgeID __P((void));
+void xscale_cache_purgeID_E __P((u_int));
+void xscale_cache_purgeD __P((void));
+void xscale_cache_purgeD_E __P((u_int));
+
+void xscale_cache_syncI __P((void));
+void xscale_cache_cleanID_rng __P((vaddr_t, vsize_t));
+void xscale_cache_cleanD_rng __P((vaddr_t, vsize_t));
+void xscale_cache_purgeID_rng __P((vaddr_t, vsize_t));
+void xscale_cache_purgeD_rng __P((vaddr_t, vsize_t));
+void xscale_cache_syncI_rng __P((vaddr_t, vsize_t));
+void xscale_cache_flushD_rng __P((vaddr_t, vsize_t));
+
+void xscale_context_switch __P((void));
+
+void xscale_setup __P((char *));
+#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
+
+#define tlb_flush cpu_tlb_flushID
+#define setttb cpu_setttb
+#define drain_writebuf cpu_drain_writebuf
+
+/*
+ * Macros for manipulating CPU interrupts
+ */
+#ifdef __PROG32
+static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
+
+static __inline u_int32_t
+__set_cpsr_c(u_int bic, u_int eor)
+{
+ u_int32_t tmp, ret;
+
+ __asm volatile(
+ "mrs %0, cpsr\n" /* Get the CPSR */
+ "bic %1, %0, %2\n" /* Clear bits */
+ "eor %1, %1, %3\n" /* XOR bits */
+ "msr cpsr_c, %1\n" /* Set the control field of CPSR */
+ : "=&r" (ret), "=&r" (tmp)
+ : "r" (bic), "r" (eor) : "memory");
+
+ return ret;
+}
+
+#define disable_interrupts(mask) \
+ (__set_cpsr_c((mask) & (I32_bit | F32_bit), \
+ (mask) & (I32_bit | F32_bit)))
+
+#define enable_interrupts(mask) \
+ (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
+
+#define restore_interrupts(old_cpsr) \
+ (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
+#else /* ! __PROG32 */
+#define disable_interrupts(mask) \
+ (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
+ (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
+
+#define enable_interrupts(mask) \
+ (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
+
+#define restore_interrupts(old_r15) \
+ (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
+ (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
+#endif /* __PROG32 */
+
+#ifdef __PROG32
+/* Functions to manipulate the CPSR. */
+u_int SetCPSR(u_int, u_int);
+u_int GetCPSR(void);
+#else
+/* Functions to manipulate the processor control bits in r15. */
+u_int set_r15(u_int, u_int);
+u_int get_r15(void);
+#endif /* __PROG32 */
+
+/*
+ * Functions to manipulate cpu r13
+ * (in arm/arm32/setstack.S)
+ */
+
+void set_stackptr __P((u_int, u_int));
+u_int get_stackptr __P((u_int));
+
+/*
+ * Miscellany
+ */
+
+int get_pc_str_offset __P((void));
+
+/*
+ * CPU functions from locore.S
+ */
+
+void cpu_reset __P((void)) __attribute__((__noreturn__));
+
+/*
+ * Cache info variables.
+ */
+
+/* PRIMARY CACHE VARIABLES */
+extern int arm_picache_size;
+extern int arm_picache_line_size;
+extern int arm_picache_ways;
+
+extern int arm_pdcache_size; /* and unified */
+extern int arm_pdcache_line_size;
+extern int arm_pdcache_ways;
+
+extern int arm_pcache_type;
+extern int arm_pcache_unified;
+
+extern int arm_dcache_align;
+extern int arm_dcache_align_mask;
+
+#endif /* _KERNEL */
+#endif /* _ARM32_CPUFUNC_H_ */
+
+/* End of cpufunc.h */
diff --git a/StdLib/Include/Arm/machine/float.h b/StdLib/Include/Arm/machine/float.h new file mode 100644 index 0000000000..4bd79b3a3d --- /dev/null +++ b/StdLib/Include/Arm/machine/float.h @@ -0,0 +1,31 @@ +/* $NetBSD: float.h,v 1.6 2005/12/11 12:16:47 christos Exp $ */
+
+#ifndef _ARM_FLOAT_H_
+#define _ARM_FLOAT_H_
+
+#ifndef __VFP_FP__
+#define LDBL_MANT_DIG 64
+#define LDBL_EPSILON 1.0842021724855044340E-19L
+#define LDBL_DIG 18
+#define LDBL_MIN_EXP (-16381)
+#define LDBL_MIN 1.6810515715560467531E-4932L
+#define LDBL_MIN_10_EXP (-4931)
+#define LDBL_MAX_EXP 16384
+#define LDBL_MAX 1.1897314953572317650E+4932L
+#define LDBL_MAX_10_EXP 4932
+#endif
+
+#include <sys/float_ieee754.h>
+
+#ifndef __VFP_FP__
+#if !defined(_ANSI_SOURCE) && !defined(_POSIX_C_SOURCE) && \
+ !defined(_XOPEN_SOURCE) || \
+ ((__STDC_VERSION__ - 0) >= 199901L) || \
+ ((_POSIX_C_SOURCE - 0) >= 200112L) || \
+ ((_XOPEN_SOURCE - 0) >= 600) || \
+ defined(_ISOC99_SOURCE) || defined(_NETBSD_SOURCE)
+#define DECIMAL_DIG 21
+#endif /* !defined(_ANSI_SOURCE) && ... */
+#endif /* !__VFP_FP__ */
+
+#endif /* !_ARM_FLOAT_H_ */
diff --git a/StdLib/Include/Arm/machine/frame.h b/StdLib/Include/Arm/machine/frame.h new file mode 100644 index 0000000000..1037a9ff8d --- /dev/null +++ b/StdLib/Include/Arm/machine/frame.h @@ -0,0 +1,123 @@ +/* $NetBSD: frame.h,v 1.8 2005/12/11 12:16:47 christos Exp $ */
+
+/*
+ * Copyright (c) 1994-1997 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+/*
+ * arm/frame.h - Stack frames structures common to arm26 and arm32
+ */
+
+#ifndef _ARM_FRAME_H_
+#define _ARM_FRAME_H_
+
+#ifndef _LOCORE
+
+#include <sys/signal.h>
+#include <sys/sa.h>
+#include <sys/ucontext.h>
+
+/*
+ * Trap frame. Pushed onto the kernel stack on a trap (synchronous exception).
+ */
+
+typedef struct trapframe {
+ register_t tf_spsr; /* Zero on arm26 */
+ register_t tf_r0;
+ register_t tf_r1;
+ register_t tf_r2;
+ register_t tf_r3;
+ register_t tf_r4;
+ register_t tf_r5;
+ register_t tf_r6;
+ register_t tf_r7;
+ register_t tf_r8;
+ register_t tf_r9;
+ register_t tf_r10;
+ register_t tf_r11;
+ register_t tf_r12;
+ register_t tf_usr_sp;
+ register_t tf_usr_lr;
+ register_t tf_svc_sp; /* Not used on arm26 */
+ register_t tf_svc_lr; /* Not used on arm26 */
+ register_t tf_pc;
+} trapframe_t;
+
+/* Register numbers */
+#define tf_r13 tf_usr_sp
+#define tf_r14 tf_usr_lr
+#define tf_r15 tf_pc
+
+/*
+ * Signal frame. Pushed onto user stack before calling sigcode.
+ */
+#ifdef COMPAT_16
+struct sigframe_sigcontext {
+ struct sigcontext sf_sc;
+};
+#endif
+
+/* the pointers are use in the trampoline code to locate the ucontext */
+struct sigframe_siginfo {
+ siginfo_t sf_si; /* actual saved siginfo */
+ ucontext_t sf_uc; /* actual saved ucontext */
+};
+
+/*
+ * Scheduler activations upcall frame. Pushed onto user stack before
+ * calling an SA upcall.
+ */
+
+struct saframe {
+#if 0 /* in registers on entry to upcall */
+ int sa_type;
+ struct sa_t ** sa_sas;
+ int sa_events;
+ int sa_interrupted;
+#endif
+ void * sa_arg;
+};
+
+#ifdef _KERNEL
+__BEGIN_DECLS
+void sendsig_sigcontext(const ksiginfo_t *, const sigset_t *);
+void *getframe(struct lwp *, int, int *);
+__END_DECLS
+#define process_frame(l) ((l)->l_addr->u_pcb.pcb_tf)
+#endif
+
+#endif /* _LOCORE */
+
+#endif /* _ARM_FRAME_H_ */
+
+/* End of frame.h */
diff --git a/StdLib/Include/Arm/machine/ieee.h b/StdLib/Include/Arm/machine/ieee.h new file mode 100644 index 0000000000..5e6b4d9165 --- /dev/null +++ b/StdLib/Include/Arm/machine/ieee.h @@ -0,0 +1,13 @@ +/* $NetBSD: ieee.h,v 1.9 2005/12/11 12:16:47 christos Exp $ */
+
+#include <sys/ieee754.h>
+
+/*
+ * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
+ * high fraction; if the bit is set, it is a `quiet NaN'.
+ */
+
+#if 0
+#define SNG_QUIETNAN (1 << 22)
+#define DBL_QUIETNAN (1 << 19)
+#endif
diff --git a/StdLib/Include/Arm/machine/lock.h b/StdLib/Include/Arm/machine/lock.h new file mode 100644 index 0000000000..be11a470ab --- /dev/null +++ b/StdLib/Include/Arm/machine/lock.h @@ -0,0 +1,89 @@ +/* $NetBSD: lock.h,v 1.7 2005/12/28 19:09:29 perry Exp $ */
+
+/*-
+ * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-dependent spin lock operations.
+ *
+ * NOTE: The SWP insn used here is available only on ARM architecture
+ * version 3 and later (as well as 2a). What we are going to do is
+ * expect that the kernel will trap and emulate the insn. That will
+ * be slow, but give us the atomicity that we need.
+ */
+
+#ifndef _ARM_LOCK_H_
+#define _ARM_LOCK_H_
+
+static __inline int
+__swp(int __val, volatile int *__ptr)
+{
+
+ __asm volatile("swp %0, %1, [%2]"
+ : "=r" (__val) : "r" (__val), "r" (__ptr) : "memory");
+ return __val;
+}
+
+static __inline void __attribute__((__unused__))
+__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
+{
+
+ *alp = __SIMPLELOCK_UNLOCKED;
+}
+
+static __inline void __attribute__((__unused__))
+__cpu_simple_lock(__cpu_simple_lock_t *alp)
+{
+
+ while (__swp(__SIMPLELOCK_LOCKED, alp) != __SIMPLELOCK_UNLOCKED)
+ continue;
+}
+
+static __inline int __attribute__((__unused__))
+__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
+{
+
+ return (__swp(__SIMPLELOCK_LOCKED, alp) == __SIMPLELOCK_UNLOCKED);
+}
+
+static __inline void __attribute__((__unused__))
+__cpu_simple_unlock(__cpu_simple_lock_t *alp)
+{
+
+ *alp = __SIMPLELOCK_UNLOCKED;
+}
+
+#endif /* _ARM_LOCK_H_ */
diff --git a/StdLib/Include/Arm/machine/math.h b/StdLib/Include/Arm/machine/math.h new file mode 100644 index 0000000000..7eca11187b --- /dev/null +++ b/StdLib/Include/Arm/machine/math.h @@ -0,0 +1,3 @@ +/* $NetBSD: math.h,v 1.2 2002/02/19 13:08:14 simonb Exp $ */
+
+#define __HAVE_NANF
diff --git a/StdLib/Include/Arm/machine/mcontext.h b/StdLib/Include/Arm/machine/mcontext.h new file mode 100644 index 0000000000..0f450c43c1 --- /dev/null +++ b/StdLib/Include/Arm/machine/mcontext.h @@ -0,0 +1,114 @@ +/* $NetBSD: mcontext.h,v 1.5 2005/12/11 12:16:47 christos Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_MCONTEXT_H_
+#define _ARM_MCONTEXT_H_
+
+/*
+ * General register state
+ */
+#define _NGREG 17
+typedef unsigned int __greg_t;
+typedef __greg_t __gregset_t[_NGREG];
+
+#define _REG_R0 0
+#define _REG_R1 1
+#define _REG_R2 2
+#define _REG_R3 3
+#define _REG_R4 4
+#define _REG_R5 5
+#define _REG_R6 6
+#define _REG_R7 7
+#define _REG_R8 8
+#define _REG_R9 9
+#define _REG_R10 10
+#define _REG_R11 11
+#define _REG_R12 12
+#define _REG_R13 13
+#define _REG_R14 14
+#define _REG_R15 15
+#define _REG_CPSR 16
+/* Convenience synonyms */
+#define _REG_FP _REG_R11
+#define _REG_SP _REG_R13
+#define _REG_LR _REG_R14
+#define _REG_PC _REG_R15
+
+/*
+ * Floating point register state
+ */
+/* Note: the storage layout of this structure must be identical to ARMFPE! */
+typedef struct {
+ unsigned int __fp_fpsr;
+ struct {
+ unsigned int __fp_exponent;
+ unsigned int __fp_mantissa_hi;
+ unsigned int __fp_mantissa_lo;
+ } __fp_fr[8];
+} __fpregset_t;
+
+typedef struct {
+ unsigned int __vfp_fpscr;
+ unsigned int __vfp_fstmx[33];
+ unsigned int __vfp_fpsid;
+} __vfpregset_t;
+
+typedef struct {
+ __gregset_t __gregs;
+ union {
+ __fpregset_t __fpregs;
+ __vfpregset_t __vfpregs;
+ } __fpu;
+} mcontext_t;
+
+/* Machine-dependent uc_flags */
+#define _UC_ARM_VFP 0x00010000 /* FPU field is VFP */
+
+/* used by signal delivery to indicate status of signal stack */
+#define _UC_SETSTACK 0x00020000
+#define _UC_CLRSTACK 0x00040000
+
+#define _UC_MACHINE_PAD 3 /* Padding appended to ucontext_t */
+
+#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
+#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PC])
+#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_R0])
+
+#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
+
+#endif /* !_ARM_MCONTEXT_H_ */
diff --git a/StdLib/Include/Arm/machine/proc.h b/StdLib/Include/Arm/machine/proc.h new file mode 100644 index 0000000000..14718611d3 --- /dev/null +++ b/StdLib/Include/Arm/machine/proc.h @@ -0,0 +1,55 @@ +/* $NetBSD: proc.h,v 1.6 2003/03/05 11:28:14 agc Exp $ */
+
+/*
+ * Copyright (c) 1994 Mark Brinicombe.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the RiscBSD team.
+ * 4. The name "RiscBSD" nor the name of the author may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM32_PROC_H_
+#define _ARM32_PROC_H_
+
+/*
+ * Machine-dependent part of the proc structure for arm.
+ */
+
+struct trapframe;
+struct lwp;
+
+struct mdlwp {
+ int md_dummy; /* must have at least one member */
+};
+
+struct mdproc {
+ void (*md_syscall)(struct trapframe *, struct lwp *, u_int32_t);
+ int pmc_enabled; /* bitfield of enabled counters */
+ void *pmc_state; /* port-specific pmc state */
+};
+
+#endif /* _ARM32_PROC_H_ */
diff --git a/StdLib/Include/Arm/machine/signal.h b/StdLib/Include/Arm/machine/signal.h new file mode 100644 index 0000000000..d42ca13e08 --- /dev/null +++ b/StdLib/Include/Arm/machine/signal.h @@ -0,0 +1,22 @@ +/**
+Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MACHINE_SIGNAL_H
+#define _MACHINE_SIGNAL_H
+#include <sys/common.h>
+
+/** The type sig_atomic_t is the (possibly volatile-qualified) integer type of
+ an object that can be accessed as an atomic entity, even in the presence
+ of asynchronous interrupts.
+**/
+typedef INTN sig_atomic_t;
+
+#endif /* _MACHINE_SIGNAL_H */
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