diff options
Diffstat (limited to 'UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32')
3 files changed, 1102 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c new file mode 100644 index 0000000000..a69f0d3d2b --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -0,0 +1,164 @@ +/** @file
+ IA32 CPU Exception Hanlder functons.
+
+ Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuExceptionCommon.h"
+
+/**
+ Internal function to setup CPU exception handlers.
+
+**/
+VOID
+InternalSetupCpuExceptionHandlers (
+ VOID
+ )
+{
+ IA32_DESCRIPTOR IdtDescriptor;
+ UINTN IdtSize;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+ UINT16 CodeSegment;
+ IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
+ UINTN Index;
+ UINTN InterruptHandler;;
+
+ //
+ // Read IDT descriptor and calculate IDT size
+ //
+ AsmReadIdtr (&IdtDescriptor);
+ IdtSize = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
+ if (IdtSize > CPU_EXCEPTION_NUM) {
+ //
+ // CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
+ //
+ IdtSize = CPU_EXCEPTION_NUM;
+ }
+
+ //
+ // Use current CS as the segment selector of interrupt gate in IDT
+ //
+ CodeSegment = AsmReadCs ();
+ IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
+
+ GetTemplateAddressMap (&TemplateMap);
+
+ for (Index = 0; Index < IdtSize; Index ++) {
+ InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
+ IdtEntry[Index].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
+ IdtEntry[Index].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
+ IdtEntry[Index].Bits.Selector = CodeSegment;
+ IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+ }
+}
+
+/**
+ Dump CPU content information.
+
+ @param ExceptionType Exception type.
+ @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpCpuContent (
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINTN ImageBase;
+ UINTN EntryPoint;
+
+ InternalPrintMessage (
+ "!!!! IA32 Exception Type - %08x CPU Apic ID - %08x !!!!\n",
+ ExceptionType,
+ GetApicId ()
+ );
+ InternalPrintMessage (
+ "EIP - %08x, CS - %08x, EFLAGS - %08x\n",
+ SystemContext.SystemContextIa32->Eip,
+ SystemContext.SystemContextIa32->Cs,
+ SystemContext.SystemContextIa32->Eflags
+ );
+ if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
+ InternalPrintMessage (
+ "ExceptionData - %08x\n",
+ SystemContext.SystemContextIa32->ExceptionData
+ );
+ }
+ InternalPrintMessage (
+ "EAX - %08x, ECX - %08x, EDX - %08x, EBX - %08x\n",
+ SystemContext.SystemContextIa32->Eax,
+ SystemContext.SystemContextIa32->Ecx,
+ SystemContext.SystemContextIa32->Edx,
+ SystemContext.SystemContextIa32->Ebx
+ );
+ InternalPrintMessage (
+ "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
+ SystemContext.SystemContextIa32->Esp,
+ SystemContext.SystemContextIa32->Ebp,
+ SystemContext.SystemContextIa32->Esi,
+ SystemContext.SystemContextIa32->Edi
+ );
+ InternalPrintMessage (
+ "DS - %08x, ES - %08x, FS - %08x, GS - %08x, SS - %08x\n",
+ SystemContext.SystemContextIa32->Ds,
+ SystemContext.SystemContextIa32->Es,
+ SystemContext.SystemContextIa32->Fs,
+ SystemContext.SystemContextIa32->Gs,
+ SystemContext.SystemContextIa32->Ss
+ );
+ InternalPrintMessage (
+ "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
+ SystemContext.SystemContextIa32->Cr0,
+ SystemContext.SystemContextIa32->Cr2,
+ SystemContext.SystemContextIa32->Cr3,
+ SystemContext.SystemContextIa32->Cr4
+ );
+ InternalPrintMessage (
+ "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
+ SystemContext.SystemContextIa32->Dr0,
+ SystemContext.SystemContextIa32->Dr1,
+ SystemContext.SystemContextIa32->Dr2,
+ SystemContext.SystemContextIa32->Dr3
+ );
+ InternalPrintMessage (
+ "DR6 - %08x, DR7 - %08x\n",
+ SystemContext.SystemContextIa32->Dr6,
+ SystemContext.SystemContextIa32->Dr7
+ );
+ InternalPrintMessage (
+ "GDTR - %08x %08x, IDTR - %08x %08x\n",
+ SystemContext.SystemContextIa32->Gdtr[0],
+ SystemContext.SystemContextIa32->Gdtr[1],
+ SystemContext.SystemContextIa32->Idtr[0],
+ SystemContext.SystemContextIa32->Idtr[1]
+ );
+ InternalPrintMessage (
+ "LDTR - %08x, TR - %08x\n",
+ SystemContext.SystemContextIa32->Ldtr,
+ SystemContext.SystemContextIa32->Tr
+ );
+ InternalPrintMessage (
+ "FXSAVE_STATE - %08x\n",
+ &SystemContext.SystemContextIa32->FxSaveState
+ );
+
+ //
+ // Find module image base and module entry point by RIP
+ //
+ ImageBase = FindModuleImageBase (SystemContext.SystemContextIa32->Eip, &EntryPoint);
+ if (ImageBase != 0) {
+ InternalPrintMessage (
+ " (ImageBase=%08x, EntryPoint=%08x) !!!!\n",
+ ImageBase,
+ EntryPoint
+ );
+ }
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S new file mode 100644 index 0000000000..8b3f6319b6 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S @@ -0,0 +1,467 @@ +#------------------------------------------------------------------------------
+#*
+#* Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+#* This program and the accompanying materials
+#* are licensed and made available under the terms and conditions of the BSD License
+#* which accompanies this distribution. The full text of the license may be found at
+#* http://opensource.org/licenses/bsd-license.php
+#*
+#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#* ExceptionHandlerAsm.S
+#*
+#* Abstract:
+#*
+#* IA32 CPU Exception Handler
+#
+#------------------------------------------------------------------------------
+
+
+
+
+
+#.MMX
+#.XMM
+
+ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
+ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
+
+#EXTRN ASM_PFX(mErrorCodeFlag):DWORD # Error code flags for exceptions
+
+.text
+
+#
+# exception handler stub table
+#
+Exception0Handle:
+ pushl $0
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception1Handle:
+ pushl $1
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception2Handle:
+ pushl $2
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception3Handle:
+ pushl $3
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception4Handle:
+ pushl $4
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception5Handle:
+ pushl $5
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception6Handle:
+ pushl $6
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception7Handle:
+ pushl $7
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception8Handle:
+ pushl $8
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception9Handle:
+ pushl $9
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception10Handle:
+ pushl $10
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception11Handle:
+ pushl $11
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception12Handle:
+ pushl $12
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception13Handle:
+ pushl $13
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception14Handle:
+ pushl $14
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception15Handle:
+ pushl $15
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception16Handle:
+ pushl $16
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception17Handle:
+ pushl $17
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception18Handle:
+ pushl $18
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception19Handle:
+ pushl $19
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception20Handle:
+ pushl $20
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception21Handle:
+ pushl $21
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception22Handle:
+ pushl $22
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception23Handle:
+ pushl $23
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception24Handle:
+ pushl $24
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception25Handle:
+ pushl $25
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception26Handle:
+ pushl $26
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception27Handle:
+ pushl $27
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception28Handle:
+ pushl $28
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception29Handle:
+ pushl $29
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception30Handle:
+ pushl $30
+ jmp ASM_PFX(CommonInterruptEntry)
+Exception31Handle:
+ pushl $31
+ jmp ASM_PFX(CommonInterruptEntry)
+
+#---------------------------------------;
+# CommonInterruptEntry ;
+#---------------------------------------;
+# The follow algorithm is used for the common interrupt routine.
+
+ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
+ASM_PFX(CommonInterruptEntry):
+ cli
+ #
+ # All interrupt handlers are invoked through interrupt gates, so
+ # IF flag automatically cleared at the entry point
+ #
+
+ #
+ # Calculate vector number
+ #
+ # Get the return address of call, actually, it is the
+ # address of vector number.
+ #
+ xchgl (%esp), %ecx
+ andl $0x0FFFF, %ecx
+ cmpl $32, %ecx # Intel reserved vector for exceptions?
+ jae NoErrorCode
+ bt %ecx, ASM_PFX(mErrorCodeFlag)
+ jc HasErrorCode
+
+NoErrorCode:
+
+ #
+ # Stack:
+ # +---------------------+
+ # + EFlags +
+ # +---------------------+
+ # + CS +
+ # +---------------------+
+ # + EIP +
+ # +---------------------+
+ # + ECX +
+ # +---------------------+ <-- ESP
+ #
+ # Registers:
+ # ECX - Vector Number
+ #
+
+ #
+ # Put Vector Number on stack
+ #
+ pushl %ecx
+
+ #
+ # Put 0 (dummy) error code on stack, and restore ECX
+ #
+ xorl %ecx, %ecx # ECX = 0
+ xchgl 4(%esp), %ecx
+
+ jmp ErrorCodeAndVectorOnStack
+
+HasErrorCode:
+
+ #
+ # Stack:
+ # +---------------------+
+ # + EFlags +
+ # +---------------------+
+ # + CS +
+ # +---------------------+
+ # + EIP +
+ # +---------------------+
+ # + Error Code +
+ # +---------------------+
+ # + ECX +
+ # +---------------------+ <-- ESP
+ #
+ # Registers:
+ # ECX - Vector Number
+ #
+
+ #
+ # Put Vector Number on stack and restore ECX
+ #
+ xchgl (%esp), %ecx
+
+ #
+ # Fall through to join main routine code
+ # at ErrorCodeAndVectorOnStack
+ #
+CommonInterruptEntry_al_0000:
+ jmp CommonInterruptEntry_al_0000
+
+ErrorCodeAndVectorOnStack:
+ pushl %ebp
+ movl %esp, %ebp
+
+ #
+ # Stack:
+ # +---------------------+
+ # + EFlags +
+ # +---------------------+
+ # + CS +
+ # +---------------------+
+ # + EIP +
+ # +---------------------+
+ # + Error Code +
+ # +---------------------+
+ # + Vector Number +
+ # +---------------------+
+ # + EBP +
+ # +---------------------+ <-- EBP
+ #
+
+ #
+ # Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+ # is 16-byte aligned
+ #
+ andl $0x0fffffff0, %esp
+ subl $12, %esp
+
+#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ pushl %eax
+ pushl %ecx
+ pushl %edx
+ pushl %ebx
+ leal 24(%ebp), %ecx
+ pushl %ecx # ESP
+ pushl (%ebp) # EBP
+ pushl %esi
+ pushl %edi
+
+#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+ movl %ss, %eax
+ pushl %eax
+ movzwl 16(%ebp), %eax
+ pushl %eax
+ movl %ds, %eax
+ pushl %eax
+ movl %es, %eax
+ pushl %eax
+ movl %fs, %eax
+ pushl %eax
+ movl %gs, %eax
+ pushl %eax
+
+#; UINT32 Eip;
+ movl 12(%ebp), %eax
+ pushl %eax
+
+#; UINT32 Gdtr[2], Idtr[2];
+ subl $8, %esp
+ sidt (%esp)
+ movl 2(%esp), %eax
+ xchgl (%esp), %eax
+ andl $0x0FFFF, %eax
+ movl %eax, 4(%esp)
+
+ subl $8, %esp
+ sgdt (%esp)
+ movl 2(%esp), %eax
+ xchgl (%esp), %eax
+ andl $0x0FFFF, %eax
+ movl %eax, 4(%esp)
+
+#; UINT32 Ldtr, Tr;
+ xorl %eax, %eax
+ str %ax
+ pushl %eax
+ sldt %ax
+ pushl %eax
+
+#; UINT32 EFlags;
+ movl 20(%ebp), %eax
+ pushl %eax
+
+#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ movl %cr4, %eax
+ orl $0x208, %eax
+ movl %eax, %cr4
+ pushl %eax
+ movl %cr3, %eax
+ pushl %eax
+ movl %cr2, %eax
+ pushl %eax
+ xorl %eax, %eax
+ pushl %eax
+ movl %cr0, %eax
+ pushl %eax
+
+#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+ movl %dr7, %eax
+ pushl %eax
+ movl %dr6, %eax
+ pushl %eax
+ movl %dr3, %eax
+ pushl %eax
+ movl %dr2, %eax
+ pushl %eax
+ movl %dr1, %eax
+ pushl %eax
+ movl %dr0, %eax
+ pushl %eax
+
+#; FX_SAVE_STATE_IA32 FxSaveState;
+ subl $512, %esp
+ movl %esp, %edi
+ .byte 0x0f, 0x0ae, 0x07 #fxsave [edi]
+
+#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+ cld
+
+#; UINT32 ExceptionData;
+ pushl 8(%ebp)
+
+#; Prepare parameter and call
+ movl %esp, %edx
+ pushl %edx
+ movl 4(%ebp), %edx
+ pushl %edx
+
+ #
+ # Call External Exception Handler
+ #
+ call ASM_PFX(CommonExceptionHandler)
+ addl $8, %esp
+
+ cli
+#; UINT32 ExceptionData;
+ addl $4, %esp
+
+#; FX_SAVE_STATE_IA32 FxSaveState;
+ movl %esp, %esi
+ .byte 0x0f, 0x0ae, 0x0e # fxrstor [esi]
+ addl $512, %esp
+
+#; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+#; Skip restoration of DRx registers to support in-circuit emualators
+#; or debuggers set breakpoint in interrupt/exception context
+ addl $24, %esp
+
+#; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ popl %eax
+ movl %eax, %cr0
+ addl $4, %esp # not for Cr1
+ popl %eax
+ movl %eax, %cr2
+ popl %eax
+ movl %eax, %cr3
+ popl %eax
+ movl %eax, %cr4
+
+#; UINT32 EFlags;
+ popl 20(%ebp)
+
+#; UINT32 Ldtr, Tr;
+#; UINT32 Gdtr[2], Idtr[2];
+#; Best not let anyone mess with these particular registers...
+ addl $24, %esp
+
+#; UINT32 Eip;
+ popl 12(%ebp)
+
+#; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+#; NOTE - modified segment registers could hang the debugger... We
+#; could attempt to insulate ourselves against this possibility,
+#; but that poses risks as well.
+#;
+ popl %gs
+ popl %fs
+ popl %es
+ popl %ds
+ popl 16(%ebp)
+ popl %ss
+
+#; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ popl %edi
+ popl %esi
+ addl $4, %esp # not for ebp
+ addl $4, %esp # not for esp
+ popl %ebx
+ popl %edx
+ popl %ecx
+ popl %eax
+
+ movl %ebp, %esp
+ popl %ebp
+ addl $8, %esp
+ iretl
+
+
+#---------------------------------------;
+# _GetTemplateAddressMap ;
+#----------------------------------------------------------------------------;
+#
+# Protocol prototype
+# GetTemplateAddressMap (
+# EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+# );
+#
+# Routine Description:
+#
+# Return address map of interrupt handler template so that C code can generate
+# interrupt table.
+#
+# Arguments:
+#
+#
+# Returns:
+#
+# Nothing
+#
+#
+# Input: [ebp][0] = Original ebp
+# [ebp][4] = Return address
+#
+# Output: Nothing
+#
+# Destroys: Nothing
+#-----------------------------------------------------------------------------;
+#-------------------------------------------------------------------------------------
+# AsmGetAddressMap (&AddressMap);
+#-------------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(GetTemplateAddressMap)
+ASM_PFX(GetTemplateAddressMap):
+
+ pushl %ebp
+ movl %esp,%ebp
+ pushal
+
+ movl 0x8(%ebp), %ebx
+ movl $Exception0Handle, (%ebx)
+ movl $(Exception1Handle - Exception0Handle), 0x4(%ebx)
+
+ popal
+ popl %ebp
+ ret
+
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm new file mode 100644 index 0000000000..dc71959bd1 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm @@ -0,0 +1,471 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; ExceptionHandlerAsm.Asm
+;
+; Abstract:
+;
+; IA32 CPU Exception Handler
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .686
+ .model flat,C
+
+;
+; CommonExceptionHandler()
+;
+CommonExceptionHandler PROTO C
+
+.data
+
+CommonEntryAddr DD CommonInterruptEntry
+
+EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
+
+.code
+
+;
+; exception handler stub table
+;
+Exception0Handle:
+ push 0
+ jmp dword ptr [CommonEntryAddr]
+Exception1Handle:
+ push 1
+ jmp dword ptr [CommonEntryAddr]
+Exception2Handle:
+ push 2
+ jmp dword ptr [CommonEntryAddr]
+Exception3Handle:
+ push 3
+ jmp dword ptr [CommonEntryAddr]
+Exception4Handle:
+ push 4
+ jmp dword ptr [CommonEntryAddr]
+Exception5Handle:
+ push 5
+ jmp dword ptr [CommonEntryAddr]
+Exception6Handle:
+ push 6
+ jmp dword ptr [CommonEntryAddr]
+Exception7Handle:
+ push 7
+ jmp dword ptr [CommonEntryAddr]
+Exception8Handle:
+ push 8
+ jmp dword ptr [CommonEntryAddr]
+Exception9Handle:
+ push 9
+ jmp dword ptr [CommonEntryAddr]
+Exception10Handle:
+ push 10
+ jmp dword ptr [CommonEntryAddr]
+Exception11Handle:
+ push 11
+ jmp dword ptr [CommonEntryAddr]
+Exception12Handle:
+ push 12
+ jmp dword ptr [CommonEntryAddr]
+Exception13Handle:
+ push 13
+ jmp dword ptr [CommonEntryAddr]
+Exception14Handle:
+ push 14
+ jmp dword ptr [CommonEntryAddr]
+Exception15Handle:
+ push 15
+ jmp dword ptr [CommonEntryAddr]
+Exception16Handle:
+ push 16
+ jmp dword ptr [CommonEntryAddr]
+Exception17Handle:
+ push 17
+ jmp dword ptr [CommonEntryAddr]
+Exception18Handle:
+ push 18
+ jmp dword ptr [CommonEntryAddr]
+Exception19Handle:
+ push 19
+ jmp dword ptr [CommonEntryAddr]
+Exception20Handle:
+ push 20
+ jmp dword ptr [CommonEntryAddr]
+Exception21Handle:
+ push 21
+ jmp dword ptr [CommonEntryAddr]
+Exception22Handle:
+ push 22
+ jmp dword ptr [CommonEntryAddr]
+Exception23Handle:
+ push 23
+ jmp dword ptr [CommonEntryAddr]
+Exception24Handle:
+ push 24
+ jmp dword ptr [CommonEntryAddr]
+Exception25Handle:
+ push 25
+ jmp dword ptr [CommonEntryAddr]
+Exception26Handle:
+ push 26
+ jmp dword ptr [CommonEntryAddr]
+Exception27Handle:
+ push 27
+ jmp dword ptr [CommonEntryAddr]
+Exception28Handle:
+ push 28
+ jmp dword ptr [CommonEntryAddr]
+Exception29Handle:
+ push 29
+ jmp dword ptr [CommonEntryAddr]
+Exception30Handle:
+ push 30
+ jmp dword ptr [CommonEntryAddr]
+Exception31Handle:
+ push 31
+ jmp dword ptr [CommonEntryAddr]
+
+;----------------------------------------------------------------------------;
+; CommonInterruptEntry ;
+;----------------------------------------------------------------------------;
+; The follow algorithm is used for the common interrupt routine.
+; Entry from each interrupt with a push eax and eax=interrupt number
+
+CommonInterruptEntry PROC PUBLIC
+ cli
+ ;
+ ; All interrupt handlers are invoked through interrupt gates, so
+ ; IF flag automatically cleared at the entry point
+ ;
+
+ ;
+ ; Calculate vector number
+ ;
+ ; Get the return address of call, actually, it is the
+ ; address of vector number.
+ ;
+ xchg ecx, [esp]
+ and ecx, 0FFFFh
+ cmp ecx, 32 ; Intel reserved vector for exceptions?
+ jae NoErrorCode
+ bt mErrorCodeFlag, ecx
+ jc HasErrorCode
+
+NoErrorCode:
+
+ ;
+ ; Stack:
+ ; +---------------------+
+ ; + EFlags +
+ ; +---------------------+
+ ; + CS +
+ ; +---------------------+
+ ; + EIP +
+ ; +---------------------+
+ ; + ECX +
+ ; +---------------------+ <-- ESP
+ ;
+ ; Registers:
+ ; ECX - Vector Number
+ ;
+
+ ;
+ ; Put Vector Number on stack
+ ;
+ push ecx
+
+ ;
+ ; Put 0 (dummy) error code on stack, and restore ECX
+ ;
+ xor ecx, ecx ; ECX = 0
+ xchg ecx, [esp+4]
+
+ jmp ErrorCodeAndVectorOnStack
+
+HasErrorCode:
+
+ ;
+ ; Stack:
+ ; +---------------------+
+ ; + EFlags +
+ ; +---------------------+
+ ; + CS +
+ ; +---------------------+
+ ; + EIP +
+ ; +---------------------+
+ ; + Error Code +
+ ; +---------------------+
+ ; + ECX +
+ ; +---------------------+ <-- ESP
+ ;
+ ; Registers:
+ ; ECX - Vector Number
+ ;
+
+ ;
+ ; Put Vector Number on stack and restore ECX
+ ;
+ xchg ecx, [esp]
+
+ ;
+ ; Fall through to join main routine code
+ ; at ErrorCodeAndVectorOnStack
+ ;
+@@:
+ jmp @B
+
+ErrorCodeAndVectorOnStack:
+ push ebp
+ mov ebp, esp
+
+ ;
+ ; Stack:
+ ; +---------------------+
+ ; + EFlags +
+ ; +---------------------+
+ ; + CS +
+ ; +---------------------+
+ ; + EIP +
+ ; +---------------------+
+ ; + Error Code +
+ ; +---------------------+
+ ; + Vector Number +
+ ; +---------------------+
+ ; + EBP +
+ ; +---------------------+ <-- EBP
+ ;
+
+ ;
+ ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+ ; is 16-byte aligned
+ ;
+ and esp, 0fffffff0h
+ sub esp, 12
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ push eax
+ push ecx
+ push edx
+ push ebx
+ lea ecx, [ebp + 6 * 4]
+ push ecx ; ESP
+ push dword ptr [ebp] ; EBP
+ push esi
+ push edi
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+ mov eax, ss
+ push eax
+ movzx eax, word ptr [ebp + 4 * 4]
+ push eax
+ mov eax, ds
+ push eax
+ mov eax, es
+ push eax
+ mov eax, fs
+ push eax
+ mov eax, gs
+ push eax
+
+;; UINT32 Eip;
+ mov eax, [ebp + 3 * 4]
+ push eax
+
+;; UINT32 Gdtr[2], Idtr[2];
+ sub esp, 8
+ sidt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0FFFFh
+ mov [esp+4], eax
+
+ sub esp, 8
+ sgdt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0FFFFh
+ mov [esp+4], eax
+
+;; UINT32 Ldtr, Tr;
+ xor eax, eax
+ str ax
+ push eax
+ sldt ax
+ push eax
+
+;; UINT32 EFlags;
+ mov eax, [ebp + 5 * 4]
+ push eax
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ mov eax, cr4
+ or eax, 208h
+ mov cr4, eax
+ push eax
+ mov eax, cr3
+ push eax
+ mov eax, cr2
+ push eax
+ xor eax, eax
+ push eax
+ mov eax, cr0
+ push eax
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+ mov eax, dr7
+ push eax
+ mov eax, dr6
+ push eax
+ mov eax, dr3
+ push eax
+ mov eax, dr2
+ push eax
+ mov eax, dr1
+ push eax
+ mov eax, dr0
+ push eax
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+ sub esp, 512
+ mov edi, esp
+ db 0fh, 0aeh, 07h ;fxsave [edi]
+
+;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+ cld
+
+;; UINT32 ExceptionData;
+ push dword ptr [ebp + 2 * 4]
+
+;; Prepare parameter and call
+ mov edx, esp
+ push edx
+ mov edx, dword ptr [ebp + 1 * 4]
+ push edx
+
+ ;
+ ; Call External Exception Handler
+ ;
+ mov eax, CommonExceptionHandler
+ call eax
+ add esp, 8
+
+ cli
+;; UINT32 ExceptionData;
+ add esp, 4
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+ mov esi, esp
+ db 0fh, 0aeh, 0eh ; fxrstor [esi]
+ add esp, 512
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+;; Skip restoration of DRx registers to support in-circuit emualators
+;; or debuggers set breakpoint in interrupt/exception context
+ add esp, 4 * 6
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ pop eax
+ mov cr0, eax
+ add esp, 4 ; not for Cr1
+ pop eax
+ mov cr2, eax
+ pop eax
+ mov cr3, eax
+ pop eax
+ mov cr4, eax
+
+;; UINT32 EFlags;
+ pop dword ptr [ebp + 5 * 4]
+
+;; UINT32 Ldtr, Tr;
+;; UINT32 Gdtr[2], Idtr[2];
+;; Best not let anyone mess with these particular registers...
+ add esp, 24
+
+;; UINT32 Eip;
+ pop dword ptr [ebp + 3 * 4]
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+;; NOTE - modified segment registers could hang the debugger... We
+;; could attempt to insulate ourselves against this possibility,
+;; but that poses risks as well.
+;;
+ pop gs
+ pop fs
+ pop es
+ pop ds
+ pop dword ptr [ebp + 4 * 4]
+ pop ss
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ pop edi
+ pop esi
+ add esp, 4 ; not for ebp
+ add esp, 4 ; not for esp
+ pop ebx
+ pop edx
+ pop ecx
+ pop eax
+
+ mov esp, ebp
+ pop ebp
+ add esp, 8
+ iretd
+
+CommonInterruptEntry ENDP
+
+;---------------------------------------;
+; _GetTemplateAddressMap ;
+;----------------------------------------------------------------------------;
+;
+; Protocol prototype
+; GetTemplateAddressMap (
+; EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+; );
+;
+; Routine Description:
+;
+; Return address map of interrupt handler template so that C code can generate
+; interrupt table.
+;
+; Arguments:
+;
+;
+; Returns:
+;
+; Nothing
+;
+;
+; Input: [ebp][0] = Original ebp
+; [ebp][4] = Return address
+;
+; Output: Nothing
+;
+; Destroys: Nothing
+;-----------------------------------------------------------------------------;
+GetTemplateAddressMap proc near public
+ push ebp ; C prolog
+ mov ebp, esp
+ pushad
+
+ mov ebx, dword ptr [ebp+08h]
+ mov dword ptr [ebx], Exception0Handle
+ mov dword ptr [ebx+4h], Exception1Handle - Exception0Handle
+
+ popad
+ pop ebp
+ ret
+GetTemplateAddressMap ENDP
+
+END
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