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-rw-r--r--UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbExceptionHandle.S51
1 files changed, 51 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbExceptionHandle.S b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbExceptionHandle.S
new file mode 100644
index 0000000000..4395b574f5
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbExceptionHandle.S
@@ -0,0 +1,51 @@
+#------------------------------------------------------------------------------
+#
+# TLB refill exception handler
+#
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#-----------------------------------------------------------------------------
+
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX(HandleTlbRefillStart)
+ASM_GLOBAL ASM_PFX(HandleTlbRefillEnd)
+
+#
+# Refill the page table.
+# @param VOID
+# @retval VOID
+#
+ASM_PFX(HandleTlbRefillStart):
+ csrwr $t0, LOONGARCH_CSR_TLBRSAVE
+ csrrd $t0, LOONGARCH_CSR_PWCTL1
+ srli.d $t0, $t0, 18
+ andi $t0, $t0, 0x3F
+ bnez $t0, Level5
+ csrrd $t0, LOONGARCH_CSR_PWCTL1
+ srli.d $t0, $t0, 6
+ andi $t0, $t0, 0x3F
+ bnez $t0, Level4
+ csrrd $t0, LOONGARCH_CSR_PGD
+ b Level3
+Level5:
+ csrrd $t0, LOONGARCH_CSR_PGD
+ lddir $t0, $t0, 4 #Put pud BaseAddress into T0
+ lddir $t0, $t0, 3 #Put pud BaseAddress into T0
+ b Level3
+Level4:
+ csrrd $t0, LOONGARCH_CSR_PGD
+ lddir $t0, $t0, 3 #Put pud BaseAddress into T0
+Level3:
+ lddir $t0, $t0, 2 #Put pmd BaseAddress into T0
+ lddir $t0, $t0, 1 #Put pte BaseAddress into T0
+ ldpte $t0, 0
+ ldpte $t0, 1
+ tlbfill // refill hi, lo0, lo1
+ csrrd $t0, LOONGARCH_CSR_TLBRSAVE
+ ertn
+ASM_PFX(HandleTlbRefillEnd):
+
+ .end