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-rw-r--r--UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf32
-rw-r--r--UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb60
2 files changed, 92 insertions, 0 deletions
diff --git a/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf b/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf
new file mode 100644
index 0000000000..2450bf6a7e
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf
@@ -0,0 +1,32 @@
+## @file
+# Reset Vector
+#
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetVector
+ FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.1
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ Vtf.nasmb
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb b/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb
new file mode 100644
index 0000000000..5aa733ea59
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb
@@ -0,0 +1,60 @@
+;------------------------------------------------------------------------------
+; @file
+; First code exectuted by processor after resetting.
+;
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+BITS 16
+
+ALIGN 16 ; 0xffffffd0
+
+applicationProcessorEntryPoint:
+;
+; Application Processors entry point
+;
+; GenFv generates code aligned on a 4k boundary which will jump to this
+; location. (0xffffffd0) This allows the Local APIC Startup IPI to be
+; used to wake up the application processors.
+;
+ jmp short resetVector
+
+ALIGN 16 ; 0xffffffe0
+
+peiCoreEntryPoint:
+;
+; PEI Core entry point
+;
+; GenFv fills the address of the PEI Core into this location
+;
+ DD 0x12345678
+
+ALIGN 16 ; 0xfffffff0
+
+resetVector:
+;
+; Reset Vector
+;
+; This is where the processor will begin execution
+;
+ nop
+ nop
+ jmp near $
+
+ALIGN 8
+
+ApStartupSegment:
+ DD 0x12345678
+
+BootFvBaseAddress:
+ DD 0x12345678
+
+ALIGN 16 ; 0x100000000