diff options
Diffstat (limited to 'UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c')
| -rw-r--r-- | UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c index 1dafce19cb..18f4a0ba3f 100644 --- a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c +++ b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c @@ -16,7 +16,7 @@ **/
UINT32
AcquireSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
@@ -30,13 +30,11 @@ AcquireSpiBar0 ( **/
VOID
ReleaseSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
}
-
-
/**
This function is to enable/disable BIOS Write Protect in SMM phase.
@@ -45,22 +43,22 @@ ReleaseSpiBar0 ( **/
VOID
CpuSmmDisableBiosWriteProtect (
- IN BOOLEAN EnableSmmSts
+ IN BOOLEAN EnableSmmSts
)
{
- UINT32 Data32;
+ UINT32 Data32;
- if(EnableSmmSts){
+ if (EnableSmmSts) {
//
// Disable BIOS Write Protect in SMM phase.
//
- Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
+ Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
} else {
//
// Enable BIOS Write Protect in SMM phase
//
- Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
+ Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
}
@@ -70,7 +68,6 @@ CpuSmmDisableBiosWriteProtect ( Data32 = MmioRead32 (0xFED30880);
}
-
/**
This function is a hook for Spi to disable BIOS Write Protect.
@@ -84,11 +81,10 @@ CpuSmmDisableBiosWriteProtect ( EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
)
{
-
//
// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
//
@@ -116,15 +112,14 @@ DisableBiosWriteProtect ( VOID
EFIAPI
EnableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
)
{
-
//
// Disable the access to the BIOS space for write cycles
//
- MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));
+ MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
if (CpuSmmBwp != 0) {
CpuSmmDisableBiosWriteProtect (FALSE);
@@ -142,16 +137,18 @@ EnableBiosWriteProtect ( **/
UINT8
SaveAndDisableSpiPrefetchCache (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
- UINT8 BiosCtlSave;
+ UINT8 BiosCtlSave;
BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
- MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \
- (UINT32) (~B_SPI_BCR_SRC), \
- (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC));
+ MmioAndThenOr32 (
+ PchSpiBase + R_SPI_BCR, \
+ (UINT32)(~B_SPI_BCR_SRC), \
+ (UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
+ );
return BiosCtlSave;
}
@@ -165,8 +162,8 @@ SaveAndDisableSpiPrefetchCache ( **/
VOID
SetSpiBiosControlRegister (
- IN UINTN PchSpiBase,
- IN UINT8 BiosCtlValue
+ IN UINTN PchSpiBase,
+ IN UINT8 BiosCtlValue
)
{
MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);
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