diff options
Diffstat (limited to 'Vlv2TbltDevicePkg/Library/MultiPlatformLib')
14 files changed, 2141 insertions, 0 deletions
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c new file mode 100644 index 0000000000..1fc731205b --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c @@ -0,0 +1,426 @@ +/** @file
+ Clock generator setting for multiplatform.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <BoardClkGens.h>
+#include <Guid/SetupVariable.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseMemoryLib.h>
+
+#ifndef __GNUC__
+#pragma optimize( "", off )
+#endif
+
+#define CLKGEN_EN 1
+#define EFI_DEBUG 1
+
+CLOCK_GENERATOR_DETAILS mSupportedClockGeneratorTable[] =
+{
+ { ClockGeneratorCk410, CK410_GENERATOR_ID , CK410_GENERATOR_SPREAD_SPECTRUM_BYTE, CK410_GENERATOR_SPREAD_SPECTRUM_BIT },
+ { ClockGeneratorCk505, CK505_GENERATOR_ID , CK505_GENERATOR_SPREAD_SPECTRUM_BYTE, CK505_GENERATOR_SPREAD_SPECTRUM_BIT }
+};
+
+/**
+ Configure the clock generator using the SMBUS PPI services.
+
+ This function performs a block write, and dumps debug information.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param ClockType Clock generator's model name.
+ @param ClockAddress SMBUS address of clock generator.
+ @param ConfigurationTableLength Length of configuration table.
+ @param ConfigurationTable Pointer of configuration table.
+
+ @retval EFI_SUCCESS - Operation success.
+
+**/
+EFI_STATUS
+ConfigureClockGenerator (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_SMBUS_PPI *SmbusPpi,
+ IN CLOCK_GENERATOR_TYPE ClockType,
+ IN UINT8 ClockAddress,
+ IN UINTN ConfigurationTableLength,
+ IN OUT UINT8 *ConfigurationTable
+ )
+{
+
+ EFI_STATUS Status;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
+ UINTN Length;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+#if CLKGEN_CONFIG_EXTRA
+ UINT8 j;
+#endif
+
+ //
+ // Verify input arguments
+ //
+ ASSERT_EFI_ERROR (ConfigurationTableLength >= 6);
+ ASSERT_EFI_ERROR (ConfigurationTableLength <= MAX_CLOCK_GENERATOR_BUFFER_LENGTH);
+ ASSERT_EFI_ERROR (ClockType < ClockGeneratorMax);
+ ASSERT_EFI_ERROR (ConfigurationTable != NULL);
+
+ //
+ // Read the clock generator
+ //
+ SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
+ Length = sizeof (Buffer);
+ Command = 0;
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadBlock,
+ FALSE,
+ &Length,
+ Buffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+#ifdef EFI_DEBUG
+ {
+ UINT8 i;
+ for (i = 0; i < sizeof (Buffer); i++) {
+ DEBUG((EFI_D_ERROR, "CK505 default Clock Generator Byte %d: %x\n", i, Buffer[i]));
+ }
+#if CLKGEN_EN
+ for (i = 0; i < ConfigurationTableLength; i++) {
+ DEBUG((EFI_D_ERROR, "BIOS structure Clock Generator Byte %d: %x\n", i, ConfigurationTable[i]));
+ }
+#endif
+ }
+#endif
+
+ DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is %x, expecting %x\n", mSupportedClockGeneratorTable[ClockType].ClockId,(Buffer[7]&0xF)));
+
+ //
+ // Program clock generator
+ //
+ Command = 0;
+#if CLKGEN_EN
+#if CLKGEN_CONFIG_EXTRA
+ for (j = 0; j < ConfigurationTableLength; j++) {
+ Buffer[j] = ConfigurationTable[j];
+ }
+
+ Buffer[30] = 0x00;
+
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteBlock,
+ FALSE,
+ &Length,
+ Buffer
+ );
+#else
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteBlock,
+ FALSE,
+ &ConfigurationTableLength,
+ ConfigurationTable
+ );
+#endif // CLKGEN_CONFIG_EXTRA
+#else
+ ConfigurationTable[4] = (ConfigurationTable[4] & 0x3) | (Buffer[4] & 0xFC);
+ Command = 4;
+ Length = 1;
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusWriteBlock,
+ FALSE,
+ &Length,
+ &ConfigurationTable[4]
+ );
+#endif //CLKGEN_EN
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Dump contents after write
+ //
+ #ifdef EFI_DEBUG
+ {
+ UINT8 i;
+ SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
+ Length = sizeof (Buffer);
+ Command = 0;
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadBlock,
+ FALSE,
+ &Length,
+ Buffer
+ );
+
+ for (i = 0; i < ConfigurationTableLength; i++) {
+ DEBUG((EFI_D_ERROR, "Clock Generator Byte %d: %x\n", i, Buffer[i]));
+ }
+ }
+ #endif
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure the clock generator using the SMBUS PPI services.
+
+ This function performs a block write, and dumps debug information.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param ClockType Clock generator's model name.
+ @param ClockAddress SMBUS address of clock generator.
+ @param ConfigurationTableLength Length of configuration table.
+ @param ConfigurationTable Pointer of configuration table.
+
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+UINT8
+ReadClockGeneratorID (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_SMBUS_PPI *SmbusPpi,
+ IN UINT8 ClockAddress
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ UINT8 Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];
+ UINTN Length;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+
+ //
+ // Read the clock generator
+ //
+ SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
+ Length = sizeof (Buffer);
+ Command = 0;
+ Status = SmbusPpi->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadBlock,
+ FALSE,
+ &Length,
+ Buffer
+ );
+
+ //
+ // Sanity check that the requested clock type is present in our supported clocks table
+ //
+ DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is 0x%x\n", Buffer[7]));
+
+ return (Buffer[7]);
+}
+
+/**
+ Configure the clock generator to enable free-running operation. This keeps
+ the clocks from being stopped when the system enters C3 or C4.
+
+ @param None
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+ConfigurePlatformClocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *SmbusPpi
+ )
+{
+ //
+ // Comment it out for now
+ // Not supported by Hybrid model.
+ //
+ EFI_STATUS Status;
+ UINT8 *ConfigurationTable;
+
+ CLOCK_GENERATOR_TYPE ClockType = ClockGeneratorCk505;
+ UINT8 ConfigurationTable_Desktop[] = CLOCK_GENERATOR_SETTINGS_DESKTOP;
+ UINT8 ConfigurationTable_Mobile[] = CLOCK_GENERATOR_SETTINGS_MOBILE;
+ UINT8 ConfigurationTable_Tablet[] = CLOCK_GENERATOR_SEETINGS_TABLET;
+
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
+ BOOLEAN EnableSpreadSpectrum;
+ UINT8 ClockGenID=0;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ UINTN Length;
+ EFI_SMBUS_DEVICE_COMMAND Command;
+ EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
+ UINT8 Data;
+
+ UINT8 ClockAddress = CLOCK_GENERATOR_ADDRESS;
+ UINTN VariableSize;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+
+ //
+ // Obtain Platform Info from HOB.
+ //
+ Status = GetPlatformInfoHob ((CONST EFI_PEI_SERVICES **) PeiServices, &PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG((EFI_D_ERROR, "PlatformInfo protocol is working in ConfigurePlatformClocks()...%x\n",PlatformInfoHob->PlatformFlavor));
+
+ //
+ // Locate SMBUS PPI
+ //
+ Status = (**PeiServices).LocatePpi (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &gEfiPeiSmbusPpiGuid,
+ 0,
+ NULL,
+ &SmbusPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Data = 0;
+ SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;
+ Length = 1;
+ Command = 0x87; //Control Register 7 Vendor ID Check
+ Status = ((EFI_PEI_SMBUS_PPI *) SmbusPpi)->Execute (
+ PeiServices,
+ SmbusPpi,
+ SlaveAddress,
+ Command,
+ EfiSmbusReadByte,
+ FALSE,
+ &Length,
+ &Data
+ );
+
+ if (EFI_ERROR (Status) || ((Data & 0x0F) != CK505_GENERATOR_ID)) {
+ DEBUG((EFI_D_ERROR, "Clock Generator CK505 Not Present, vendor ID on board is %x\n",(Data & 0x0F)));
+ return EFI_SUCCESS;
+}
+ ClockGenID = Data & 0x0F;
+
+ EnableSpreadSpectrum = FALSE;
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+
+ Status = (*PeiServices)->LocatePpi (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &Variable
+ );
+ //
+ // Use normal setup default from NVRAM variable,
+ // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
+ //
+ VariableSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = Variable->GetVariable (Variable,
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration);
+
+ if(!EFI_ERROR (Status)){
+ EnableSpreadSpectrum = SystemConfiguration.EnableClockSpreadSpec;
+ }
+
+ //
+ // Perform platform-specific intialization dependent upon Board ID:
+ //
+ DEBUG((EFI_D_ERROR, "board id is %x, platform id is %x\n",PlatformInfoHob->BoardId,PlatformInfoHob->PlatformFlavor));
+
+
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_MINNOW2:
+ default:
+ switch(PlatformInfoHob->PlatformFlavor) {
+ case FlavorTablet:
+ ConfigurationTable = ConfigurationTable_Tablet;
+ Length = sizeof (ConfigurationTable_Tablet);
+ break;
+ case FlavorMobile:
+ ConfigurationTable = ConfigurationTable_Mobile;
+ Length = sizeof (ConfigurationTable_Mobile);
+ break;
+ case FlavorDesktop:
+ default:
+ ConfigurationTable = ConfigurationTable_Desktop;
+ Length = sizeof (ConfigurationTable_Desktop);
+ break;
+ }
+ break;
+ }
+
+ //
+ // Perform common clock initialization:
+ //
+ // Program Spread Spectrum function.
+ //
+ if (EnableSpreadSpectrum)
+ {
+ ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] |= mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset;
+ } else {
+ ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] &= ~(mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset);
+ }
+
+
+#if CLKGEN_EN
+ Status = ConfigureClockGenerator (PeiServices, SmbusPpi, ClockType, ClockAddress, Length, ConfigurationTable);
+ ASSERT_EFI_ERROR (Status);
+#endif // CLKGEN_EN
+ return EFI_SUCCESS;
+}
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiSmbusPpiGuid,
+ ConfigurePlatformClocks
+ }
+};
+
+EFI_STATUS
+InstallPlatformClocksNotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "InstallPlatformClocksNotify()...\n"));
+
+ Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+ return EFI_SUCCESS;
+
+}
+
+#ifndef __GNUC__
+#pragma optimize( "", on )
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h new file mode 100644 index 0000000000..4ec5b881ab --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h @@ -0,0 +1,260 @@ +/**@file
+ Clock generator setting for multiplatform.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARD_CLK_GEN_H_
+#define _BOARD_CLK_GEN_H_
+
+#include <PiPei.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmbusLib.h>
+#include <Ppi/Smbus.h>
+#include <IndustryStandard/SmBus.h>
+#include <Guid/PlatformInfo.h>
+
+
+#define CLOCK_GENERATOR_ADDRESS 0xd2
+
+#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
+#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
+#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}
+
+typedef enum {
+ ClockGeneratorCk410,
+ ClockGeneratorCk505,
+ ClockGeneratorMax
+} CLOCK_GENERATOR_TYPE;
+
+typedef struct {
+ CLOCK_GENERATOR_TYPE ClockType;
+ UINT8 ClockId;
+ UINT8 SpreadSpectrumByteOffset;
+ UINT8 SpreadSpectrumBitOffset;
+} CLOCK_GENERATOR_DETAILS;
+
+#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
+
+//
+// CK410 Definitions
+//
+#define CK410_GENERATOR_ID 0x65
+#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE 1
+#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
+#define CK410_GENERATOR_CLOCK_FREERUN_BYTE 4
+#define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)
+
+//
+// CK505 Definitions
+//
+#define VF_CK505_GENERATOR_ID 0x5
+#define CK505_GENERATOR_ID 0x5 // Confirmed readout is 5
+#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE 4
+#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)
+#define CK505_GENERATOR_PERCENT_SPREAD_BYTE 1
+#define CK505_GENERATOR_PERCENT_MASK ~(0xE)
+#define CK505_GENERATOR_PERCENT_250_VALUE 0xC
+#define CK505_GENERATOR_PERCENT_050_VALUE 0x4
+#define CK505_GENERATOR_PERCENT_000_VALUE 0x2
+
+//
+// IDT Definitions
+//
+#define IDT_GENERATOR_ID_REVA 0x1 //IDT Rev A
+#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE 0
+#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
+#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE 5
+#define IDTRevA_GENERATOR_PERCENT_250_VALUE 0xF
+#define IDTRevA_GENERATOR_PERCENT_050_VALUE 0x3
+#define IDTRevA_GENERATOR_PERCENT_000_VALUE 0xE
+#define IDTRevA_GENERATOR_PERCENT_MASK ~(0xF)
+
+#define IDT_GENERATOR_ID_REVB 0x11 //IDT RevB
+#define IDT_GENERATOR_ID_REVD 0x21 //IDT RevD
+
+//
+// CLOCK CONTROLLER
+// SmBus address to read DIMM SPD
+//
+#define SMBUS_BASE_ADDRESS 0xEFA0
+#define SMBUS_BUS_DEV_FUNC 0x1F0300
+#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4
+#define SMBUS_ADDR_CH_A_1 0xA0
+#define SMBUS_ADDR_CH_A_2 0xA2
+#define SMBUS_ADDR_CH_B_1 0xA4
+#define SMBUS_ADDR_CH_B_2 0xA6
+
+//
+// Bits for FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0)
+//
+#define B_ICH_LPC_FWH_BIOS_DEC_F0 0x4000
+#define B_ICH_LPC_FWH_BIOS_DEC_E0 0x1000
+#define B_ICH_LPC_FWH_BIOS_DEC_E8 0x2000
+#define B_ICH_LPC_FWH_BIOS_LEG_F 0x0080
+#define B_ICH_LPC_FWH_BIOS_LEG_E 0x0040
+
+
+//
+// An arbitrary maximum length for clock generator buffers
+//
+#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH 0x20
+
+//
+// SmBus Bus Device Function and Register Definitions
+//
+#define SMBUS_BUS_NUM 0
+#define SMBUS_DEV_NUM 31
+#define SMBUS_FUNC_NUM 3
+#define SMBUS_BUS_DEV_FUNC_NUM \
+ SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)
+
+//
+//ICH7: SMBus I/O Space Equates;
+//
+#define BIT_SLAVE_ADDR BIT00
+#define BIT_COMMAND BIT01
+#define BIT_DATA BIT02
+#define BIT_COUNT BIT03
+#define BIT_WORD BIT04
+#define BIT_CONTROL BIT05
+#define BIT_PEC BIT06
+#define BIT_READ BIT07
+#define SMBUS_IO_READ_BIT BIT00
+
+
+#define SMB_CMD_QUICK 0x00
+#define SMB_CMD_BYTE 0x04
+#define SMB_CMD_BYTE_DATA 0x08
+#define SMB_CMD_WORD_DATA 0x0C
+#define SMB_CMD_PROCESS_CALL 0x10
+#define SMB_CMD_BLOCK 0x14
+#define SMB_CMD_I2C_READ 0x18
+#define SMB_CMD_RESERVED 0x1c
+
+#define HST_STS_BYTE_DONE 0x80
+#define SMB_HST_STS 0x000
+#define SMB_HST_CNT 0x002
+#define SMB_HST_CMD 0x003
+#define SMB_HST_ADD 0x004
+#define SMB_HST_DAT_0 0x005
+#define SMB_HST_DAT_1 0x006
+#define SMB_HST_BLK_DAT 0x007
+#define SMB_PEC 0x008
+#define SMB_RCV_SLVA 0x009
+#define SMB_SLV_DAT 0x00A
+#define SMB_AUX_STS 0x00C
+#define SMB_AUX_CTL 0x00D
+#define SMB_SMLINK_PIN_CTL 0x00E
+#define SMB_SMBUS_PIN_CTL 0x00F
+#define SMB_SLV_STS 0x010
+#define SMB_SLV_CMD 0x011
+#define SMB_NTFY_DADDR 0x014
+#define SMB_NTFY_DLOW 0x016
+#define SMB_NTFY_DHIGH 0x017
+
+//
+// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below
+//
+#define R_COMMAND 0x04 // PCI Command Register, 16bit
+#define B_IOSE 0x01 // RW
+#define R_BASE_ADDRESS 0x20 // PCI BAR for SMBus I/O
+#define B_BASE_ADDRESS 0xFFE0 // RW
+#define R_HOST_CONFIGURATION 0x40 // SMBus Host Configuration Register
+#define B_HST_EN 0x01 // RW
+#define B_SMB_SMI_EN 0x02 // RW
+#define B_I2C_EN 0x04 // RW
+//
+// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below
+//
+#define HOST_STATUS_REGISTER 0x00 // Host Status Register R/W
+#define HST_STS_HOST_BUSY 0x01 // RO
+#define HST_STS_INTR 0x02 // R/WC
+#define HST_STS_DEV_ERR 0x04 // R/WC
+#define HST_STS_BUS_ERR 0x08 // R/WC
+#define HST_STS_FAILED 0x10 // R/WC
+#define SMBUS_B_SMBALERT_STS 0x20 // R/WC
+#define HST_STS_INUSE 0x40 // R/WC
+#define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC
+#define SMBUS_B_HSTS_ALL 0xFF // R/WC
+#define HOST_CONTROL_REGISTER 0x02 // Host Control Register R/W
+#define HST_CNT_INTREN 0x01 // RW
+#define HST_CNT_KILL 0x02 // RW
+#define SMBUS_B_SMB_CMD 0x1C // RW
+#define SMBUS_V_SMB_CMD_QUICK 0x00
+#define SMBUS_V_SMB_CMD_BYTE 0x04
+#define SMBUS_V_SMB_CMD_BYTE_DATA 0x08
+#define SMBUS_V_SMB_CMD_WORD_DATA 0x0C
+#define SMBUS_V_SMB_CMD_PROCESS_CALL 0x10
+#define SMBUS_V_SMB_CMD_BLOCK 0x14
+#define SMBUS_V_SMB_CMD_IIC_READ 0x18
+#define SMBUS_B_LAST_BYTE 0x20 // WO
+#define HST_CNT_START 0x40 // WO
+#define HST_CNT_PEC_EN 0x80 // RW
+#define HOST_COMMAND_REGISTER 0x03 // Host Command Register R/W
+#define XMIT_SLAVE_ADDRESS_REGISTER 0x04 // Transmit Slave Address Register R/W
+#define SMBUS_B_RW_SEL 0x01 // RW
+#define SMBUS_B_ADDRESS 0xFE // RW
+#define HOST_DATA_0_REGISTER 0x05 // Data 0 Register R/W
+#define HOST_DATA_1_REGISTER 0x06 // Data 1 Register R/W
+#define HOST_BLOCK_DATA_BYTE_REGISTER 0x07 // Host Block Data Register R/W
+#define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W
+#define SMBUS_R_RSA 0x09 // Receive Slave Address Register R/W
+#define SMBUS_B_SLAVE_ADDR 0x7F // RW
+#define SMBUS_R_SD 0x0A // Receive Slave Data Register R/W
+#define SMBUS_R_AUXS 0x0C // Auxiliary Status Register R/WC
+#define SMBUS_B_CRCE 0x01 //R/WC
+#define AUXILIARY_CONTROL_REGISTER 0x0D // Auxiliary Control Register R/W
+#define SMBUS_B_AAC 0x01 //R/W
+#define SMBUS_B_E32B 0x02 //R/W
+#define SMBUS_R_SMLC 0x0E // SMLINK Pin Control Register R/W
+#define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO
+#define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO
+#define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW
+#define SMBUS_R_SMBC 0x0F // SMBus Pin Control Register R/W
+#define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO
+#define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO
+#define SMBUS_B_SMBCLK_CTL 0x04 // RW
+#define SMBUS_R_SSTS 0x10 // Slave Status Register R/WC
+#define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC
+#define SMBUS_R_SCMD 0x11 // Slave Command Register R/W
+#define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W
+#define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W
+#define SMBUS_B_SMBALERT_DIS 0x04 // R/W
+#define SMBUS_R_NDA 0x14 // Notify Device Address Register RO
+#define SMBUS_B_DEVICE_ADDRESS 0xFE // RO
+#define SMBUS_R_NDLB 0x16 // Notify Data Low Byte Register RO
+#define SMBUS_R_NDHB 0x17 // Notify Data High Byte Register RO
+#define BUS_TRIES 3 // How many times to retry on Bus Errors
+#define SMBUS_NUM_RESERVED 21 // Number of device addresses that are
+ // reserved by the SMBus spec.
+#define SMBUS_ADDRESS_ARP 0xC2 >> 1
+#define SMBUS_DATA_PREPARE_TO_ARP 0x01
+#define SMBUS_DATA_RESET_DEVICE 0x02
+#define SMBUS_DATA_GET_UDID_GENERAL 0x03
+#define SMBUS_DATA_ASSIGN_ADDRESS 0x04
+#define SMBUS_GET_UDID_LENGTH 17 // 16 byte UDID + 1 byte address
+
+
+EFI_STATUS
+ConfigurePlatformClocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *SmbusPpi
+ );
+
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c new file mode 100644 index 0000000000..092d3f3783 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c @@ -0,0 +1,535 @@ +/** @file
+ Gpio setting for multiplatform..
+
+ Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <BoardGpios.h>
+#include <Guid/SetupVariable.h>
+
+//
+//AlpineValley platform ocde begin
+//
+#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48
+#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C
+#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50
+#define AV_SC_REG_GPIOS_MUXES_EN0 0x54
+#define AV_SC_REG_GPIOS_MUXES_EN1 0x58
+#define AV_SC_REG_GPIOS_MUXES_EN2 0x5C
+//
+//AlpineValley platform code end
+//
+
+EFI_GUID gPeiSmbusPpiGuid = EFI_PEI_SMBUS_PPI_GUID;
+
+/**
+ @param None
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+ConfigurePlatformSysCtrlGpio (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *SmbusPpi
+ )
+{
+ //
+ //AlpineValley platform code begin
+ //
+ // Initialize GPIO Settings:
+ //
+ UINT32 Status;
+ EFI_PLATFORM_INFO_HOB *PlatformInfoHob;
+
+ DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));
+
+ //
+ // Obtain Platform Info from HOB.
+ //
+ Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // The GPIO settings are dependent upon the platform. Obtain the Board ID through
+ // the EC to determine the current platform.
+ //
+ DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));
+
+
+
+ Status = (**PeiServices).LocatePpi (
+ (const EFI_PEI_SERVICES **)PeiServices,
+ &gPeiSmbusPpiGuid,
+ 0,
+ NULL,
+ (void **)&SmbusPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Select/modify the GPIO initialization data based on the Board ID.
+ //
+ switch (PlatformInfoHob->BoardId)
+ {
+ default:
+ Status = EFI_SUCCESS;
+
+ //
+ // Do nothing for other RVP boards.
+ //
+ break;
+ }
+ return Status;
+}
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiSmbusPpiGuid,
+ ConfigurePlatformSysCtrlGpio
+ }
+};
+
+EFI_STATUS
+InstallPlatformSysCtrlGPIONotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));
+
+ Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+ return EFI_SUCCESS;
+
+}
+
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
+
+/**
+ Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
+ @param BoardId BoardId ID as determined through the EC.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+MultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
+ UINTN VarSize;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));
+
+ //
+ // Select/modify the GPIO initialization data based on the Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+
+ case BOARD_ID_MINNOW2: // Minnow2
+
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (void **)&PeiReadOnlyVarPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ VarSize = sizeof (SYSTEM_CONFIGURATION);
+ Status = PeiReadOnlyVarPpi->GetVariable (
+ PeiReadOnlyVarPpi,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VarSize,
+ &SystemConfiguration
+ );
+
+ if (SystemConfiguration.GpioWakeCapability == 1) {
+ PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;
+ }
+ else {
+ PlatformInfoHob->PlatformCfioData = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;
+ }
+
+ PlatformInfoHob->PlatformGpioData_NC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];
+ PlatformInfoHob->PlatformGpioData_SC = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];
+ PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];
+ break;
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+UINT32
+GPIORead32 (
+ IN UINT32 mmio_conf
+ )
+{
+ UINT32 conf_val;
+ UINT32 i;
+ conf_val = MmioRead32(mmio_conf);
+ for(i=0;i<5;i++){
+ if(conf_val == 0xffffffff)
+ conf_val = MmioRead32(mmio_conf);
+ else
+ break;
+ }
+
+ return conf_val;
+}
+
+/**
+
+ Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters
+
+ @param Gpio_Mmio_Offset GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.
+ @param Gpio_Pin_Num Pin numbers to config for each GPIO clusters.
+ @param Gpio_Conf_Data GPIO_CONF_PAD_INIT data array for each GPIO clusters.
+
+**/
+VOID
+InternalGpioConfig (
+ IN UINT32 Gpio_Mmio_Offset,
+ IN UINT32 Gpio_Pin_Num,
+ GPIO_CONF_PAD_INIT* Gpio_Conf_Data
+ )
+{
+ UINT32 index;
+ UINT32 mmio_conf0;
+ UINT32 mmio_padval;
+ PAD_CONF0 conf0_val;
+ PAD_VAL pad_val;
+
+ //
+ // GPIO WELL -- Memory base registers
+ //
+
+ // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
+ // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
+ //
+ for(index=0; index < Gpio_Pin_Num; index++)
+ {
+ //
+ // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
+ //
+ mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
+ mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
+
+#ifdef EFI_DEBUG
+ DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
+
+#endif
+ DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
+ Gpio_Conf_Data[index].usage,
+ Gpio_Conf_Data[index].func,
+ Gpio_Conf_Data[index].int_type,
+ Gpio_Conf_Data[index].pull,
+ mmio_conf0));
+
+ //
+ // Step 1: PadVal Programming.
+ //
+ pad_val.dw = GPIORead32(mmio_padval);
+
+ //
+ // Config PAD_VAL only for GPIO (Non-Native) Pin
+ //
+ if(Native != Gpio_Conf_Data[index].usage)
+ {
+ pad_val.dw &= ~0x6; // Clear bits 1:2
+ pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
+
+ //
+ // set GPO default value
+ //
+ if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
+ {
+ pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
+ }
+ }
+
+
+ DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
+
+ MmioWrite32(mmio_padval, pad_val.dw);
+
+ //
+ // Step 2: CONF0 Programming
+ // Read GPIO default CONF0 value, which is assumed to be default value after reset.
+ //
+ conf0_val.dw = GPIORead32(mmio_conf0);
+
+ //
+ // Set Function #
+ //
+ conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
+
+ if(GPO == Gpio_Conf_Data[index].usage)
+ {
+ //
+ // If used as GPO, then internal pull need to be disabled.
+ //
+ conf0_val.r.Pull_assign = 0; // Non-pull
+ }
+ else
+ {
+ //
+ // Set PullUp / PullDown
+ //
+ if(P_20K_H == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x1; // PullUp
+ conf0_val.r.Pull_strength = 0x2;// 20K
+ }
+ else if(P_20K_L == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x2; // PullDown
+ conf0_val.r.Pull_strength = 0x2;// 20K
+ }
+ else if(P_10K_H == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x1; // PullUp
+ conf0_val.r.Pull_strength = 0x1;// 10K
+ }
+ else if(P_10K_L == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x2; // PullDown
+ conf0_val.r.Pull_strength = 0x1;// 10K
+ }
+ else if(P_2K_H == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x1; // PullUp
+ conf0_val.r.Pull_strength = 0x0;// 2K
+ }
+ else if(P_2K_L == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x2; // PullDown
+ conf0_val.r.Pull_strength = 0x0;// 2K
+ }
+ else if(P_NONE == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0; // Non-pull
+ }
+ else
+ {
+ ASSERT(FALSE); // Invalid value
+ }
+ }
+
+
+ //
+ // Set INT Trigger Type
+ //
+ conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
+
+ //
+ // Set INT Trigger Type
+ //
+ if(TRIG_ == Gpio_Conf_Data[index].int_type)
+ {
+ //
+ // Interrupt not capable, clear bits 27:24
+ //
+ }
+ else
+ {
+ conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
+ }
+
+ DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
+
+ //
+ // Write back the targeted GPIO config value according to platform (board) GPIO setting.
+ //
+ MmioWrite32 (mmio_conf0, conf0_val.dw);
+ }
+
+ //
+ // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
+ // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
+ //
+}
+
+/**
+ Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param PlatformInfoHob PlatformInfoHob pointer with PlatformFlavor specified.
+ @param BoardId BoardId ID as determined through the EC.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_DEVICE_ERROR KSC fails to respond.
+
+**/
+EFI_STATUS
+MultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+#if !_SIMIC_
+ CFIO_INIT_STRUCT* PlatformCfioDataPtr;
+
+ PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;
+ DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));
+
+ //
+ // SCORE GPIO WELL -- IO base registers
+ //
+
+ //
+ // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);
+
+ //
+ // Set GP_LVL Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);
+
+ //
+ // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);
+
+ //
+ // GPIO Triger Positive Edge Enable Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);
+
+ //
+ // GPIO Trigger Negative Edge Enable Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);
+
+ //
+ // GPIO Trigger Status
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);
+
+ //
+ // GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);
+
+ //
+ // Set GP_LVL2 Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);
+
+ //
+ // GP_IO_SEL2 Register -> 1 = Input 0 = Output. If Native Mode don't care
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);
+
+ //
+ // GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);
+
+ //
+ // Set GP_LVL3 Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);
+
+ //
+ // GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);
+
+ //
+ // SUS GPIO WELL -- IO base registers
+ //
+
+ //
+ // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);
+
+ //
+ // Set GP_LVL Register
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);
+
+ //
+ // GP_IO_SEL Register -> 1 = Input 0 = Output. If Native Mode don't care.
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);
+
+ //
+ // GPIO Triger Positive Edge Enable Register.
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);
+
+ //
+ // GPIO Trigger Negative Edge Enable Register.
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);
+
+ //
+ // GPIO Trigger Status.
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);
+
+ //
+ // GPIO Wake Enable.
+ //
+ IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);
+
+ //
+ // Config SC/NC/SUS GPIO Pins
+ //
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_MINNOW2:
+ DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));
+ InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);
+ InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);
+ InternalGpioConfig(GPIO_SSUS_OFFSET, sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);
+ break;
+ default:
+
+ break;
+ }
+
+ //
+ // configure the CFIO Pnp settings
+ //
+ if (PlatformInfoHob->CfioEnabled) {
+ if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2){
+ InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);
+ }
+ }
+#else
+ DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or HYB model\n"));
+#endif
+ return EFI_SUCCESS;
+}
+
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h new file mode 100644 index 0000000000..e7d54d1fe1 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h @@ -0,0 +1,329 @@ +/**@file
+ Gpio setting for multiplatform.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARDGPIOS_H_
+#define _BOARDGPIOS_H_
+
+#include <PiPei.h>
+#include "PchAccess.h"
+#include "PlatformBaseAddresses.h"
+#include <../MultiPlatformLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/Smbus.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SetupVariable.h>
+
+
+GPIO_CONF_PAD_INIT mNB_BB_FAB3_GpioInitData_SC_TRI[] =
+{
+// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
+GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
+GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,TRISTS ,NA ,F0 , , ,NONE ,0x6a),
+GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,TRISTS ,NA ,F0 , , ,NONE ,0x68),
+};
+
+//
+// Minnow2
+//
+#define MINNOW2_GPIO_USE_SEL_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_USE_SEL_VAL_32_63 0x00000000
+#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
+#define MINNOW2_GPIO_USE_SEL_VAL_64_70 0x00000000
+#define MINNOW2_GPIO_USE_SEL_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_USE_SEL_VAL_SUS2 0x00000007
+
+
+#define MINNOW2_GPIO_IO_SEL_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_IO_SEL_VAL_32_63 0x00000000
+#define MINNOW2_GPIO_IO_SEL_VAL_64_70 0x00000000
+#define MINNOW2_GPIO_IO_SEL_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_IO_SEL_VAL_SUS2 0x00000007
+
+
+#define MINNOW2_GPIO_LVL_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_LVL_VAL_32_63 0x00000000
+#define MINNOW2_GPIO_LVL_VAL_64_70 0x00000000
+#define MINNOW2_GPIO_LVL_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_LVL_VAL_SUS2 0x00000007
+
+#define MINNOW2_GPIO_TPE_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_TPE_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_TPE_VAL_SUS2 0x00000007
+
+#define MINNOW2_GPIO_TNE_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_TNE_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_TNE_VAL_SUS2 0x00000007
+
+#define MINNOW2_GPIO_TS_VAL_0_31 0x00000000
+#define MINNOW2_GPIO_TS_VAL_SUS 0x00000000
+#define MINNOW2_GPIO_TS_VAL_SUS2 0x00000007
+
+static CFIO_INIT_STRUCT mMinnow2CfioInitData =
+{
+ MINNOW2_GPIO_USE_SEL_VAL_0_31,
+ MINNOW2_GPIO_USE_SEL_VAL_32_63,
+ MINNOW2_GPIO_USE_SEL_VAL_64_70,
+ MINNOW2_GPIO_USE_SEL_VAL_SUS,
+
+ MINNOW2_GPIO_IO_SEL_VAL_0_31,
+ MINNOW2_GPIO_IO_SEL_VAL_32_63,
+ MINNOW2_GPIO_IO_SEL_VAL_64_70,
+ MINNOW2_GPIO_IO_SEL_VAL_SUS,
+
+ MINNOW2_GPIO_LVL_VAL_0_31,
+ MINNOW2_GPIO_LVL_VAL_32_63,
+ MINNOW2_GPIO_LVL_VAL_64_70,
+ MINNOW2_GPIO_LVL_VAL_SUS,
+
+ MINNOW2_GPIO_TPE_VAL_0_31,
+ MINNOW2_GPIO_TPE_VAL_SUS,
+ MINNOW2_GPIO_TNE_VAL_0_31,
+ MINNOW2_GPIO_TNE_VAL_SUS,
+
+ MINNOW2_GPIO_TS_VAL_0_31,
+ MINNOW2_GPIO_TS_VAL_SUS
+};
+
+static CFIO_INIT_STRUCT mMinnow2CfioInitData2 =
+{
+ MINNOW2_GPIO_USE_SEL_VAL_0_31,
+ MINNOW2_GPIO_USE_SEL_VAL_32_63,
+ MINNOW2_GPIO_USE_SEL_VAL_64_70,
+ MINNOW2_GPIO_USE_SEL_VAL_SUS2,
+
+ MINNOW2_GPIO_IO_SEL_VAL_0_31,
+ MINNOW2_GPIO_IO_SEL_VAL_32_63,
+ MINNOW2_GPIO_IO_SEL_VAL_64_70,
+ MINNOW2_GPIO_IO_SEL_VAL_SUS2,
+
+ MINNOW2_GPIO_LVL_VAL_0_31,
+ MINNOW2_GPIO_LVL_VAL_32_63,
+ MINNOW2_GPIO_LVL_VAL_64_70,
+ MINNOW2_GPIO_LVL_VAL_SUS2,
+
+ MINNOW2_GPIO_TPE_VAL_0_31,
+ MINNOW2_GPIO_TPE_VAL_SUS2,
+ MINNOW2_GPIO_TNE_VAL_0_31,
+ MINNOW2_GPIO_TNE_VAL_SUS2,
+
+ MINNOW2_GPIO_TS_VAL_0_31,
+ MINNOW2_GPIO_TS_VAL_SUS2
+};
+
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_NC[] =
+{
+// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
+GPIO_INIT_ITEM("HV_DDI0_HPD GPIONC_0 " ,Native ,NA ,F2 , , ,NONE ,0x13),
+GPIO_INIT_ITEM("HV_DDI0_DDC_SDA GPIONC_1 " ,Native ,NA ,F2 , , ,NONE ,0x12),
+GPIO_INIT_ITEM("HV_DDI0_DDC_SCL GPIONC_2 " ,Native ,NA ,F2 , , ,NONE ,0x11),
+GPIO_INIT_ITEM("PANEL0_VDDEN GPIONC_3 " ,GPIO ,NA ,F0 , , ,NONE ,0x14),
+GPIO_INIT_ITEM("PANEL0_BKLTEN GPIONC_4 " ,GPIO ,NA ,F0 , , ,NONE ,0x15),
+GPIO_INIT_ITEM("PANEL0_BKLTCTL GPIONC_5 " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
+GPIO_INIT_ITEM("HV_DDI1_HPD GPIONC_6 " ,GPI ,NA ,F0 , , ,20K_L ,0x18),
+GPIO_INIT_ITEM("HV_DDI1_DDC_SDA GPIONC_7 " ,Native ,NA ,F2 , , ,20K_L ,0x19),
+GPIO_INIT_ITEM("HV_DDI1_DDC_SCL GPIONC_8 " ,GPI ,NA ,F0 , , ,20K_L ,0x17),
+GPIO_INIT_ITEM("PANEL1_VDDEN GPIONC_9 " ,GPIO ,NA ,F0 , , ,NONE ,0x10),
+GPIO_INIT_ITEM("PANEL1_BKLTEN GPIONC_10" ,GPIO ,NA ,F0 , , ,NONE ,0x0e),
+GPIO_INIT_ITEM("PANEL1_BKLTCTL GPIONC_11" ,GPIO ,NA ,F0 , , ,NONE ,0x0f),
+GPIO_INIT_ITEM("GP_INTD_DSI_TE1 GPIONC_12" ,GPO ,NA ,F0 , , ,NONE ,0x0c),
+GPIO_INIT_ITEM("HV_DDI2_DDC_SDA GPIONC_13" ,GPI ,NA ,F0 , , ,10K_L ,0x1a),
+GPIO_INIT_ITEM("HV_DDI2_DDC_SCL GPIONC_14" ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
+GPIO_INIT_ITEM("GP_CAMERASB00 GPIONC_15" ,GPIO ,NA ,F0 , , ,NONE ,0x01),
+GPIO_INIT_ITEM("GP_CAMERASB01 GPIONC_16" ,GPIO ,NA ,F0 , , ,NONE ,0x04),
+GPIO_INIT_ITEM("GP_CAMERASB02 GPIONC_17" ,GPIO ,NA ,F0 , , ,NONE ,0x08),
+GPIO_INIT_ITEM("GP_CAMERASB03 GPIONC_18" ,GPIO ,NA ,F0 , , ,NONE ,0x0b),
+GPIO_INIT_ITEM("GP_CAMERASB04 GPIONC_19" ,GPIO ,NA ,F0 , , ,NONE ,0x00),
+GPIO_INIT_ITEM("GP_CAMERASB05 GPIONC_20" ,GPIO ,NA ,F0 , , ,NONE ,0x03),
+GPIO_INIT_ITEM("GP_CAMERASB06 GPIONC_21" ,GPIO ,NA ,F0 , , ,NONE ,0x06),
+GPIO_INIT_ITEM("GP_CAMERASB07 GPIONC_22" ,GPIO ,NA ,F0 , , ,NONE ,0x0a),
+GPIO_INIT_ITEM("GP_CAMERASB08 GPIONC_23" ,GPIO ,NA ,F0 , , ,NONE ,0x0d),
+GPIO_INIT_ITEM("GP_CAMERASB09 GPIONC_24" ,GPIO ,NA ,F0 , , ,NONE ,0x02),
+GPIO_INIT_ITEM("GP_CAMERASB10 GPIONC_25" ,GPIO ,NA ,F0 , , ,NONE ,0x05),
+GPIO_INIT_ITEM("GP_CAMERASB11 GPIONC_26" ,GPIO ,NA ,F0 , , ,NONE ,0x09),
+};
+
+
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SC[] = {
+// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
+GPIO_INIT_ITEM("SATA_GP0 GPIOC_0 " ,Native ,NA ,F1 , , ,NONE ,0x55),
+GPIO_INIT_ITEM("SATA_GP1 GPIOC_1 " ,Native ,NA ,F1 , , ,NONE ,0x59),
+GPIO_INIT_ITEM("SATA_LEDN GPIOC_2 " ,Native ,NA ,F1 , , ,NONE ,0x5d),
+GPIO_INIT_ITEM("PCIE_CLKREQ0B GPIOC_3 " ,Native ,NA ,F1 , , ,10K_H ,0x60),
+GPIO_INIT_ITEM("PCIE_CLKREQ1B GPIOC_4 " ,Native ,NA ,F1 , , ,10K_H ,0x63),
+GPIO_INIT_ITEM("PCIE_CLKREQ2B GPIOC_5 " ,Native ,NA ,F1 , , ,10K_H ,0x66),
+GPIO_INIT_ITEM("PCIE_CLKREQ3B GPIOC_6 " ,GPIO ,NA ,F0 , , ,NONE ,0x62),
+GPIO_INIT_ITEM("SDMMC3_WP GPIOC_7 " ,Native ,NA ,F2 , , ,NONE ,0x65),
+GPIO_INIT_ITEM("HDA_RSTB GPIOC_8 " ,GPIO ,NA ,F0 , , ,NONE ,0x22),
+GPIO_INIT_ITEM("HDA_SYNC GPIOC_9 " ,GPIO ,NA ,F0 , , ,NONE ,0x25),
+GPIO_INIT_ITEM("HDA_CLK GPIOC_10 " ,GPIO ,NA ,F0 , , ,NONE ,0x24),
+GPIO_INIT_ITEM("HDA_SDO GPIOC_11 " ,GPIO ,NA ,F0 , , ,NONE ,0x26),
+GPIO_INIT_ITEM("HDA_SDI0 GPIOC_12 " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
+GPIO_INIT_ITEM("HDA_SDI1 GPIOC_13 " ,GPIO ,NA ,F0 , , ,NONE ,0x23),
+GPIO_INIT_ITEM("HDA_DOCKRSTB GPIOC_14 " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
+GPIO_INIT_ITEM("HDA_DOCKENB GPIOC_15 " ,GPIO ,NA ,F0 , , ,NONE ,0x54),
+GPIO_INIT_ITEM("SDMMC1_CLK GPIOC_16 " ,GPIO ,NA ,F0 , , ,NONE ,0x3e),
+GPIO_INIT_ITEM("SDMMC1_D0 GPIOC_17 " ,GPIO ,NA ,F0 , , ,NONE ,0x3d),
+GPIO_INIT_ITEM("SDMMC1_D1 GPIOC_18 " ,GPIO ,NA ,F0 , , ,NONE ,0x40),
+GPIO_INIT_ITEM("SDMMC1_D2 GPIOC_19 " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
+GPIO_INIT_ITEM("SDMMC1_D3_CD_B GPIOC_20 " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
+GPIO_INIT_ITEM("MMC1_D4_SD_WE GPIOC_21 " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
+GPIO_INIT_ITEM("MMC1_D5 GPIOC_22 " ,GPIO ,NA ,F0 , , ,NONE ,0x3c),
+GPIO_INIT_ITEM("MMC1_D6 GPIOC_23 " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
+GPIO_INIT_ITEM("MMC1_D7 GPIOC_24 " ,GPIO ,NA ,F0 , , ,NONE ,0x3f),
+GPIO_INIT_ITEM("SDMMC1_CMD GPIOC_25 " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
+GPIO_INIT_ITEM("MMC1_RESET_B GPIOC_26 " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
+GPIO_INIT_ITEM("SDMMC2_CLK GPIOC_27 " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
+GPIO_INIT_ITEM("SDMMC2_D0 GPIOC_28 " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
+GPIO_INIT_ITEM("SDMMC2_D1 GPIOC_29 " ,GPIO ,NA ,F0 , , ,NONE ,0x2f),
+GPIO_INIT_ITEM("SDMMC2_D2 GPIOC_30 " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
+GPIO_INIT_ITEM("SDMMC2_D3_CD_B GPIOC_31 " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
+GPIO_INIT_ITEM("SDMMC2_CMD GPIOC_32 " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
+//
+//Just for test, We make the setting that all is same with Bayleybay.
+//
+GPIO_INIT_ITEM("SDMMC3_CLK GPIOC_33 " ,Native ,NA ,F1 , , ,NONE ,0x2b),
+GPIO_INIT_ITEM("SDMMC3_D0 GPIOC_34 " ,Native ,NA ,F1 , , ,NONE ,0x2e),
+GPIO_INIT_ITEM("SDMMC3_D1 GPIOC_35 " ,Native ,NA ,F1 ,YES , ,NONE ,0x29),
+GPIO_INIT_ITEM("SDMMC3_D2 GPIOC_36 " ,Native ,NA ,F1 , , ,NONE ,0x2d),
+GPIO_INIT_ITEM("SDMMC3_D3 GPIOC_37 " ,Native ,NA ,F1 , , ,NONE ,0x2a),
+GPIO_INIT_ITEM("SDMMC3_CD_B GPIOC_38 " ,Native ,NA ,F1 ,YES ,Edge_Both ,NONE ,0x3a),
+GPIO_INIT_ITEM("SDMMC3_CMD GPIOC_39 " ,Native ,NA ,F1 , , ,NONE ,0x2c),
+GPIO_INIT_ITEM("SDMMC3_1P8_EN GPIOC_40 " ,Native ,NA ,F1 , , ,NONE ,0x5f),
+GPIO_INIT_ITEM("SDMMC3_PWR_EN_B GPIOC_41 " ,Native ,NA ,F1 , , ,NONE ,0x69),
+GPIO_INIT_ITEM("LPC_AD0 GPIOC_42 " ,GPIO ,NA ,F0 , , ,NONE ,0x46),
+GPIO_INIT_ITEM("LPC_AD1 GPIOC_43 " ,GPIO ,NA ,F0 , , ,NONE ,0x44),
+GPIO_INIT_ITEM("LPC_AD2 GPIOC_44 " ,GPIO ,NA ,F0 , , ,NONE ,0x43),
+GPIO_INIT_ITEM("LPC_AD3 GPIOC_45 " ,GPIO ,NA ,F0 , , ,NONE ,0x42),
+GPIO_INIT_ITEM("LPC_FRAMEB GPIOC_46 " ,GPIO ,NA ,F0 , , ,NONE ,0x45),
+GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,GPIO ,NA ,F0 , , ,NONE ,0x47),
+GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,GPIO ,NA ,F0 , , ,NONE ,0x41),
+GPIO_INIT_ITEM("LPC_CLKRUNB GPIOC_49 " ,GPIO ,NA ,F0 , , ,NONE ,0x48),
+GPIO_INIT_ITEM("ILB_SERIRQ GPIOC_50 " ,GPIO ,NA ,F0 , , ,NONE ,0x56),
+GPIO_INIT_ITEM("SMB_DATA GPIOC_51 " ,Native ,NA ,F1 , , ,NONE ,0x5a),
+GPIO_INIT_ITEM("SMB_CLK GPIOC_52 " ,Native ,NA ,F1 , , ,NONE ,0x58),
+GPIO_INIT_ITEM("SMB_ALERTB GPIOC_53 " ,Native ,NA ,F1 , , ,10K_H ,0x5c),
+GPIO_INIT_ITEM("SPKR GPIOC_54 " ,GPI ,NA ,F0 , , ,20K_H ,0x67),
+GPIO_INIT_ITEM("MHSI_ACDATA GPIOC_55 " ,GPIO ,NA ,F0 , , ,NONE ,0x4d),
+GPIO_INIT_ITEM("MHSI_ACFLAG GPIOC_56 " ,GPI ,NA ,F0 , , ,20K_H ,0x4f),
+GPIO_INIT_ITEM("MHSI_ACWAKE GPIOC_58 " ,GPIO ,NA ,F0 , , ,NONE ,0x4e),
+GPIO_INIT_ITEM("MHSI_CADATA GPIOC_59 " ,GPIO ,NA ,F0 , , ,NONE ,0x51),
+GPIO_INIT_ITEM("MHSI_CAFLAG GPIOC_60 " ,GPO ,HI ,F0 , , ,20K_H ,0x50),
+GPIO_INIT_ITEM("GP_SSP_2_CLK GPIOC_62 " ,GPI ,NA ,F0 , , ,20K_H ,0x0d),
+GPIO_INIT_ITEM("GP_SSP_2_FS GPIOC_63 " ,GPI ,NA ,F0 , , ,20K_H ,0x0c),
+GPIO_INIT_ITEM("GP_SSP_2_RXD GPIOC_64 " ,GPI ,NA ,F0 , , ,20K_H ,0x0f),
+GPIO_INIT_ITEM("GP_SSP_2_TXD GPIOC_65 " ,GPI ,NA ,F0 , , ,20K_H ,0x0e),
+GPIO_INIT_ITEM("SPI1_CS0_B GPIOC_66 " ,Native ,NA ,F1 , , ,20K_H ,0x11),
+GPIO_INIT_ITEM("SPI1_MISO GPIOC_67 " ,Native ,NA ,F1 , , ,20K_H ,0x12),
+GPIO_INIT_ITEM("SPI1_MOSI GPIOC_68 " ,Native ,NA ,F1 , , ,20K_H ,0x13),
+GPIO_INIT_ITEM("SPI1_CLK GPIOC_69 " ,Native ,NA ,F1 , , ,20K_H ,0x10),
+GPIO_INIT_ITEM("UART1_RXD GPIOC_70 " ,Native ,NA ,F1 , , ,20K_H ,0x02),
+GPIO_INIT_ITEM("UART1_TXD GPIOC_71 " ,Native ,NA ,F1 , , ,20K_H ,0x01),
+GPIO_INIT_ITEM("UART1_RTS_B GPIOC_72 " ,GPI ,NA ,F0 , , ,20K_H ,0x00),
+GPIO_INIT_ITEM("UART1_CTS_B GPIOC_73 " ,GPI ,NA ,F0 , , ,20K_H ,0x04),
+GPIO_INIT_ITEM("UART2_RXD GPIOC_74 " ,Native ,NA ,F1 , , ,20K_H ,0x06),
+GPIO_INIT_ITEM("UART2_TXD GPIOC_75 " ,Native ,NA ,F1 , , ,20K_H ,0x07),
+GPIO_INIT_ITEM("UART2_RTS_B GPIOC_76 " ,GPIO ,NA ,F0 , , ,NONE ,0x09),
+GPIO_INIT_ITEM("UART2_CTS_B GPIOC_77 " ,Native ,NA ,F1 , , ,20K_H ,0x08),
+GPIO_INIT_ITEM("I2C0_SDA GPIOC_78 " ,GPIO ,NA ,F0 , , ,NONE ,0x21),
+GPIO_INIT_ITEM("I2C0_SCL GPIOC_79 " ,GPIO ,NA ,F0 , , ,NONE ,0x20),
+GPIO_INIT_ITEM("I2C1_SDA GPIOC_80 " ,Native ,NA ,F1 , , ,NONE ,0x1f),
+GPIO_INIT_ITEM("I2C1_SCL GPIOC_81 " ,Native ,NA ,F1 , , ,NONE ,0x1e),
+GPIO_INIT_ITEM("I2C2_SDA GPIOC_82 " ,GPIO ,NA ,F0 , , ,NONE ,0x1d),
+GPIO_INIT_ITEM("I2C2_SCL GPIOC_83 " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
+GPIO_INIT_ITEM("I2C3_SDA GPIOC_84 " ,GPIO ,NA ,F0 , , ,NONE ,0x19),
+GPIO_INIT_ITEM("I2C3_SCL GPIOC_85 " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
+GPIO_INIT_ITEM("I2C4_SDA GPIOC_86 " ,Native ,NA ,F1 , , ,20K_H ,0x1a),
+GPIO_INIT_ITEM("I2C4_SCL GPIOC_87 " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
+GPIO_INIT_ITEM("I2C5_SDA GPIOC_88 " ,Native ,NA ,F1 , , ,20K_H ,0x15),
+GPIO_INIT_ITEM("I2C5_SCL GPIOC_89 " ,Native ,NA ,F1 , , ,20K_H ,0x14),
+GPIO_INIT_ITEM("I2C6_SDA GPIOC_90 " ,Native ,NA ,F1 , , ,20K_H ,0x18),
+GPIO_INIT_ITEM("I2C6_SCL GPIOC_91 " ,Native ,NA ,F1 , , ,20K_H ,0x16),
+GPIO_INIT_ITEM("I2C_NFC_SDA GPIOC_92 " ,GPIO ,NA ,F1 , , ,NONE ,0x05),
+GPIO_INIT_ITEM("I2C_NFC_SCL GPIOC_93 " ,GPO ,LO ,F1 , , ,NONE ,0x03),
+GPIO_INIT_ITEM("PWM0 GPIOC_94 " ,Native ,NA ,F1 , , ,20K_L ,0x0a),
+GPIO_INIT_ITEM("PWM1 GPIOC_95 " ,Native ,NA ,F1 , , ,20K_L ,0x0b),
+GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,GPIO ,NA ,F0 , , ,NONE ,0x6a),
+GPIO_INIT_ITEM("PLT_CLK1 GPIOC_97 " ,GPIO ,NA ,F0 , , ,NONE ,0x57),
+GPIO_INIT_ITEM("PLT_CLK2 GPIOC_98 " ,GPIO ,NA ,F0 , , ,NONE ,0x5b),
+GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,GPIO ,NA ,F0 , , ,NONE ,0x68),
+GPIO_INIT_ITEM("PLT_CLK4 GPIOC_100" ,GPIO ,NA ,F0 , , ,NONE ,0x61),
+GPIO_INIT_ITEM("PLT_CLK5 GPIOC_101" ,GPIO ,NA ,F0 , , ,NONE ,0x64),
+};
+
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SUS[] = {
+// Pad Name GPIO Number Used As GPIO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
+GPIO_INIT_ITEM("GPIO_SUS0 GPIO_SUS0" ,GPI ,NA ,F0 , , ,20K_H ,0x1d),
+GPIO_INIT_ITEM("GPIO_SUS1 GPIO_SUS1" ,GPI ,NA ,F0 , , ,20K_H ,0x21),
+GPIO_INIT_ITEM("GPIO_SUS2 GPIO_SUS2" ,GPI ,NA ,F0 , , ,20K_H ,0x1e),
+GPIO_INIT_ITEM("GPIO_SUS3 GPIO_SUS3" ,Native ,NA ,F6 ,YES ,Level_Low ,2K_H ,0x1f),
+GPIO_INIT_ITEM("GPIO_SUS4 GPIO_SUS4" ,GPIO ,NA ,F0 , , ,NONE ,0x20),
+GPIO_INIT_ITEM("GPIO_SUS5 GPIO_SUS5" ,GPI ,NA ,F0 , , ,NONE ,0x22),
+GPIO_INIT_ITEM("GPIO_SUS6 GPIO_SUS6" ,GPI ,NA ,F0 , , ,NONE ,0x24),
+GPIO_INIT_ITEM("GPIO_SUS7 GPIO_SUS7" ,GPI ,NA ,F0 , , ,NONE ,0x23),
+GPIO_INIT_ITEM("SEC_GPIO_SUS8 GPIO_SUS8" ,GPO ,HI ,F0 , , ,20K_H ,0x26),
+GPIO_INIT_ITEM("SEC_GPIO_SUS9 GPIO_SUS9" ,GPO ,HI ,F0 , , ,20K_H ,0x25),
+GPIO_INIT_ITEM("SEC_GPIO_SUS10 GPIO_SUS10" ,GPO ,HI ,F0 , , ,NONE ,0x12),
+GPIO_INIT_ITEM("SUSPWRDNACK GPIOS_11 " ,Native ,NA ,F0 , , ,10K_H ,0x07),
+GPIO_INIT_ITEM("PMU_SUSCLK GPIOS_12 " ,Native ,NA ,F0 , , ,NONE ,0x0b),
+GPIO_INIT_ITEM("PMU_SLP_S0IX_B GPIOS_13 " ,Native ,NA ,F0 , , ,NONE ,0x14),
+GPIO_INIT_ITEM("PMU_SLP_LAN_B GPIOS_14 " ,GPO ,LO ,F1 , , ,10K_H ,0x11),
+GPIO_INIT_ITEM("PMU_WAKE_B GPIOS_15 " ,Native ,NA ,F0 , , ,20K_H ,0x01),
+GPIO_INIT_ITEM("PMU_PWRBTN_B GPIOS_16 " ,Native ,NA ,F0 , , ,20K_H ,0x08),
+GPIO_INIT_ITEM("PMU_WAKE_LAN_B GPIOS_17 " ,GPIO ,NA ,F1 , , ,NONE ,0x0a),
+GPIO_INIT_ITEM("SUS_STAT_B GPIOS_18 " ,GPO ,NA ,F1 , , ,NONE ,0x13),
+GPIO_INIT_ITEM("USB_OC0_B GPIOS_19 " ,Native ,NA ,F0 , , ,10K_H ,0x0c),
+GPIO_INIT_ITEM("USB_OC1_B GPIOS_20 " ,Native ,NA ,F0 , , ,10K_H ,0x00),
+GPIO_INIT_ITEM("SPI_CS1_B GPIOS_21 " ,Native ,NA ,F0 , , ,NONE ,0x02),
+GPIO_INIT_ITEM("GPIO_DFX0 GPIOS_22 " ,GPIO ,NA ,F0 , , ,NONE ,0x17),
+GPIO_INIT_ITEM("GPIO_DFX1 GPIOS_23 " ,GPIO ,NA ,F0 , , ,NONE ,0x27),
+GPIO_INIT_ITEM("GPIO_DFX2 GPIOS_24 " ,GPIO ,NA ,F0 , , ,NONE ,0x1c),
+GPIO_INIT_ITEM("GPIO_DFX3 GPIOS_25 " ,GPIO ,NA ,F0 , , ,NONE ,0x1b),
+GPIO_INIT_ITEM("GPIO_DFX4 GPIOS_26 " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
+GPIO_INIT_ITEM("GPIO_DFX5 GPIOS_27 " ,GPI ,NA ,F0 , , ,20K_H ,0x15),
+GPIO_INIT_ITEM("GPIO_DFX6 GPIOS_28 " ,GPI ,NA ,F0 , , ,20K_H ,0x18),
+GPIO_INIT_ITEM("GPIO_DFX7 GPIOS_29 " ,GPI ,NA ,F0 , , ,20K_H ,0x19),
+GPIO_INIT_ITEM("GPIO_DFX8 GPIOS_30 " ,GPI ,NA ,F0 , , ,20K_H ,0x1a),
+GPIO_INIT_ITEM("USB_ULPI_0_CLK GPIOS_31 " ,GPIO ,NA ,F0 , , ,NONE ,0x33),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA0 GPIOS_32 " ,GPIO ,NA ,F0 , , ,NONE ,0x38),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA1 GPIOS_33 " ,GPIO ,NA ,F0 , , ,NONE ,0x36),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA2 GPIOS_34 " ,GPIO ,NA ,F0 , , ,NONE ,0x31),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA3 GPIOS_35 " ,GPIO ,NA ,F0 , , ,NONE ,0x37),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA4 GPIOS_36 " ,GPIO ,NA ,F0 , , ,NONE ,0x30),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA5 GPIOS_37 " ,GPIO ,NA ,F0 , , ,NONE ,0x39),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA6 GPIOS_38 " ,GPIO ,NA ,F0 , , ,NONE ,0x32),
+GPIO_INIT_ITEM("USB_ULPI_0_DATA7 GPIOS_39 " ,GPIO ,NA ,F0 , , ,NONE ,0x3a),
+GPIO_INIT_ITEM("USB_ULPI_0_DIR GPIOS_40 " ,GPIO ,NA ,F0 , , ,NONE ,0x34),
+GPIO_INIT_ITEM("USB_ULPI_0_NXT GPIOS_41 " ,GPIO ,NA ,F0 , , ,NONE ,0x35),
+GPIO_INIT_ITEM("USB_ULPI_0_STP GPIOS_42 " ,GPIO ,NA ,F0 , , ,NONE ,0x3b),
+GPIO_INIT_ITEM("USB_ULPI_0_REFCLK GPIOS_43 " ,GPIO ,NA ,F0 , , ,NONE ,0x28),
+};
+
+EFI_STATUS
+MultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+MultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c new file mode 100644 index 0000000000..6862c63c5d --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c @@ -0,0 +1,35 @@ +/** @file
+ Jumper setting for multiplatform.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <BoardJumpers.h>
+
+BOOLEAN
+IsRecoveryJumper (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+)
+{
+ return FALSE;
+}
+
+BOOLEAN
+IsManufacturingMode(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+)
+{
+ return FALSE;
+}
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h new file mode 100644 index 0000000000..e93d55cd3d --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h @@ -0,0 +1,35 @@ +/**@file
+ Jumper setting for multiplatform.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _BOARDJUMPERS_H_
+#define _BOARDJUMPERS_H_
+
+#include <PiPei.h>
+#include "PchAccess.h"
+#include "PlatformBaseAddresses.h"
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Guid/PlatformInfo.h>
+
+BOOLEAN
+IsRecoveryJumper (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+);
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c new file mode 100644 index 0000000000..7381e00875 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c @@ -0,0 +1,47 @@ +/** @file
+ ACPI oem ids setting for multiplatform.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <BoardOemIds.h>
+
+//
+// Global module data
+//
+EFI_STATUS
+InitializeBoardOemId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT64 OemId;
+ UINT64 OemTableId;
+
+ //
+ // Set OEM ID according to Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+
+ case BOARD_ID_MINNOW2:
+ default:
+ OemId = EFI_ACPI_OEM_ID_DEFAULT;
+ OemTableId = EFI_ACPI_OEM_TABLE_ID_DEFAULT;
+ break;
+ }
+
+ PlatformInfoHob->AcpiOemId = OemId;
+ PlatformInfoHob->AcpiOemTableId = OemTableId;
+ return EFI_SUCCESS;
+}
+
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h new file mode 100644 index 0000000000..d8da53f111 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h @@ -0,0 +1,34 @@ +/**@file
+ ACPI oem ids setting for multiplatform.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Guid/PlatformInfo.h>
+#include <Library/BaseMemoryLib.h>
+
+#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', ' ', ' ') // max 6 chars
+#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ') // max 6 chars
+#define EFI_ACPI_OEM_ID2 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '2', ' ', ' ') // max 6 chars
+
+#define EFI_ACPI_OEM_TABLE_ID_DEFAULT SIGNATURE_64('E', 'D', 'K', '2', ' ', ' ', ' ', ' ')
+#define EFI_ACPI_OEM_TABLE_ID1 SIGNATURE_64('E', 'D', 'K', '2', '_', '1', ' ', ' ')
+#define EFI_ACPI_OEM_TABLE_ID2 SIGNATURE_64('E', 'D', 'K', '2', '_', '2', ' ', ' ')
+
+
+EFI_STATUS
+InitializeBoardOemId (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c new file mode 100644 index 0000000000..4a05d313f8 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c @@ -0,0 +1,42 @@ +/** @file
+ Subsystem IDs setting for multiplatform.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <BoardSsidSvid.h>
+
+//
+// Global module data
+//
+EFI_STATUS
+InitializeBoardSsidSvid (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT32 SsidSvidValue = 0;
+
+ //
+ // Set OEM ID according to Board ID.
+ //
+ switch (PlatformInfoHob->BoardId) {
+ case BOARD_ID_MINNOW2:
+ default:
+ SsidSvidValue = SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT;
+ break;
+ }
+ PlatformInfoHob->SsidSvid = SsidSvidValue;
+ return EFI_SUCCESS;
+}
+
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h new file mode 100644 index 0000000000..b22c03c804 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h @@ -0,0 +1,40 @@ +/**@file
+ Subsystem IDs setting for multiplatform.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Guid/PlatformInfo.h>
+#include <Library/BaseMemoryLib.h>
+
+//
+// Default Vendor ID and Subsystem ID
+//
+#define SUBSYSTEM_VENDOR_ID1 0x8086
+#define SUBSYSTEM_DEVICE_ID1 0x1999
+#define SUBSYSTEM_SVID_SSID1 (SUBSYSTEM_VENDOR_ID1 + (SUBSYSTEM_DEVICE_ID1 << 16))
+
+#define SUBSYSTEM_VENDOR_ID2 0x8086
+#define SUBSYSTEM_DEVICE_ID2 0x1888
+#define SUBSYSTEM_SVID_SSID2 (SUBSYSTEM_VENDOR_ID2 + (SUBSYSTEM_DEVICE_ID2 << 16))
+
+#define SUBSYSTEM_VENDOR_ID 0x8086
+#define SUBSYSTEM_DEVICE_ID 0x1234
+#define SUBSYSTEM_SVID_SSID (SUBSYSTEM_VENDOR_ID + (SUBSYSTEM_DEVICE_ID << 16))
+
+EFI_STATUS
+InitializeBoardSsidSvid (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c new file mode 100644 index 0000000000..d32deb5b6c --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c @@ -0,0 +1,122 @@ +/** @file
+ Multiplatform initialization.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <MultiPlatformLib.h>
+
+/**
+ Platform Type detection. Because the PEI globle variable
+ is in the flash, it could not change directly.So use
+ 2 PPIs to distinguish the platform type.
+
+ @param FfsHeader Pointer to Firmware File System file header.
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS Memory initialization completed successfully.
+ @retval Others All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+MultiPlatformInfoInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ )
+{
+ UINT32 PcieLength;
+ EFI_STATUS Status;
+
+
+ PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
+
+ PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);
+
+ //
+ // Update ICH Type
+ //
+ //
+ // Device ID
+ //
+ PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
+
+ PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
+
+ //
+ //64MB
+ //
+ PcieLength = 0x04000000;
+
+ //
+ // Don't support BASE above 4GB currently.
+ //
+ PlatformInfoHob->PciData.PciExpressSize = PcieLength;
+ PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
+
+ PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
+ PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
+
+ PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
+ PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
+ PlatformInfoHob->CpuData.CpuAddressWidth = 36;
+
+ PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
+ PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
+
+ PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
+
+ //
+ // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
+ //
+ if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
+ } else {
+ PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
+ }
+ PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
+
+ //
+ // Platform PCI MMIO Size in unit of 1MB.
+ //
+ PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
+
+ //
+ // Enable ICH IOAPIC
+ //
+ PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
+
+ DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));
+
+ //
+ // Get Platform Info and fill the Hob.
+ //
+ PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
+
+ //
+ // Get GPIO table
+ //
+ Status = MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
+
+ //
+ // Program GPIO
+ //
+ Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
+
+ //
+ // Update OemId
+ //
+ Status = InitializeBoardOemId (PeiServices, PlatformInfoHob);
+ Status = InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
+
+ return EFI_SUCCESS;
+}
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h new file mode 100644 index 0000000000..a1fe9d4356 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h @@ -0,0 +1,94 @@ +/**@file
+ Multiplatform initialization header file.
+
+ This file includes package header files, library classes.
+
+ Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MULTIPLATFORM_LIB_H_
+#define _MULTIPLATFORM_LIB_H_
+
+
+#define LEN_64M 0x4000000
+
+//
+// Default PCI32 resource size
+//
+#define RES_MEM32_MIN_LEN 0x38000000
+
+#define RES_IO_BASE 0x0D00
+#define RES_IO_LIMIT 0xFFFF
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <FrameworkPei.h>
+
+#include "PlatformBaseAddresses.h"
+#include "PchAccess.h"
+#include "SetupMode.h"
+#include "PlatformBootMode.h"
+#include "Platform.h"
+
+#include <Ppi/Stall.h>
+#include <Guid/SetupVariable.h>
+#include <Ppi/AtaController.h>
+#include <Ppi/FindFv.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/Capsule.h>
+#include <Guid/EfiVpdData.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Ppi/Speaker.h>
+#include <Guid/FirmwareFileSystem.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/Cache.h>
+#include <Ppi/Reset.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Guid/GlobalVariable.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/DeviceRecoveryModule.h>
+#include <Guid/Capsule.h>
+#include <Guid/RecoveryDevice.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/PlatformInfo.h>
+
+#include <BoardOemIds/BoardOemIds.h>
+#include <BoardSsidSvid/BoardSsidSvid.h>
+
+
+EFI_STATUS
+GetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ );
+
+EFI_STATUS
+MultiPlatformGpioTableInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+MultiPlatformGpioProgram (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf new file mode 100644 index 0000000000..74ffc78c91 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf @@ -0,0 +1,83 @@ +#
+#
+# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#
+#
+# Module Name:
+#
+# MultiPlatform.inf
+#
+# Abstract:
+#
+#
+--*/
+
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MultiPlatformLib
+ FILE_GUID = AB83A52B-B44A-462c-B099-444CC0ED274D
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MultiPlatformLib
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+[sources]
+ MultiPlatformLib.c
+ MultiPlatformLib.h
+ PlatformInfoHob.c
+#GPIO
+ BoardGpios/BoardGpios.c
+ BoardGpios/BoardGpios.h
+
+#ClkGen
+ BoardClkGens/BoardClkGens.c
+ BoardClkGens/BoardClkGens.h
+
+#Jumper
+ BoardJumpers/BoardJumpers.c
+ BoardJumpers/BoardJumpers.h
+
+#OemId
+ BoardOemIds/BoardOemIds.c
+ BoardOemIds/BoardOemIds.h
+
+#SSIDSVID
+ BoardSsidSvid/BoardSsidSvid.c
+ BoardSsidSvid/BoardSsidSvid.h
+[Guids]
+
+ gEfiPlatformInfoGuid # ALWAYS_CONSUMED
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Vlv2TbltDevicePkg/PlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
+ IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+# PeiKscLib
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+[Pcd.common]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Guids]
+ gEfiSetupVariableGuid
diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c new file mode 100644 index 0000000000..ebaaf40a16 --- /dev/null +++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c @@ -0,0 +1,59 @@ +/** @file
+ Platform Hob access interface for multiplatform.
+
+ Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#include <MultiPlatformLib.h>
+
+/**
+ Returns the Platform Info of the platform from the HOB.
+
+ @param PeiServices General purpose services available to every PEIM.
+ @param PlatformInfoHob Pointer to the PLATFORM_INFO_HOB Pointer
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND PlatformInfoHob data doesn't exist, use default instead.
+
+**/
+EFI_STATUS
+GetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ )
+{
+ EFI_PEI_HOB_POINTERS GuidHob;
+
+ //
+ // Find the PlatformInfo HOB
+ //
+ GuidHob.Raw = GetHobList ();
+ if (GuidHob.Raw == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {
+ *PlatformInfoHob = GET_GUID_HOB_DATA (GuidHob.Guid);
+ }
+
+ //
+ // PlatformInfo PEIM should provide this HOB data, if not ASSERT and return error.
+ //
+ ASSERT_EFI_ERROR (*PlatformInfoHob != NULL);
+ if (!(*PlatformInfoHob)) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
|