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* IntelSiliconPkg IntelVTdDxe: use gEfiAcpi10TableGuid for ACPI 1.0Star Zeng2018-05-102-2/+2
| | | | | | | | | | | | | According to definition (Acpi.h and MdePkg.dec), gEfiAcpiTableGuid = gEfiAcpi20TableGuid, and the code is trying to parse ACPI 2.0 first and then ACPI 1.0, but it uses gEfiAcpiTableGuid wrongly for ACPI 1.0, this patch is to fix it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 118f1657b9c6c338c25ef81e6c30ece392138673)
* IntelSiliconPkg/VtdInfoSample: Fix IGD RMRR memory.Jiewen Yao2018-05-101-1/+1
| | | | | | | | | | Fix a calculation problem in IGD RMRR memory. Cc: Zeng Star <zeng.star@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Zeng Star <zeng.star@intel.com> (cherry picked from commit c13cb4aebf4a27dd056f3a4b36d18646ffccef3b)
* IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3Jiewen Yao2018-05-102-2/+59
| | | | | | | | | | | In S3 resume, before system transfer to waking vector, the VTdPmr need turn off VTd protection based upon VTdPolicy. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit fc8be1ad9ab310b1c7752985c982b66a5a377f1a)
* IntelSiliconPkg/dec: Clarify VTdPolicy.Jiewen Yao2018-05-101-2/+2
| | | | | | | | | | Clarify the VTdPolicy is for both PEI and DXE. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8be3ff8fb82026b6294b1e203563737bfae76a57)
* IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.Jiewen Yao2018-05-102-4/+9
| | | | | | | | | | Make sure the context table are flush to memory. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 73a2fe8b871a84c30f77182c3b56c77893488484)
* IntelSiliconPkg/VTdInfoSample: Add RMRR table.Jiewen Yao2018-05-102-10/+149
| | | | | | | | | | | Let system report RMRR table for the platform support PEI graphic. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 70dc3ec5a72e0e3fc3ea8f63baecdeafd1110db8)
* IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.Jiewen Yao2018-05-103-29/+624
| | | | | | | | | | | | | | | | | | | | In order to support PEI graphic, we let VTdPmrPei driver parse DMAR table RMRR entry and allow the UMA access. If a system has no PEI IGD, no RMRR is needed. The behavior is unchanged. If a system has PEI IGD, it must report RMRR in PEI phase. The PeiVTdPrm will program the IGD VTd engine to skip the RMRR region, and program the rest PCI VTd engine to skip the another DMA buffer allocated in PEI phase for other device driver. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8e9da4ba3c4a4eeded7651f629330df3a9e5a780)
* IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.Jiewen Yao2018-05-101-11/+14
| | | | | | | | | | | | | | We notice that there is real usage in PEI to show the graphic out. As such we need report RMRR table in PEI to let VTdPmrPei driver skip the IGD UMA region. Now the VTD_INFO PPI uses the same DMAR data structure. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit f02c531967785780ad14fbc8475d8322dfd0909b)
* IntelSiliconPkg/VTdPei: Fix Linux build error.Jiewen Yao2018-05-103-3/+3
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 4084ccfa22dab15e2b9c3f531ba9ec18a6e08a8d)
* IntelSiliconPkg/PlatformIntelVTdInfoSamplePei: Move to feature dir.Jiewen Yao2018-05-105-1/+1
| | | | | | | | | | | Move PlatformIntelVTdInfoSamplePei to Feature/VTd/. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit bec7a86c70398e774eb90511d7d5a370e23ad0dd)
* IntelSiliconPkg/IntelVTdPmrPei: Move to feature dir.Jiewen Yao2018-05-107-1/+1
| | | | | | | | | | | Move IntelVTdPmrPei to Feature/VTd/IntelVTdPmrPei. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit db5c75863d17e9fc1e5b7081a7ec62dee8c6f177)
* IntelSiliconPkg/PlatformVTdSampleDxe: Move to feature dir.Jiewen Yao2018-05-105-1/+1
| | | | | | | | | | | Move PlatformVTdSampleDxe to Feature/VTd/PlatformVTdSampleDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit e4c9ac648d3db26103b778d69b62290863986e82)
* IntelSiliconPkg/IntelVTdDxe: Move to feature dir.Jiewen Yao2018-05-1013-1/+1
| | | | | | | | | | | Move IntelVTdDxe to Feature/VTd/IntelVTdDxe. Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 9010459c9aaa985619e341ecc2789a06993b2310)
* IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei.Jiewen Yao2018-05-101-0/+1
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8a4ed1188b7d3e6d39c9759a6f91fbbc5660160e)
* IntelSiliconPkg: Add PlatformVTdInfoSamplePei.Jiewen Yao2018-05-104-0/+156
| | | | | | | | | | This is a sample driver to produce VTD_INFO PPI. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 53269009cbe4bb59520630aef971b89f82a3c72d)
* IntelSiliconPkg/dsc: Add IntelVTdPmrPeim.Jiewen Yao2018-05-101-0/+9
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 71cfa709ed591ceca36017e93304cce1de51c810)
* IntelSiliconPkg: Add IntelVTdPmrPei.Jiewen Yao2018-05-106-0/+1096
| | | | | | | | | | | | | | | | This PEIM is to produce IOMMU_PPI, so that PEI device driver can have better DAM management. This PEIM will setup VTD PMR register to protect most DRAM. It allocates a big chunk DMA buffer in the entrypoint, and only use this buffer for DMA. Any other region is DMA protected. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 3f5ed3fa13c66d66e1a7c5df9a78311f9a0ed991)
* IntelSiliconPkg/dec: Add VTD_INFO PPI GUIDJiewen Yao2018-05-101-0/+3
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 0b7df50021b9d21c2acef3bc06c683febbbeb60d)
* IntelSiliconPkg/include: Add VTD_INFO PPI.Jiewen Yao2018-05-101-0/+40
| | | | | | | | | | | | | | This VTD_INFO_PPI is to provide VTD information in PEI. As such, we can have a generic VTd driver. It is a lightweight version DMAR table, but it does not contain PCI device information. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 77562d13ac7fa2c3840ccae598b26e665251ede7)
* IntelSiliconPkg/VTdDxe: Disable PMRJiewen Yao2018-05-101-1/+50
| | | | | | | | | | | When VTd translation is enabled, PMR can be disable. Or the DMA will be blocked by PMR. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit ffe77707a320077373d35029ba5b43253da6fd05)
* IntelSiliconPkg/Vtd.h: Add definition for PMR.Jiewen Yao2018-05-101-0/+6
| | | | | | | | | | Add missing PMR definition in VTd spec. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 40cc2270556ec5e49d184c946bb58981f7155cf3)
* IntelSiliconPkg/IntelVtd: Consume VTd policy PCDJiewen Yao2018-05-103-2/+12
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit c50596a701435b62dc7e9c12b49201a17c38e17c)
* IntelSiliconPkg/dec: Add VTd policy PCDJiewen Yao2018-05-101-0/+6
| | | | | | | | | | | | | | | BIT0: This is to control if a platform wants to enable VTd based protection during boot. BIT1: This is to control if a platform wants to keep VTd enabled at ExitBootService. The default configuration is BIT0:1, BIT1:0. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 0d12b733060930df03fca00ae1228b565481a3aa)
* IntelSiliconPkg/VTd: improve debug message.Jiewen Yao2018-05-101-2/+2
| | | | | | | | | | | Add /n for debug message to make error more readable. Suggested-by: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 4d150848c51f39363fec01779514baa8394d68c5)
* IntelSiliconPkg/Vtd: Support CSM usage.Jiewen Yao2018-05-102-5/+5
| | | | | | | | | | | | | | Remove zero address check in IoMmuMap. The reason is that a CSM legacy driver may use legacy memory for DMA. As such, the legacyBios need allow below 1M to the legacy device. This patch also fixed some typo. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 94fb621d370e7397e988038f28eede05b40ee6e5)
* IntelSiliconPkg/PlatformVTdSample: Avoid using constant result 'if'Hao Wu2018-05-101-14/+24
| | | | | | | | | | | | | In this sample driver, if (0) {...} else {...} statements were used to illustrate two different using scenarios. This comment refines the coding style by substituting the 'if (0)' statement with comments to select sample codes for different cases. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 7046a2739ae74f5d5c86ea18dc4bcc855e4916c6)
* IntelSiliconPkg/PlatformVTdSample: update ExceptionDeviceJiewen Yao2018-05-101-10/+70
| | | | | | | | | | | Add sample for device scope based exception list and PCI vendor id based exception list. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 5f5bdf4ab58e3b225d2cebe5735a6825f535c7cd)
* IntelSiliconPkg/IntelVTd: update PlatformVtdPolicyJiewen Yao2018-05-107-161/+423
| | | | | | | | | | | | | | | | | 1. Handle flexible exception list format. 1.1 Handle DeviceScope based device info. 1.2 Handle PciDeviceId based device info. 2. Reorg the PCI_DEVICE_INFORMATION 2.1 Merge data pointer reduce allocation times 2.2 Add PCI device id to PCI_DEVICE_INFORMATION 2.3 Rename PciDescriptor to avoid confusing. 3. Fix the debug message too long issue. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit f77d35c7f0835150df4be5327dd83152bac5ee39)
* IntelSiliconPkg/header: update PlatformVtdPolicyJiewen Yao2018-05-101-1/+50
| | | | | | | | | | | | | | | Add flexible exception list format: 1) Support Device scope based reporting: Such as, Seg:0/StartBus:0/(Dev:1C|Func:0)/(Dev:0|Func:0) 2) Support PCI VendorId/DeviceId based reporting Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270 Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 71872f7cda66ddf381e7d788750ed69e3e02a3d0)
* IntelSiliconPkg/IntelVTdDxe: Update function commentsBi, Dandan2018-05-102-0/+3
| | | | | | | | | | | | In commit 4ad5f597153c7cb20a968236c2c7d6ff01994350, the parameters of some functions have been updated, but miss to update the comments accordingly. This patch is to update the function comments. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit d654bf852f86902816f0ecddff90aa772f71dd09)
* IntelSiliconPkg/IntelVTdDxe: Improve performance.Jiewen Yao2018-05-107-216/+189
| | | | | | | | | | | | | | | | This patch is to improve IOMMU performance. All WBINVD is removed due to performance issue. CLFLUSH by WriteBackDataCacheRange() is used to only flush the context table or second level page table if they are changed. This patch also removed some unused functions. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 4ad5f597153c7cb20a968236c2c7d6ff01994350)
* IntelSiliconPkg/dsc: Add CacheMaintenanceLib.Jiewen Yao2018-05-101-0/+1
| | | | | | | | | | It will be used by IntelVTdDxe. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 3ccf5a8a41b42fc5116fdc03bc2a273f7f3c5179)
* IntelSiliconPkg: Fix VS2015 NOOPT IA32 build failure in IntelVTdDxeStar Zeng2018-05-106-132/+152
| | | | | | | | | | | | | | | | There are VS2015 NOOPT IA32 build failure like below in IntelVTdDxe. XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __allshl XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __aullshr This patch is to update Vtd.h to use UINT32 instead of UINT64 for bitfields in structure definition, and also update IntelVTdDxe code accordingly. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 76c6f69ccadc7835c9616b077d9ff1b8e46fe49e)
* IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checksHao Wu2018-05-101-2/+4
| | | | | | | | | Add explicit NULL pointer check to make the codes more straight-forward. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit be61fcd2b095f39e250f309fe4a01cf170f5c8e7)
* IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain IDHao Wu2018-05-101-1/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit f5046945b668403a9800e686f804a3ea1e9e79d7)
* IntelSiliconPkg/dsc: Add PlatformVtd sample driver.Jiewen Yao2018-05-101-0/+1
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 9745ddcf8ae78d9fbe8c21a7ff41b848782f8b57)
* IntelSiliconPkg: Add PlatformVTdSample driver.Jiewen Yao2018-05-104-0/+438
| | | | | | | | | | | It provides sample on Platform VTd policy protocol. This protocol is optional. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 5071fb9cd99c6093625c7b3ec16b1dbdbb9cb8dc)
* IntelSiliconPkg/dsc: Add Vtd driver.Jiewen Yao2018-05-101-0/+31
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 642d22424c8e3fc22dff6664a8be3cc832bae6f9)
* IntelSiliconPkg: Add VTd driver.Jiewen Yao2018-05-1012-0/+4818
| | | | | | | | | | | It provides AllocateBuffer/FreeBuffer/Map/Unmap function. It also provides VTd capability yet. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit c049fc99098b08a4a5bae38ff5f06cce8904fc03)
* IntelSiliconPkg/Dec: Add ProtocolGuid.Jiewen Yao2018-05-101-0/+3
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit b7ff5027fed581ef8a94b577b8c44afde4d4178b)
* IntelSiliconPkg/Include: Add PlatformVtdPolicy ProtocolJiewen Yao2018-05-101-0/+100
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 4fd8eda9a3b466bc3ad862f3c5ce807918f8530f)
* IntelSiliconPkg/Include: Add VTD industry standard.Jiewen Yao2018-05-101-0/+344
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit e2d81fb12a0bb9bff19f25e269a3d9db1f626d21)
* IntelSiliconPkg: Add package DSC fileHao Wu2018-05-101-0/+46
| | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=608 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 578dbd52b70061fd3442dc5b050479e4f13b9585)
* MdePkg/DMAR: Add the definition for DMA_CTRL_PLATFORM_OPT_IN_FLAG bitHao Wu2018-05-101-6/+12
| | | | | | | | | | | | | For the support of VTd 2.5, add the BIT definition of DMA_CTRL_PLATFORM_OPT_IN_FLAG Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 8ab0bd2397c9d3922e0c7dbb1aa6f7e08799079f)
* MdePkg/include: Add Acpi.h to DMAR table.Jiewen Yao2018-05-101-0/+2
| | | | | | | | | Suggested-by: Star Zeng <star.zeng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 83a457840e6f903f87c1fc32c71aec26e498d2ab)
* MdeModulePkg/PciBusDxe: Fix VS2012 build failureDandan Bi2018-05-101-0/+5
| | | | | | | | | | | | | | | | | | | Initialize local variable to suppress warning C4703: potentially uninitialized local pointer variable. Both reads (dereferences) of "PciRootBridgeIo" in PciBusDriverBindingStart() are only reached if "gFullEnumeration" is TRUE on entry *and* we successfully open the EfiPciRootBridgeIoProtocol interface. Cc: Star Zeng <star.zeng@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit a012bf6e3e08d1fc878ffb271932e3cbce4a71f6)
* MdeModulePkg Ppi/IoMmu.h: Add EFI_NOT_AVAILABLE_YET return status codeStar Zeng2018-05-101-2/+13
| | | | | | | | | | | | Install IOMMU PPI for pre-memory phase and return EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled, but DMA buffer are not available to be allocated yet. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 20b58eb850ee6d1263bbe175e28d42dd1eaa9d05)
* MdeModulePkg/NvmExpressDxe: Fix data buffer not mapped for Write cmdHao Wu2018-05-101-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Within function NvmExpressPassThru(): The data buffer for the below 2 Admin command: Create I/O Completion Queue command (Opcode 01h) Create I/O Submission Queue command (Opcode 05h) are not mapped to the PCI controller specific addresses. But the current code logic also prevents the below NVM command: Write (Opcode 01h) from mapping its data buffer. Hence, this commit refine the logic to resolve this issue. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 748cd9a68041d00f991eee3570f7150f573d360f)
* MdeModulePkg/PciBusDxe: Install PciEnumerationComplete after PciIoRuiyu Ni2018-05-102-12/+13
| | | | | | | | | | | | | | | | Per PI spec, the PciEnumerationComplete protocol installation should be after PciIo installation. Today's implementation installs the PciEnumerationComplete after hardware enumeration is completed, but before PciIo installation. The change corrects the spec/implementation gap. The change also benefits certain implementation that depends on the PciIo handle in PciEnumerationComplete callback. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 42e8bc7d16aa2ef8d65a19b327d33c64cae54a9c)
* MdeModulePkg/PciBusDxe: reference gFullEnumeration in one fileRuiyu Ni2018-05-103-42/+38
| | | | | | | | | The patch is just a code cleanup with no functionality impact. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 2632981783683f5c37b430c3e8ac2df067810d3a)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 06:24:43 +0000