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* SignedCapsulePkg SystemFirmwareUpdateDxe: Fix failure caused by d69d922Star Zeng2018-07-131-5/+16
| | | | | | | | | | | | | | | | | | d69d9227d046211265de1fab5580c50a65944614 caused system firmware update failure. It is because FindMatchingFmpHandles() is expected to return handles matched, but the function returns all handles found. This patch is to fix the issue. This patch also assigns mSystemFmpPrivate->Handle for "case 1:" path in case the Handle is needed by other place in future. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> (cherry picked from commit 665bfd41ac32b364201c07dc1c5434432730c034)
* SignedCapsulePkg/SystemFirmwareReportDxe: Pass thru on same handleKinney, Michael D2018-07-131-3/+7
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=928 Use HandleProtocol() to pass thru a SetImage() call to the System FMP Protocol that must be on the same handle as the FMP Protocol. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 153f5c7a93be09403891404c06e5b0e24eb019a3)
* SignedCapsulePkg/SystemFirmwareUpdateDxe: Single FMPKinney, Michael D2018-07-131-21/+322
| | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=928 Uninstall all System FMP Protocols for the current FW device. If an FMP Protocol for the current FW device is already present, then install the new System FMP protocol onto the same handle as the FMP Protocol. Otherwise, install the FMP protocol onto a new handle. This supports use cases where multiple capsules for the same system firmware device are processed on the same boot of the platform. It guarantees there is at most one FMP protocol for each system firmware device. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit d69d9227d046211265de1fab5580c50a65944614)
* MdeModulePkg/PciHostBridgeDxe: Make bitwise operands of the same sizeHao Wu2018-06-061-1/+1
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 8df95dd04f467c5626850b34dec564dec918c47d)
* MdeModulePkg/PciHostBridgeDxe: Fix EBC build failureDandan Bi2018-06-061-2/+2
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 7a85e8474127ae6df47337a04797b2b443b57682)
* SecurityPkg:Tcg2Smm: Update TcgNvs info after memory is allocatedZhang, Chao B2018-05-251-7/+12
| | | | | | | | | | | | | Update package format info in _PRS to TcgNvs after memory is allocated. Change-Id: Icfadb350e60d3ed2df332e92c257ce13309c0018 Contributed-under: TianoCore Contribution Agreement 1.1 Cc: Yao Jiewen <jiewen.yao@intel.com> Cc: Long Qin <qin.long@intel.com> Signed-off-by: Zhang, Chao B <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com> (cherry picked from commit 1ea08a3dcdd61c7481ec78ad8b8037ee6ca45402) (cherry picked from commit fb8254478f7259d22d8433f6729307e001b81bdd)
* MdePkg/ResetNotification: Rename to UnregisterResetNotifyRuiyu Ni2018-05-251-1/+1
| | | | | | | | | | | | | | | UEFI Spec uses UnRegisterResetNotify in protocol structure definition but uses UnregisterResetNotify in the function prototype definition. By searching the entire spec, Unregister* is used for SIMPLE_TEXT_INPUT_EX_PROTOCOL.UnregisterKeyNotify(). So choose to use UnregisterResetNotify for consistency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> (cherry picked from commit fcccba378bebd740bfa3e36d684215d739421181)
* MdePkg: Add ResetNotification protocol definitionRuiyu Ni2018-05-252-0/+89
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 342470a6f83a29002ddcf99221343d2e5261eb6b)
* MdePkg/SmmPeriodicSmiLib: Get Periodic SMI Context More RobustlyRuiyu Ni2018-05-211-23/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PeriodicSmiDispatchFunction() in SmmPeriodicSmiLib may assert with "Bad CR signature". Currently, the SetActivePeriodicSmiLibraryHandler() function (invoked at the beginning of the PeriodicSmiDispatchFunction() function) attempts to locate the PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT structure pointer for the current periodic SMI from a given EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT (RegiserContext) structure pointer (using the CR macro). The RegisterContext structure pointer passed to the PeriodicSmiDispatchFunction() is assumed to point to the same RegisterContext structure address given to the SmmPeriodicTimerDispatch2 protocol Register() API in PeriodicSmiEnable(). However, certain SmmPeriodicTimerDispatch2 implementation may copy the RegisterContext to a local buffer and pass that address as the context to PeriodicSmiDispatchFunction() in which case usage of the CR macro to find the parent structure base fails. The patch uses the LookupPeriodicSmiLibraryHandler() function to find the PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT structure pointer. This works even in this scenario since the DispatchHandle returned from the SmmPeriodicTimerDispatch2 Register() function uniquely identifies that registration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> (cherry picked from commit 1e35fcc9ee8b6b991535d9d6731d0e04169b99c0)
* SourceLevelDebugPkg DebugCommUsb3: Return error when debug cap is resetStar Zeng2018-05-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When source level debug is enabled, but debug cable is not connected, XhcResetHC() in XhciReg.c will reset the host controller, the debug capability registers will be also reset. After the code in InitializeUsbDebugHardware() sets DCE bit and LSE bit to "1" in DCCTRL, there will be DMA on 0 (the value of some debug capability registers for data transfer is 0) address buffer, fault info like below will appear when IOMMU based on VTd is enabled. VER_REG - 0x00000010 CAP_REG - 0x00D2008C40660462 ECAP_REG - 0x0000000000F050DA GSTS_REG - 0xC0000000 RTADDR_REG - 0x0000000086512000 CCMD_REG - 0x2800000000000000 FSTS_REG - 0x00000002 FECTL_REG - 0xC0000000 FEDATA_REG - 0x00000000 FEADDR_REG - 0x00000000 FEUADDR_REG - 0x00000000 FRCD_REG[0] - 0xC0000006000000A0 0000000000000000 Fault Info - 0x0000000000000000 Source - B00 D14 F00 Type - 1 (read) Reason - 6 IVA_REG - 0x0000000000000000 IOTLB_REG - 0x1200000000000000 This patch is to return error for the case. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit df67a480eb81821ba21ad6909e2fda287e745834)
* SourceLevelDebugPkg DebugUsb3: Re-Support IOMMUStar Zeng2018-05-116-112/+954
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | de8373fa07f87ca735139bb86c51e2c29fb1d956 could not handle two cases. 1. For the case that the USB3 debug port instance and DMA buffers are from PEI HOB with IOMMU enabled, it was to reallocate the DMA buffers by AllocateAddress with the memory type accessible by SMM environment. But reallocating the DMA buffers by AllocateAddress may fail. 2. At S3 resume, after the code is transferred to PiSmmCpuDxeSmm from S3Resume2Pei, HOB is still needed to be used for DMA operation, but PiSmmCpuDxeSmm has no way to get the HOB at S3 resume. The patch is to re-support IOMMU. For PEI, allocate granted DMA buffer from IOMMU PPI, register IOMMU PPI notification to reinitialize hardware with granted DMA buffer if IOMMU PPI is not present yet. For DXE, map DMA buffer by PciIo in PciIo notification for early DXE, and register DxeSmmReadyToLock notification to reinitialize hardware with granted DXE DMA buffer accessible by SMM environment for late DXE. DebugAgentLib has been managing the instance as Handle in HOB/SystemTable. The Handle(instance) from DebugAgentLib can be used directly in DebugCommunicationLibUsb3. Then DebugCommunicationLibUsb3 could get consistent Handle(instance) from DebugAgentLib. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 75787f6580f331b8cf6765c677c6a8bdccb98270)
* SourceLevelDebugPkg DebugCommUsb3: Refine some formats/commentsStar Zeng2018-05-112-50/+13
| | | | | | | | | | | | Refine some formats/comments and remove some unused prototypes. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit f0c562761f397733e2294c8725512e31c352cb72)
* SourceLevelDebugPkg DebugUsb3: Re-Fix GCC build failuresStar Zeng2018-05-112-5/+1
| | | | | | | | | | | | | | | | | | | | | Fix GCC build failures below. variable 'EvtTrb' set but not used [-Werror=unused-but-set-variable] variable 'Index' set but not used [-Werror=unused-but-set-variable] The build failure could only be caught with -D SOURCE_DEBUG_USE_USB3 build flag. ad6040ec9b5bbc462762331f9738b8e42c0b9c80 needs to be also reverted when reverting IOMMU support patches, otherwise there will be conflict. This patch is to re-do ad6040ec9b5bbc462762331f9738b8e42c0b9c80. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 3ecca0033039cac31845b9dbb9e4a3d6b8148b01)
* Revert "DebugUsb3: Support IOMMU"Star Zeng2018-05-116-842/+129
| | | | | | | | | | | | This reverts commit de8373fa07f87ca735139bb86c51e2c29fb1d956. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 1f279e7a53f5a576682214a550810faff92fd9a1)
* Revert "DebugUsb3: Fix GCC build failures"Star Zeng2018-05-112-1/+5
| | | | | | | | | | | | This reverts commit ad6040ec9b5bbc462762331f9738b8e42c0b9c80. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 373b1d0ee31ea2e2868307ea82277271b18a7be7)
* Revert "DebugUsb3: Check mUsb3Instance before dereferencing it"Star Zeng2018-05-111-1/+1
| | | | | | | | | | | | This reverts commit 6ef394ffe29bbc67038fc16ed540bfe6eed10e16. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit abea3bca8212f8c2ea34da6b9f6315d755537767)
* SourceLevelDebugPkg DebugUsb3: Check mUsb3Instance before dereferencing itStar Zeng2018-05-111-1/+1
| | | | | | | | | Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 6ef394ffe29bbc67038fc16ed540bfe6eed10e16)
* SourceLevelDebugPkg DebugUsb3: Fix GCC build failuresStar Zeng2018-05-112-5/+1
| | | | | | | | | | | | | | | | Fix GCC build failures below. variable 'EvtTrb' set but not used [-Werror=unused-but-set-variable] variable 'Index' set but not used [-Werror=unused-but-set-variable] The build failure could only be caught with -D SOURCE_DEBUG_USE_USB3 build flag. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit ad6040ec9b5bbc462762331f9738b8e42c0b9c80)
* SourceLevelDebugPkg DebugUsb3: Support IOMMUStar Zeng2018-05-116-129/+842
| | | | | | | | | | | | | For PEI, allocate granted DMA buffer from IOMMU PPI. For DXE, map DMA buffer by PciIo. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> (cherry picked from commit de8373fa07f87ca735139bb86c51e2c29fb1d956)
* SourceLevelDebugPkg DebugUsb3: Fix some typosStar Zeng2018-05-114-12/+12
| | | | | | | | | Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit f4043414da4b0415aa97dba83f0e59e2ce4334a9)
* SourceLevelDebugPkg DebugAgentLib: Rename IsBsp to DebugAgentIsBspStar Zeng2018-05-113-8/+8
| | | | | | | | | | | | | For avoiding function name confliction, rename IsBsp to DebugAgentIsBsp. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> (cherry picked from commit a2acb04ca67853519a514a986de11b6bc468d564)
* SourceLevelDebugPkg/DebugCommLibUsb3: Remove IntelFrameworkPkg.decStar Zeng2018-05-112-3/+1
| | | | | | | | | Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 9c6a26d6430f7ca10e6e79e6c9145cbd319944ca)
* SourceLevelDebugPkg/DebugCommLibUsb3Pei: Make sure alloc physical memStar Zeng2018-05-112-9/+24
| | | | | | | | | | | | | | | PI 1.6 has supported pre permanent memory page allocation, to make sure the allocated memory is physical memory for DMA, the patch is to check memory discovered PPI installed or not first before calling AllocatePages. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 364f63c06533a4de83e6f35ee698700bb24f735f)
* IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support.Jiewen Yao2018-05-103-1/+73
| | | | | | | | | | | | If IOMMU is enabled, the legacy BIOS need allow the legacy memory access by the legacy device. The legacy memory is below 1M memory and HighPmm memory. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 60794ee6b0c86c103ab227b0d9c2968c9c74810e)
* IntelSiliconPkg/Vtd: Add more debug info.Jiewen Yao2018-05-101-1/+1
| | | | | | | | | | Add more debug info for reason code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 8d8c487fb9845685a2d7d0489bc0e2b3cca4d5ff)
* IntelSiliconPkg/Vtd: Add missing dump in ExtContext.Jiewen Yao2018-05-101-0/+1
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 224f87932d8cd8a585fa335cdb005fbd05ac3004)
* IntelSiliconPkg/Vtd: Add DMA_CTRL_PLATFORM_OPT_IN_FLAG dumpJiewen Yao2018-05-102-0/+8
| | | | | | | | Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 6cea3c1b51148c34892d03a87e9cb5f253f98b3c)
* IntelSiliconPkg/Vtd: Add MapHandleInfo in VtdDxe.Jiewen Yao2018-05-102-13/+144
| | | | | | | | | | | This information is to record which device requested which DMA buffer. It can be used for DMA buffer analysis. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 6d2d2e6e5b6619dd46d944b90629739c97ee8a65)
* IntelSiliconPkg VTdPmrPei: Add PcdVTdPeiDmaBufferSize(S3)Star Zeng2018-05-103-7/+22
| | | | | | | | | | | Add PcdVTdPeiDmaBufferSize(S3) to replace the hard coded value TOTAL_DMA_BUFFER_SIZE and TOTAL_DMA_BUFFER_SIZE_S3 in IntelVTdPmrPei. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 339cb0af96f768bfefee81bf7995a608adeb2125)
* IntelSiliconPkg VTdPmrPei: Return SUCCESS when Mapping == NULL in UnmapStar Zeng2018-05-101-2/+2
| | | | | | | | | | | | | | | | NULL is returned to Mapping when Operation is BusMasterCommonBuffer or BusMasterCommonBuffer64 in PeiIoMmuMap(). So Mapping == NULL is valid when calling PeiIoMmuUnmap(). 940dbd071e9f01717236af236740aa0da716805f wrongly changed EFI_SUCCESS to EFI_INVALID_PARAMETER when Mapping == NULL in PeiIoMmuUnmap(). This patch is to correct it. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit abe63fa7dc0de3e1875139a4abd62357795f52d7)
* IntelSiliconPkg IntelVTdPmrPei: Install IOMMU PPI for pre-memory phaseStar Zeng2018-05-101-11/+66
| | | | | | | | | | | | Install IOMMU PPI for pre-memory phase and return EFI_NOT_AVAILABLE_YET to indicate that DMA protection has been enabled, but DMA buffer are not available to be allocated yet. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 940dbd071e9f01717236af236740aa0da716805f)
* IntelSiliconPkg IntelVTdPmrPei: Install IoMmu PPI before enabling PMRStar Zeng2018-05-101-34/+29
| | | | | | | | | | | | Then the consumer of IoMmu PPI has opportunity to get granted DMA buffer (by callback) to replace old buffer before it is forbidden by enabling PMR. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit ed0e52fc9a533fa809c56afbdfd7c350f17e22cc)
* IntelSiliconPkg PlatformVTdSampleDxe: State it is only for dev/debugStar Zeng2018-05-102-2/+8
| | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 17ac6b23dc92c9a052a252055bec46c70a4b16ee)
* IntelSiliconPkg IntelVTdDxe: Fix flush cache issueStar Zeng2018-05-101-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes flush cache issue in CreateSecondLevelPagingEntryTable(). We found some video cards still not work even they have been added to the exception list. In CreateSecondLevelPagingEntryTable(), the check "(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done" will be executed, then the FlushPageTableMemory operations at the end of the function will be skipped. Instead of "goto Done", this patch uses "break" to break the for loops, then the FlushPageTableMemory operations at the end of the function could have opportunity to be executed. The patch also fixes a miscalculation for Lvl3End. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit bac7f02365b1d24cc6ac93fe853a25ebb8df6efe)
* IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issueStar Zeng2018-05-101-3/+7
| | | | | | | | | | | Fix DMA does not work issue when system memory is not greater than 4G. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 1d4c17a6ef1a06023cb533d108556c419bdb1fed)
* IntelSiliconPkg IntelVTdPmrPei: Get high top by host address widthStar Zeng2018-05-103-178/+5
| | | | | | | | | | Get high top by host address width instead of resource HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit b2725f57c7a1e6feeb176f1563a4f1a8c2eb6c6f)
* IntelSiliconPkg IntelVTdDxe: Remove mVtdHostAddressWidthMaskStar Zeng2018-05-103-5/+1
| | | | | | | | | | | mVtdHostAddressWidthMask is not been used at all, its definition and related code could be removed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 9eaa902a52ec1ab0032d0c5a23f9d16493bcb4c5)
* IntelSiliconPkg IntelVTdPmrPei: Use HostAddressWidth in DMAR correctlyStar Zeng2018-05-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | According to VTd spec, HostAddressWidth + 1 should be used as the real host address width value. Host Address Width: This field indicates the maximum DMA physical addressability supported by this platform. The system address map reported by the BIOS indicates what portions of this addresses are populated. The Host Address Width (HAW) of the platform is computed as (N+1), where N is the value reported in this field. For example, for a platform supporting 40 bits of physical addressability, the value of 100111b is reported in this field. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 9dd8b1908e7d0585ba6b77d4586f6091842d925c)
* IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.LimitStar Zeng2018-05-101-3/+3
| | | | | | | | | | | | | | According to VTd spec, the real hardware decoded limit should be PHMR/PLMR.Limit value + alignment value. "Bits N:0 of the limit register are decoded by hardware as all 1s." Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit e8097a74b763bfc439c273ddfef8e1d542d83ea7)
* IntelSiliconPkg IntelVTdDxe: Fix potential NULL pointer dereferenceStar Zeng2018-05-101-3/+3
| | | | | | | | | | | | | The implementation of MdeModulePkg\Universal\Acpi\AcpiTableDxe reserves first entry of RSDT/XSDT to FADT, the first entry value is 0 when FADT is not installed. So the RSDT/XSDT parsing code should check the entry value first before checking the table signature. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 01bd1c98fa83ef4449798fcf206fbd40db97b2d6)
* IntelSiliconPkg IntelVTdDxe: Support early SetAttributes()Star Zeng2018-05-104-3/+202
| | | | | | | | | | Support early SetAttributes() before DMAR table is installed. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 0bc94c748bc9b8645dd0566535708d88a5be0fe1)
* IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operationStar Zeng2018-05-104-31/+26
| | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 3a71670618dfa463b3377b752858df7964ad038c)
* IntelSiliconPkg IntelVTdDxe: Signal AcpiNotificationFunc() initiallyStar Zeng2018-05-102-4/+15
| | | | | | | | | | | Signal AcpiNotificationFunc() initially for the case that DMAR table has been installed when creating event. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit dcd39e09ff3dbec468152a32b343e68e6c87f4b6)
* IntelSilicon: Correct function description for AllocateBufferStar Zeng2018-05-103-3/+3
| | | | | | | | | | | | DUAL_ADDRESS_CYCLE is missing in the EFI_UNSUPPORTED return status description. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> (cherry picked from commit 34e18d1758980d2a01a4503e2be6c06eba59c6ec)
* IntelSiliconPkg IntelVTdDxe: Do not SetupVtd againStar Zeng2018-05-103-5/+10
| | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Tested-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 7729e3c448a116eb5b6198f0f70355f421df43fa)
* IntelSiliconPkg IntelVTdDxe: Use ACPI table event to get DMAR tableStar Zeng2018-05-104-30/+46
| | | | | | | | | | | | Use ACPI table event to get DMAR table instead of using ACPI SDT notification as ACPI SDT is optional and the default value of PcdInstallAcpiSdtProtocol is FALSE in MdeModulePkg.dec. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit f6f486e7bf7667ca7bcf50d808e056bd5ac7deaf)
* IntelSiliconPkg/VtdPeiSample: Add premem support.Jiewen Yao2018-05-102-35/+201
| | | | | | | | | | | | | | | Before memory is ready, this sample produces one VTd engine. After memory and silicon is initialized, this sample produces both IGD VTd engine and all-rest VTd engine by reinstall the FV_INFO_PPI. This update is to demonstrate how to support pre-mem VTd usage. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit af807bb98682d0b11dc37188d80fb70687ae2512)
* IntelSiliconPkg/VtdPmrPei: Add premem support.Jiewen Yao2018-05-106-596/+1358
| | | | | | | | | | | | | | | Remove memory discovered dependency to support both premem VTD_INFO_PPI and postmem VTD_INFO_PPI. If VTD_INFO_PPI is installed before memory is ready, this driver protects all memory region. If VTD_INFO_PPI is installed or reinstalled after memory is ready, this driver allocates DMA buffer and protect rest. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit a1e7cd0b020ac024015095068b02e03a68edd96c)
* IntelSiliconPkg/VTdDxe: return unsupported for exceptionlistJiewen Yao2018-05-101-2/+3
| | | | | | | | | | | Since the exception list is not a recommended way, we returns EFI_UNSUPPORTED in the sample code. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit e5d847476ab6386bef4e3c70e76f5d26c606ed5e)
* IntelSiliconPkg/VTdDxe: Change EBS Event TPL to CALLBACK.Jiewen Yao2018-05-101-2/+2
| | | | | | | | | | | Change ExitBootServices TPL to CALLBACK, so that a device can disable BME before IOMMU grants access right. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> (cherry picked from commit 01df510319f3de8eb358e400dae786cddc160180)
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 18:12:36 +0000