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* pip: bump antlr4-python3-runtime from 4.7.1 to 4.11.1dependabot/pip/antlr4-python3-runtime-4.11.1dependabot[bot]2023-01-061-1/+1
| | | | | | | | | | | | Bumps [antlr4-python3-runtime](http://www.antlr.org) from 4.7.1 to 4.11.1. --- updated-dependencies: - dependency-name: antlr4-python3-runtime dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] <support@github.com>
* Maintainers.txt: Update reviewers for OVMF/Confidential ComputingMichael Roth2023-01-061-1/+1
| | | | | | | | | | | Add myself as a reviewer for OVMF/Confidential Computing patches. Remove Brijesh while at it, since he is no longer at AMD, and the email is no longer valid. Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* SecurityPkg: Move TdTcg2Dxe from OvmfPkg to SecurityPkgMin M Xu2023-01-068-11/+15
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4194 The TdTcg2Dxe lives in the OvmfPkg instead of the SecurityPkg. Having the TdTcg2Dxe at the same place as Tcg2Dxe will be easier for platforms to consume. Definition of PcdCcEventlogAcpiTableLaml and PcdCcEventlogAcpiTableLasa are also moved from OvmfPkg.dec to SecurityPkg.dec. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Arti Gupta <ARGU@microsoft.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* Maintainers.txt: designate Gerd Hoffmann as UefiCpuPkg reviewerLaszlo Ersek2023-01-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I suggest that Gerd be notified about all UefiCpuPkg patches, so he may take a quick look at, or (by his preference) even test, the proposed change, in a genuine QEMU/KVM environment. Assuming this patch is accepted -- subsequently, please *wait* for Gerd's approval on UefiCpuPkg patches, before merging them. Notes: - It's perfectly fine for a reviewer to give an A-b just so the review process be unblocked, if they don't have anything to add, or don't have time to review or test in detail. The point is that someone outside of Intel should *consistently get a chance* to raise concerns about UefiCpuPkg patches before they are merged. - My A-b's and R-b's on UefiCpuPkg patches were never supposed to be "sufficient", only "necessary", for merging. The intent is the same here, with Gerd's designation as a reviewer. Cc: Andrew Fish <afish@apple.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20230103160539.87830-1-lersek@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* .azurepipelines: Skip CodeCoverage if coverage.xml not foundGua Guo2023-01-061-0/+8
| | | | | | | | | | Skip CodeCoverage if coverage.xml not found Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Maintainers.txt: Update NetworkPkg & MM modules ReviewerWu, Jiaxin2023-01-061-2/+1
| | | | | | | | | This is to change NetworkPkg & MM modules Reviewer. Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* OvmfPkg/SmmCpuFeaturesLib: drop obsolete API implementationLaszlo Ersek2023-01-041-31/+0
| | | | | | | | | | | | | | | | | | | | | Commit 0426115b6738 ("UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.h", 2022-12-21) removed the declaration of the function SmmCpuFeaturesAllocatePageTableMemory() from the "SmmCpuFeaturesLib.h" library class header. Remove the API's (null-)implementation from OvmfPkg/SmmCpuFeaturesLib as well. Testing: OVMF builds, boots, and suspends/resumes (see earlier in this series). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4235 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg/SmmCpuFeaturesLib: drop obsolete API implementationLaszlo Ersek2023-01-041-28/+0
| | | | | | | | | | | | | | | | | | | | | | | Commit 0426115b6738 ("UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.h", 2022-12-21) removed the declaration of the function SmmCpuFeaturesAllocatePageTableMemory() from the "SmmCpuFeaturesLib.h" library class header. Remove the API's (null-)implementation from UefiCpuPkg/SmmCpuFeaturesLib as well. Build-tested with: build -a IA32 -a X64 -b NOOPT -p UefiCpuPkg/UefiCpuPkg.dsc -t GCC5 Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4235 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Dun Tan <dun.tan@intel.com>
* OvmfPkg: raise DXEFV size to 13 MB in the traditional platform FDFsLaszlo Ersek2023-01-043-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to the "cadence" mentioned in commit d272449d9e1e ("OvmfPkg: raise DXEFV size to 11 MB", 2018-05-29), it's been ~1.75 years since commit 5e75c4d1fe4f ("OvmfPkg: raise DXEFV size to 12 MB", 2020-03-11), and we've outgrown DXEFV again (with NOOPT builds). Increase the DXEFV size to 13MB now. Do not modify all platform FDF files under OvmfPkg. "BhyveX64.fdf" is still at 11MB, "OvmfXen.fdf" at 10MB. The "AmdSevX64.fdf", "CloudHvX64.fdf", "IntelTdxX64.fdf" and "MicrovmX64.fdf" flash devices could be modified similarly (from 12MB to 13MB), but I don't use or build those platforms. Tested on: - IA32, q35, SMM_REQUIRE, Fedora 30 guest - X64, pc (i440fx), no SMM, RHEL-7.9 guest - IA32X64, q35, SMM_REQUIRE, RHEL-7.9 guest Test steps: - configure 3 VCPUs - boot - run "taskset -c $I efibootmgr" with $I covering 0..2 - systemctl suspend - resume from virt-manager - run "taskset -c $I efibootmgr" with $I covering 0..2 Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Julien Grall <julien@xen.org> Cc: Min Xu <min.m.xu@intel.com> Cc: Peter Grehan <grehan@freebsd.org> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4236 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/QemuVideoDxe/VbeShim.sh: remove end-of-options delimiter for nasmLaszlo Ersek2023-01-041-2/+5
| | | | | | | | | | | | | | | | | | | | | | | Per my bisection: nasm broke the parsing of the "--" end-of-options delimiter in commit 55568c1193df ("nasm: scan the command line twice", 2016-10-03), part of the nasm-2.13 release. The parsing remains broken in at least nasm-2.15.03. The (invalid) error message is: "more than one input file specified". I've filed the following ticket for upstream nasm (and ndisasm): <https://bugzilla.nasm.us/show_bug.cgi?id=3392829>. Since the delimiter is not necessary in practice (due to $STEM being "VbeShim", i.e., not starting with a hyphen), simply remove the delimiter. Tested by enabling DEBUG in "VbeShim.asm", running the script, building OVMF, booting Windows 7, and checking the firmware log (debug console). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3876 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdeModulePkg/Bus/Pci/XhciDxe: Reset port if status change returns an errorSean Rhodes2023-01-041-1/+10
| | | | | | | | Force resetting the port by clearing the USB_PORT_STAT_C_RESET bit in PortChangeStatus when XhcPollPortStatusChange fails Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* .azurepipelines: Install code coverage toolGua Guo2023-01-045-1/+51
| | | | | | | | | | | | | | | | | | | For Windows add below tool for code coverage 1. OpenCppCoverage: parsing pdb file to generate coverage data 2. pycobertura: show up html format data for coverage data For Linux add below tool for code coverage 1. lcov: parsing gcda gcno file to generate coverage data 2. lcov-cobertura: convert coverage data to cobertura format 3. pycobertura: show up html format data for coverage data Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* BaseTools/Plugin: Add coverage support for Unit TestGua Guo2023-01-041-1/+100
| | | | | | | | | | | | | | | | For GCC, use lcov to generate Unit Test code coverage report For VS2019, use OpenCppCoverage to generate code coverage report Cc: Bob Feng <bob.c.feng@intel.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Liming Gao <gaoliming@bysoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* UnitTestFrameworkPkg: Add code coverage support for GCCGua Guo2023-01-043-1/+44
| | | | | | | | | | | | In order to collect code coverage after running executable file, generate *.gcda and *.gcno file that require by lcov tool to generate code coverage report. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm:Fix PF issue caused by smm page table codeTan, Dun2023-01-031-14/+27
| | | | | | | | | | | | | | | When setting new page table pool to RO, only disable/enable WP when Cr0.WP has been set to 1 to fix potential PF caused by b822be1a20 (UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism). With previous code, if someone want to modify the page table and Cr0.WP has been cleared before modify page table, Cr0.WP may be set to 1 again since new pool may be generated during this process Then PF fault may happens. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* BaseTools: Generate deps for Arm targetsJake Garver via groups.io2022-12-301-1/+1
| | | | | | | | | | Prior to this change, deps were not generated for Arm and AARCH64 libraries when MODULE_TYPE was BASE, SEC, PEI_CORE, or PIEM. That resulted in bad incremental builds. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* BaseTools: Use BUILD_CC when checking gcc version in DevicePathJake Garver2022-12-301-1/+1
| | | | | | | | | | When checking the version in DevicePath's Makefile, use BUILD_CC instead of assuming "gcc". BUILD_CC is set in header.makefile and is the compiler that will actually be used to build DevicePath. It defaults to "gcc", but may be overridden. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* BaseTools: Fix IA32 UINT64 alignment for CLANG toolchainsPedro Falcato2022-12-301-9/+9
| | | | | | | | | | | | | | | | | Currently, UINT64 is not 8-byte aligned for CLANG* toolchains on IA32, which causes ABI differences between IA32 and X64 in such simple examples as: struct S {UINT32 A; UINT64 B;}; Pass -malign-double to align it to 8 bytes, as is done for GCC already. Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Cc: Marvin H?user <mhaeuser@posteo.de> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* OvmfPkg: Use NestedInterruptTplLib in nested interrupt handlersMichael Brown2022-12-2312-6/+22
| | | | | | | | | | | | | | | | Prevent stack underrun in the event of a timer interrupt storm in LocalApicTimerDxe and 8254TimerDxe interrupt handlers by using the helper functions provided by NestedInterruptTplLib. This fixes the same problem as addressed in commit 239b50a86 ("OvmfPkg: End timer interrupt later to avoid stack overflow under load"), but does so without breaking nested timer interrupts. Cc: Paolo Bonzini <pbonzini@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2815 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4162 Signed-off-by: Michael Brown <mcb30@ipxe.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: Add library to handle TPL from within nested interrupt handlersMichael Brown2022-12-236-0/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UEFI requires us to support nested interrupts, but provides no way for an interrupt handler to call RestoreTPL() without implicitly re-enabling interrupts. In a virtual machine, it is possible for a large burst of interrupts to arrive. We must prevent such a burst from leading to stack underrun, while continuing to allow nested interrupts to occur. This can be achieved by allowing, when provably safe to do so, an inner interrupt handler to return from the interrupt without restoring the TPL and with interrupts remaining disabled after IRET, with the deferred call to RestoreTPL() then being issued from the outer interrupt handler. This is necessarily messy and involves direct manipulation of the interrupt stack frame, and so should not be implemented as open-coded logic within each interrupt handler. Add the Nested Interrupt TPL Library (NestedInterruptTplLib) to provide helper functions that can be used by nested interrupt handlers in place of RaiseTPL()/RestoreTPL(). Example call tree for a timer interrupt occurring at TPL_APPLICATION with a nested timer interrupt that makes its own call to RestoreTPL(): outer TimerInterruptHandler() InterruptedTPL == TPL_APPLICATION ... IsrState->InProgressRestoreTPL = TPL_APPLICATION; gBS->RestoreTPL (TPL_APPLICATION); EnableInterrupts(); dispatch a TPL_CALLBACK event gEfiCurrentTpl = TPL_CALLBACK; nested timer interrupt occurs inner TimerInterruptHandler() InterruptedTPL == TPL_CALLBACK ... IsrState->InProgressRestoreTPL = TPL_CALLBACK; gBS->RestoreTPL (TPL_CALLBACK); EnableInterrupts(); DisableInterrupts(); IsrState->InProgressRestoreTPL = TPL_APPLICATION; IRET re-enables interrupts ... finish dispatching TPL_CALLBACK events ... gEfiCurrentTpl = TPL_APPLICATION; DisableInterrupts(); IsrState->InProgressRestoreTPL = 0; sees IsrState->DeferredRestoreTPL == FALSE and returns IRET re-enables interrupts Example call tree for a timer interrupt occurring at TPL_APPLICATION with a nested timer interrupt that defers its call to RestoreTPL() to the outer instance of the interrupt handler: outer TimerInterruptHandler() InterruptedTPL == TPL_APPLICATION ... IsrState->InProgressRestoreTPL = TPL_APPLICATION; gBS->RestoreTPL (TPL_APPLICATION); EnableInterrupts(); dispatch a TPL_CALLBACK event ... finish dispatching TPL_CALLBACK events ... gEfiCurrentTpl = TPL_APPLICATION; nested timer interrupt occurs inner TimerInterruptHandler() InterruptedTPL == TPL_APPLICATION; ... sees InterruptedTPL == IsrState->InProgressRestoreTPL IsrState->DeferredRestoreTPL = TRUE; DisableInterruptsOnIret(); IRET returns without re-enabling interrupts DisableInterrupts(); IsrState->InProgressRestoreTPL = 0; sees IsrState->DeferredRestoreTPL == TRUE and loops IsrState->InProgressRestoreTPL = TPL_APPLICATION; gBS->RestoreTPL (TPL_APPLICATION); <-- deferred call EnableInterrupts(); DisableInterrupts(); IsrState->InProgressRestoreTPL = 0; sees IsrState->DeferredRestoreTPL == FALSE and returns IRET re-enables interrupts Cc: Paolo Bonzini <pbonzini@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4162 Signed-off-by: Michael Brown <mcb30@ipxe.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: Send EOI before RestoreTPL() in timer interrupt handlersMichael Brown2022-12-232-6/+4
| | | | | | | | | | | | | | | | Deferring the EOI until after the call to RestoreTPL() means that any callbacks invoked by RestoreTPL() will run with timer interrupt delivery disabled. If any such callbacks themselves rely on timers to implement timeout loops, then the callbacks will get stuck in an infinite loop from which the system will never recover. This reverts commit 239b50a86 ("OvmfPkg: End timer interrupt later to avoid stack overflow under load"). Cc: Paolo Bonzini <pbonzini@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4162 Signed-off-by: Michael Brown <mcb30@ipxe.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PlatformInitLib: pass through reservations from qemuGerd Hoffmann2022-12-231-0/+16
| | | | | | | | | | | | | | | | | | qemu uses the etc/e820 fw_cfg file not only for memory, but also for reservations. Handle reservations by adding resource descriptor hobs for them. A typical qemu configuration has a small reservation between lapic and flash: # sudo cat /proc/iomem [ ... ] fee00000-fee00fff : Local APIC feffc000-feffffff : Reserved <= HERE ffc00000-ffffffff : Reserved [ ... ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg: fix PlatformConfigGerd Hoffmann2022-12-233-2/+4
| | | | | | | | The Hii form is named "MainFormState" and the EFI variable is named "PlatformConfig". Take into account the different names. Fixes: aefcc91805fd ("OvmfPkg/PlatformDxe: Handle all requests in ExtractConfig and RouteConfig") Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiPayloadPkg: Fix boot issue for non-universal payloadGuo Dong2022-12-221-3/+4
| | | | | | | | | | | | | | | BDS module was moved from DXEFV to newly created BDSFV recently. Non-universal UEFI payload doesn't support multiple FV, so it failed to boot since BDS module could not be found. This patch add BDS back to DXEFV when UNIVERSAL_PAYLOAD is not set. Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com>
* ArmVirtPkg: Remove CcProbeLib from ArmVirtQemu.dscMin M Xu2022-12-221-1/+0
| | | | | | | | | | | Since CcProbeLib is not used in AcpiPlatformDxe, CcProbeLib can be removed from ArmVirtQemu.dsc. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/AcpiPlatformDxe: Check PcdConfidentialComputingGuestAttrMin M Xu2022-12-222-5/+3
| | | | | | | | | | | | | | | | | | | | | PcdConfidentialComputingGuestAttr can be used to check the cc guest type, including td-guest or sev-guest. CcProbe() can do the same thing but CcProbeLib should be included in the dsc which uses AcpiPlatformDxe. The difference between PcdConfidentialComputingGuestAttr and CcProbe() is that PcdConfidentialComputingGuestAttr cannot be used in multi-processor scenario but CcProbe() can. But there is no such issue in AcpiPlatformDxe. So we use PcdConfidentialComputingGuestAttr instead of CcProbeLib so that it is simpler. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* PcAtChipsetPkg: Move RTC PCD to dynamic PCDKasimX Liu2022-12-221-8/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4193 In order to remove RTC_INDEX/RTC_TARGET from the UplBuild macro list,change the RTC_INDEX /RTC_TARGET type from PcdsFixedAtBuild to PcdsDynamicEx Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
* tools_def: add -fno-omit-frame-pointer to GCC48_{IA32,X64}_CC_FLAGSGerd Hoffmann2022-12-221-2/+2
| | | | | | | | Fixes problems due to code assuming it runs with frame pointers and thus updates rbp / ebp registers when switching stacks. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Liming Gao <gaoliming@byosoft.com.cn>
* tools_def: remove GCC_IA32_CC_FLAGS/GCC_X64_CC_FLAGSGerd Hoffmann2022-12-221-2/+0
| | | | | | | They are not used anywhere. Remove them. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* CryptoPkg: Need to enable crypto functionsJudah Vang2022-12-212-7/+13
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3992 V2: Update Readme and CryptoPkg.dsc to reflect changes and be in sync. V1: Enable CryptAes for PEI phase. Enable CryptHkdf for SMM phase. Update Readme.md Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Nishant C Mistry <nishant.c.mistry@intel.com> Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Nishant C Mistry <nishant.c.mistry@intel.com> Signed-off-by: Judah Vang <judah.vang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Simplify the code to set smm page table as ROTan, Dun2022-12-214-259/+136
| | | | | | | | | | | | | Simplify the code to set memory used by smm page table as RO. Since memory used by smm page table are in PageTablePool list, we only need to set all PageTablePool as ReadOnly in smm page table itself. Also, we only need to flush tlb once after setting all page table pool as Read Only. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.hTan, Dun2022-12-211-25/+0
| | | | | | | | | | | Remove SmmCpuFeaturesAllocatePageTableMemory in this headfile. This API is not used by PiSmmCpuDxeSmm driver any more. Also no other files use this API. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanismduntan2022-12-215-66/+172
| | | | | | | | | | | | | | | | | | Introduce page table pool mechanism for smm page table to simplify page table memory management and protection. This mechanism has been used in DxeIpl. The basic idea is to allocate a bunch of continuous pages of memory in advance, and all future page tables consumption will happen in those pool instead of system memory. Since we have centralized page tables, we only need to mark all page table pools as RO, instead of searching page table memory layer by layer in smm page table. Once current page table pool has been used up, another memory pool will be allocated and the new pool will also be set as RO if current page table memory has been marked as RO. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* OvmfPkg/OvmfXen: Build platform info HOB in XenPlatformPeiAnthony PERARD2022-12-212-0/+21
| | | | | | | | | | | | | | Copy the function BuildPlatformInfoHob() from OvmfPkg/PlatformPei. QemuFwCfgLib expect this HOB to be present, or fails to do anything. InternalQemuFwCfgIsAvailable() from QemuFwCfgPeiLib module will not check if the HOB is actually present for example and try to use a NULL pointer. Fixes: cda98df16228 ("OvmfPkg/QemuFwCfgLib: remove mQemuFwCfgSupported + mQemuFwCfgDmaSupported") Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/PlatformInitLib: Implement multi-core accept memory for TDVFMin M Xu2022-12-212-49/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 TDVF once accepts memory only by BSP. To improve the boot performance this patch introduce the multi-core accpet memory. Multi-core means BSP and APs work together to accept memory. TDVF leverages mailbox to wake up APs. It is not enabled in MpInitLib (Which requires SIPI). So multi-core accept memory cannot leverages MpInitLib to coordinate BSP and APs to work together. So TDVF split the accept memory into 2 phases. - AcceptMemoryForAPsStack: BSP accepts a small piece of memory which is then used by APs to setup stack. We assign a 16KB stack for each AP. So a td-guest with 256 vCPU requires 255*16KB = 4080KB. - AcceptMemory: After above small piece of memory is accepted, BSP commands APs to accept memory by sending AcceptPages command in td-mailbox. Together with the command and accpet-function, the APsStack address is send as well. APs then set the stack and jump to accept-function to accept memory. AcceptMemoryForAPsStack accepts as small memory as possible and then jump to AcceptMemory. It fully takes advantage of BSP/APs to work together. After accept memory is done, the memory region for APsStack is not used anymore. It can be used as other private memory. Because accept-memory is in the very beginning of boot process and it will not impact other phases. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Enable APs to accept memory for TDVFMin M Xu2022-12-212-2/+63
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 TDVF APs once did nothing but spin around to wait for the Wakeup command. This patch enables APs to handle the AcceptPages command. Once APs find the AcceptPages command, it set its stack and jump to the function of ApAcceptMemoryResourceRange (which will be introduced in the following patch). Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/Sec: Move TDX APs related nasm code to IntelTdxAPs.nasmMin M Xu2022-12-213-106/+68
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 This patch moves the TDX APs nasm code from SecEntry.nasm to IntelTdxAPs.nasm. IntelTdxX64 and OvmfPkgX64 use the same nasm so that it can be easier to be managed. In the following patch there will be AcceptMemory related changes in IntelTdxAPs.nasm. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Add TdxMailboxLibNull in some platform dscMin M Xu2022-12-215-1/+5
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 In the following patches TdxMailboxLib will be included in PlatformInitLib. While PlatformInitLib is imported by some IA32/X64 platforms (for example AmdSevX64.dsc). So TdxMailboxLibNull is added in those platforms which don't support TDX feature. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/TdxMailboxLib: Add NULL instance of TdxMailboxLibMin M Xu2022-12-212-5/+36
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 TdxMailboxLib is designed only for TDX guest which arch is X64. This patch set the VALID_ARCHITECTURES of TdxMailboxLib as X64. Because in the following patches TdxMailboxLib will be included in PlatformInitLib. While PlatformInitLib is imported by some X64 platforms (for example AmdSevX64.dsc). So we need a NULL instance of TdxMailboxLib which VALID_ARCHITECTURES is X64 as well. Based on this consideration we design TdxMailboxLibNull. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/TdxMailboxLib: Delete global variablesMin M Xu2022-12-211-12/+10
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 TdxMailboxLib once was designed to be used in DXE phase. But now it is going to be used in SEC/PEI phase (in the following patches). Global variables are not allowed. The library is refactored after those global variables are deleted. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* SecurityPkg: deprecate RpmcLib and VariableKeyLibJian J Wang2022-12-218-291/+0
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2594 There's no real usage of these two libraries. They're deprecated. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nishant C Mistry <nishant.c.mistry@intel.com> Cc: Judah Vang <judah.vang@intel.com> Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiPayloadPkg: Fixed that The UPL info section is not aligned at 4-byteMarsX Lin2022-12-211-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4196 Align .upld_info with 4-byte boundary by spec Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* MdePkg: Fix typos and spacing in Library/PerformanceLib.hRebecca Cran2022-12-211-31/+31
| | | | | | | | | | | | - Fix typos of "disable". - Fix typos of "performance". - Fix missing spaces. - Use comma instead of period when the sentence continues on the next line. - Fix typo of "PERF_CORE_LOAD_IMAGE". Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix typo of EFI_INVALID_PARAMETER in Protocol/UsbIo.hRebecca Cran2022-12-211-2/+2
| | | | | | | | Fix typo of EFI_INVALID_PARAMETER in Protocol/UsbIo.h by adding a missing 'R'. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Bus/Pci/XhciDxe: Check port is compatible before getting PSIVSean Rhodes2022-12-213-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol Speed ID Value) indices are shared between Protocol Speed ID DWORD' in the extended capabilities registers for both USB2 (Full Speed) and USB3 (Super Speed). An example can be found below: XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps XhciPsivGetPsid: found 3 PSID entries XhciPsivGetPsid: looking for port speed 1 XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12 XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500 XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480 XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps XhciPsivGetPsid: found 3 PSID entries XhciPsivGetPsid: looking for port speed 1 XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5 XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10 XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248 The result is edk2 detecting USB2 devices as USB3 devices, which consequently causes enumeration to fail. To avoid incorrect detection, check the Compatible Port Offset to find the starting Port of Root Hubs that support the protocol. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/XhciDxe/Xhci: Don't check for invalid PSIVMatt DeVillier2022-12-211-19/+25
| | | | | | | | | | | | | PSID matching relies on comparing the PSIV against the PortSpeed value. This patch stops edk2 from checking for a PSIV of 0, as it is not valid; this reduces the number of register access by approximately 6 per second. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiPayloadPkg: Add CpuPageTableLib required by MpInitLib.Yuanhao Xie2022-12-201-0/+1
| | | | | | | | Add CpuPageTableLib required by MpInitLib in UefiPayloadPkg. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* OvmfPkg: Add CpuPageTableLib required by MpInitLib.Yuanhao Xie2022-12-207-4/+13
| | | | | | | | Add CpuPageTableLib required by MpInitLib in OvmfPkg. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Has APs in 64 bit long-mode before booting to OS.Xie, Yuanhao2022-12-207-200/+184
| | | | | | | | | | | | | | | | | | | | | | During the finalization of Mp initialization before booting into the OS, depending on whether Mwait is supported or not, AsmRelocateApLoop places Aps in MWAIT-loop or HLT-loop. Since paging is necessary for long mode, the original implementation of moving APs to 32-bit was to disable paging to ensure that the booting does not crash. The current modification creates a page table in reserved memory, avoiding switching modes and reclaiming memory by OS. This modification is only for 64 bit mode. More specifically, we keep the AMD logic as the original code flow, extract and update the Intel-related code, where the APs would stay in 64-bit, and run in a Mwait or Hlt loop until the OS wake them up. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Duplicated AsmRelocateApLoop as AsmRelocateApLoopAmdYuanhao Xie2022-12-205-20/+235
| | | | | | | | AsmRelocateApLoop is replicated for future Intel Logic Extraction, further brings AP into 64-bit, and enables paging. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 15:30:02 +0000