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* pip: bump edk2-pytool-extensions from 0.26.4 to 0.27.4dependabot/pip/edk2-pytool-extensions-0.27.4dependabot[bot]2024-05-171-1/+1
| | | | | | | | | | | | | | Bumps [edk2-pytool-extensions](https://github.com/tianocore/edk2-pytool-extensions) from 0.26.4 to 0.27.4. - [Release notes](https://github.com/tianocore/edk2-pytool-extensions/releases) - [Commits](https://github.com/tianocore/edk2-pytool-extensions/compare/v0.26.4...v0.27.4) --- updated-dependencies: - dependency-name: edk2-pytool-extensions dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] <support@github.com>
* MdeModulePkg: Potential UINT32 overflow in S3 ResumeCountShanmugavel Pakkirisamy2024-05-171-4/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4677 Attacker able to modify physical memory and ResumeCount. System will crash/DoS when ResumeCount reaches its MAX_UINT32. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Pakkirisamy ShanmugavelX <shanmugavelx.pakkirisamy@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2024-05-152-0/+2
| | | | | | | | | | | | | Declare InternalAssertJumpBuffer as EXTERN Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Shun Cheng Liu <adam.liu@tw.synaptics.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg: Add MmUnblockMemoryLib to MdeLibs.dscRay Ni2024-05-101-1/+2
| | | | | | | | | | | | | | | | | | MdeLibs.dsc.inc included some default libraries provided by MdePkg. Platform can include MdeLibs.dsc.inc file to avoid some potential incompatible changes to platform dsc file in future. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* DynamicTablesPkg: Adds integer to the AML package nodeAbdul Lateef Attar2024-05-102-1/+107
| | | | | | | | | | | Adds an AmlAddIntegerToNamedPackage() API to generate AML code, which adds an integer value to the package node. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: Updated SpcrTable structure for Revision_4praveensankarn2024-05-091-0/+32
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4656 In SPCR table, 4 structure members have been added newly as per SPCR table Revision 4, which has to be added in MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h. Signed-off-by: Praveen Sankar N <praveensankarn@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Felix Polyudov <Felixp@ami.com> Cc: Srinivasan Mani <srinivasanm@ami.com> Cc: Sundaresan S <sundaresans@ami.com> Cc: Rabisha R <rabishar@ami.com>
* OvmfPkg: Use newly defined Unaccepted Memory TypeSachin Ganesh2024-05-085-14/+14
| | | | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg: Update Delayed Dispatch PPI as per PI 1.8 SpecSachin Ganesh2024-05-081-1/+23
| | | | | | | | | | | Added WaitOnEvent() function to EFI_DELAYTED_DISPATCH_PPI. Modified DispatchRegister() parameter list. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Use newly defined Unaccepted Memory TypeSachin Ganesh2024-05-084-69/+24
| | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Define Unaccepted Memory TypeSachin Ganesh2024-05-082-18/+7
| | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new Resource Attributes defined in PI 1.8 SpecSachin Ganesh2024-05-081-0/+2
| | | | | | | | | | | Defined Encrypted and Special Purpose resource attributes as defined in PI 1.8 Specification Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add definition for NVMe Over Fabric Device PathSachin Ganesh2024-05-081-0/+22
| | | | | | | | | | | | In accordance with UEFI 2.10 Specification: Adding definition for NVMe Over Fabric (NVMe-oF) Device Path of Messaging Sub-Type. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg/Library: Support to get processor extended infoJiaxin Wu2024-05-082-4/+4
| | | | | | | | | | | | | | Intel has some features need to use processor extended information under CPU feature InitializeFunc(), so add code to support it: This patch is to add CPU_V2_EXTENDED_TOPOLOGY to get processor extended info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Adding SpiHc DriversBrit Chesley2024-05-081-0/+2
| | | | | | | | | | | | | | Including the SpiHc drivers in MdeModulePkg.dsc Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: SpiHc: SpiHc DriversBrit Chesley2024-05-087-0/+514
| | | | | | | | | | | | | | Added SpiHc DXE and SMM drivers. This code receives bus transactions from the SpiBus layer and passes them onto the SpiHcPlatformLib Platform Initialization Spec 1.7 volume 5 section 18.1.7 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdeModulePkg:BaseSpiHcPlatformLib: Adding NULL lib instanceBrit Chesley2024-05-086-0/+344
| | | | | | | | | | | | | | | | | | Adding NULL SpiHcPlatformLib instance. This library is responsible for handling the low level details of the SPI host controller. Since this is platform specific this library will be dependent on OEM SPI implementation. The SPI host controller layer will utilize this library for SPI bus transactions. Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Adding SpiBus DriversBrit Chesley2024-05-081-0/+2
| | | | | | | | | | | | | | | | Including the SpiBus drivers in MdeModulePkg.dsc Platform Initialization spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Bus/Spi/SpiBus: Adding SpiBus DriversBrit Chesley2024-05-087-0/+1052
| | | | | | | | | | | | | | | | | Added SpiBus DXE and SMM drivers. This code translates SPI requests from the application layer into SPI Bus transactions on the SPI host controller. The code is responsible for checking if the transaction is valid, then setting up the SPI clock and chip select properly before passing the bus transaction to the host controller. Platform Initialization Spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdePkg/SpiConfiguration: Correct the definition spellingAbner Chang2024-05-081-2/+2
| | | | | | | Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove SmBases relocation logicJiaxin Wu2024-05-0811-856/+40
| | | | | | | | | | | | | | | | | | | | | | This patch is to remove legacy SmBase relocation in PiSmmCpuDxeSmm Driver. The responsibility for SmBase relocation has been transferred to the SmmRelocationInit interface, which now handles the following tasks: 1. Relocates the SmBase for each processor. 2. Generates the gSmmBaseHobGuid HOB. As a result of this change, the PiSmmCpuDxeSmm driver's role in SMM environment setup is simplified to: 1. Utilize the gSmmBaseHobGuid to determine the SmBase. 2. Perform the ExecuteFirstSmiInit() to do early SMM initialization. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiPayloadPkg/UefiPayloadPkg.dsc: Include SmmRelocationLibJiaxin Wu2024-05-081-0/+2
| | | | | | | | | | | | | This patch just includes SmmRelocationLib in UefiPayloadPkg. Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* OvmfPkg/PlatformPei: Relocate SmBases in PEI phaseJiaxin Wu2024-05-084-1/+92
| | | | | | | | | | | | | | This patch is to consume SmmRelocationInit for SmBase Relocation. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/SmmCpuFeaturesLib: Check Smbase Relocation is done or notJiaxin Wu2024-05-081-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | Based on gSmmBaseHobGuid: If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. So, this patch check smbase relocation is done or not in SmmCpuFeaturesInitializeProcessor(). With SmmRelocationLib, gSmmBaseHobGuid will be always created. Here this patch just makes the function/logic correct. The SMM Relocation logic can be totally cleaned from the SmmCpuFeaturesLib. But it will happen in the future patch set, this patch does not target to the cleanup work. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg: Refine SmmAccess implementationJiaxin Wu2024-05-088-151/+87
| | | | | | | | | | | | | | | | | | | | This patch refines the SmmAccess implementation: 1. SmramMap will be retrieved from the gEfiSmmSmramMemoryGuid instead of original from the TSEG Memory Base register. 2. Remove the gEfiAcpiVariableGuid creation, thus the DESCRIPTOR_INDEX definition can be also cleaned. 3. The gEfiAcpiVariableGuid HOB is moved to the OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/PlatformInitLib: Create gEfiSmmSmramMemoryGuidJiaxin Wu2024-05-082-40/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the PiSmmCpuDxeSmm driver, SMRAM allocation for SMI handlers and processor Save State areas was traditionally performed using the Smst->AllocatePages() function during the DXE phase. The introduction of SmmRelocationLib changes this process by moving the allocation to the PEI phase, where Smst->AllocatePages() is not accessible. Instead, the allocation is now handled by partitioning the SMRAM based on the information provided by a GUID HOB (identified by gEfiSmmSMramMemoryGuid). This patch is to ensure that OVMF produces the gEfiSmmSMramMemoryGuid HOB, allowing SmmRelocationLib to reserve the necessary memory for SMBASE relocation. More info for the change: 1. The EFI_SMM_SMRAM_MEMORY_GUID HOB, as defined in the PI specification, vol.3, section 5, which is used to describe the SMRAM memory regions supported by the platform. This HOB should be produced during the memory detection phase to align with the PI spec. 2. In addition to the memory reserved for ACPI S3 resume, an increasing number of features require reserving SMRAM for specific purposes, such as SmmRelocation. Other advanced features in Intel platforms also necessitate this. The implementation of these features varies and is entirely dependent on the platform. This is why an increasing number of platforms are adopting the EFI_SMM_SMRAM_MEMORY_GUID HOB for SMRAM description. 3. It is crucial that the SMRAM information remains consistent when retrieved from the platform, whether through the SMM ACCESS PPI/Protocol or the EFI_SMM_SMRAM_MEMORY_GUID HOB. Inconsistencies can lead to unexpected issues, most commonly memory region conflicts. 4. The SMM ACCESS PPI/Protocol can be naturally implemented for general use. The common approach is to utilize the EFI_SMM_SMRAM_MEMORY_GUID HOB. For reference, see the existing implementation in the EDK2 repository at edk2/UefiPayloadPkg/SmmAccessDxe/SmmAccessDxe.inf and edk2-platforms/Silicon/Intel/IntelSiliconPkg/Feature/ SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf. Next patch will refine the OVMF SMM Access to consume the EFI_SMM_SMRAM_MEMORY_GUID HOB. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/SmmRelocationLib: Add library instance for OVMFJiaxin Wu2024-05-0814-0/+1299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are below 2 differences between AMD & OVMF according existing implementation: 1.The mode of the CPU check is different between the AMD & OVMF. OVMF: CpuSaveState->x86.SMMRevId & 0Xffff AMD: LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA 2.Existing SmBase configuration is different between the AMD & OVMF. OVMF: if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { CpuSaveState->x86.SMBASE = mSmBaseForAllCpus[CpuIndex]; } else { CpuSaveState->x64.SMBASE = mSmBaseForAllCpus[CpuIndex]; } AMD: AmdCpuState->x64.SMBASE = mSmBaseForAllCpus[CpuIndex]; This patch provides the SmmRelocationLib library instance for OVMF to handle the logic difference, and it won't change the existing implementation code logic. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add library instance for AMDJiaxin Wu2024-05-083-0/+186
| | | | | | | | | | | | | | | | | | Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary CpuIndexJiaxin Wu2024-05-085-23/+3
| | | | | | | | | | | This patch is to remove unnecessary CpuIndex. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary global variableJiaxin Wu2024-05-081-56/+32
| | | | | | | | | | | | | | This patch aims on mProcessorInfo global variable, which can be defined as local variable in SmmRelocateBases(). With this patch, no need to allocate the memory for all CPUs to store the Processor Info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Avoid unnecessary memory allocationJiaxin Wu2024-05-081-111/+90
| | | | | | | | | | | | | | | | | Since SMM relocation is performed serially for each CPU, there is no need to allocate buffers for all CPUs to store the SmBase address in mSmBase and the Rebased flag in mRebased. A defined global variable is sufficient. This patch focuses on the mSmBase and mRebased global variables to prevent unnecessary memory allocation for these variables. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Rename global variablesJiaxin Wu2024-05-084-35/+35
| | | | | | | | | | | | | This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add SmmRelocationLib library instanceJiaxin Wu2024-05-089-0/+1396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch just separates the smbase relocation logic from PiSmmCpuDxeSmm driver, and moves to the SmmRelocationInit interface. It maintains the original implementation of most functions and leaves the definitions of global variables intact. Further refinements to the code are planned for subsequent patches. Platform shall consume the interface for the smbase relocation if need SMM support. Note: Before using SmmRelocationLib, the PiSmmCpuDxeSmm driver allocates the SMRAM to be used for SMI handler and Save state area of each processor from Smst->AllocatePages(). With SmmRelocationLib, the SMRAM allocation for SMI handlers and Save state areas is moved to early PEI phase (Smst->AllocatePages() service is not available). So, the allocation is done by splitting the SMRAM out of the SMRAM regions reported from gEfiSmmSMramMemoryGuid. So, Platform must produce the gEfiSmmSMramMemoryGuid HOB for SmmRelocationLib usage. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add SmmRelocationLib classJiaxin Wu2024-05-082-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel plans to separate the smbase relocation logic from PiSmmCpuDxeSmm driver, and the related behavior will be moved to the new interface defined by the SmmRelocationLib class. The SmmRelocationLib class provides the SmmRelocationInit() interface for platform to do the smbase relocation, which shall provide below 2 functionalities: 1. Relocate smbases for each processor. 2. Create the gSmmBaseHobGuid HOB. With SmmRelocationLib, PiSmmCpuDxeSmm driver (which runs at a later phase) shall: 1. Consume the gSmmBaseHobGuid HOB for the relocated smbases for each Processor. 2. Execute the early SMM Init. This patch just provides the SmmRelocationLib class. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Handle the NULL gMpInformation2HobGuidRay Ni2024-05-072-3/+87
| | | | | | | | | | | | If gMpInformation2HobGuid HOB is NULL, then fall back to an older way of collecting CPU information from the MP services library. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* MdeModulePkg/XhciDxe: Add PCD for the delay of HCRSTXianglei Cai2024-05-074-1/+12
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4727 Recently some of XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset. PHY transition from P3 to P0 can take around 1.3ms and the xHCI reset can take around 1.5ms. Add PCD to control the delay, the default is 2 ms. Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: More Shih <more.shih@intel.com> Cc: Ian Chiu <ian.chiu@intel.com> Signed-off-by: Xianglei Cai <xianglei.cai@intel.com> Reviewed-by: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/XhciDxe: Reset endpoint while USB Transaction errorXianglei Cai2024-05-073-2/+15
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4556 Based on XHCI spec 4.8.3, software should do the reset endpoint while USB Transaction occur. Add the error code for USB Transaction error since UEFI spec don't have the related definition. Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: More Shih <more.shih@intel.com> Signed-off-by: Xianglei Cai <xianglei.cai@intel.com> Reviewed-by: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* OvmfPkg: Add sp800155Event3 supportDionna Glaze2024-05-071-5/+10
| | | | | | | | | | | | The signatures for event2 or event3 are now valid TCG SP800155 event types. Fixes uncrustify formatting. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
* SecurityPkg: Recognize sp800155Event3 eventDionna Glaze2024-05-071-5/+10
| | | | | | | | | | | The signatures for event2 or event3 are now valid TCG SP800155 event types. Fixes uncrustify formatting. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
* MdePkg: Add TcgSp800155Event3 type infoDionna Glaze2024-05-071-1/+37
| | | | | | | | | | | | | | TCG PC Client Platform Firmware Profile 1.06 revision 52 of December 2023 added a new event signature and extended information about where a reference measurement document for the firmware can be found. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* RedfishPkg: Rename x-uefi-redfish to x-UEFI-redfishNickle Wang2024-05-048-63/+63
| | | | | | | | | | | | | | Rename x-uefi-redfish to x-UEFI-redfish to match the format of UEFI configuration namespace prefix. RFC: https://edk2.groups.io/g/rfc/message/849 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Co-authored-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* IntelFsp2Pkg/PatchFv.py: FIX for GCC 32BIT build errorDuggapu Chinni B2024-05-031-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4762 Map file generating 8 byte address offset is not matched with the pattern defined in patchFv tool resulting build error. Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com>
* OvmfPkg/CcExitLib: Drop special handling for Encrypted MMIO to APICMichael Roth2024-05-021-11/+1
| | | | | | | | | | | | | | | | | | | The current #VC handler guards against MMIO to addresses that are mapped with the encryption bit set, but has an special exception for MMIO accesses to the APIC base address so allow for early access during SEC. Now that the SEC page table has the encryption bit cleared for the APIC base address range, there is no longer any need for this special handling. Go ahead and remove it. Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg: Don't make APIC MMIO accesses with encryption bit setMichael Roth2024-05-0210-3/+97
| | | | | | | | | | | | | | | | | | | | | | | | | For the most part, OVMF will clear the encryption bit for MMIO regions, but there is currently one known exception during SEC when the APIC base address is accessed via MMIO with the encryption bit set for SEV-ES/SEV-SNP guests. In the case of SEV-SNP, this requires special handling on the hypervisor side which may not be available in the future[1], so make the necessary changes in the SEC-configured page table to clear the encryption bit for 4K region containing the APIC base address. [1] https://lore.kernel.org/lkml/20240208002420.34mvemnzrwwsaesw@amd.com/#t Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jianyong Wu <jianyong.wu@arm.com> Cc: Anatol Belski <anbelski@linux.microsoft.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/ResetVector: Clear SEV encryption bit for non-leaf PTEsMichael Roth2024-05-022-11/+14
| | | | | | | | | | | | | | | | | | Future changes will make use of CpuPageTableLib to handle splitting page table mappings during SEC phase. While it's not strictly required by hardware, CpuPageTableLib relies on non-leaf PTEs never having the encryption bit set, so go ahead change the page table setup code to satisfy this expectation. Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
* Maintainers.txt: Update my email addressAnthony PERARD2024-05-021-1/+1
| | | | | | Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* Maintainers.txt: Update StandaloneMmPkg and UefiCpuPkg ReviewerJiaxin Wu2024-04-301-0/+2
| | | | | | | | | | | | This is to update StandaloneMmPkg and UefiCpuPkg Reviewer. Cc: Ray Ni <ray.ni@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* OvmfPkg: Remove QemuFwCfgLibMmio.infChao Li2024-04-301-54/+0
| | | | | | | | | | | | All of platforms are switching to QemuFwCfgMmioDxeLib.inf, remove QemuFwCfgLibMmio.inf now. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* OvmfPkg/RiscVVirt: Enable QemuFwCfgMmioDxeLib.infChao Li2024-04-301-1/+1
| | | | | | | | | | | | | | | Enable QemuFwCfgMmioDxeLib.inf in RiscVVirtQemu.dsc Build-tested only (with "RiscVVirtQemu.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* ArmVirtPkg: Enable QemuFwCfgMmioDxeLib.infChao Li2024-04-302-2/+2
| | | | | | | | | | | | | | | | Enable QemuFwCfgMmioDxeLib.inf in ArmVirtQemu.dsc and ArmVirtQemuKernel.dsc. Build-tested only (with "ArmVirtQemu.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* OvmfPkg: Copy the same new INF as QemuFwCfgLibMmio.infChao Li2024-04-301-0/+54
| | | | | | | | | | | | | Copy QemuFwCfgLibMmio.inf to QemuFwCfgMmioDxeLib.inf, QemuFwCfgLibMmio.inf will be deleted when all platforms switching is completed. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4755 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 18:54:04 +0000