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* ArmVirtPkg/ArmVirtQemu: Use PEI flavor of ArmMmuLib for all PEIMsArd Biesheuvel2023-03-161-6/+4
| | | | | | | | | | | | | | | The PEI flavor of the ArmMmuLib will install a HOB that exposes its implementation of the special helper routine that is used to update live entries, so that other instantiations of ArmMmuLib can invoke it. This is needed to ensure that splitting page tables using break-before-make (BBM) does not unmap the code that is performing the split. However, the BASE variety of ArmMmuLib discovers the HOB and sets a global pointer to refer to it, which is not possible in PEIMs, and so all PEIMs must use the PEI variety of this library if one does. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Introduce region types for RO/XP WB cached memoryArd Biesheuvel2023-03-163-6/+47
| | | | | | | | | | | | | | | | To prepare for the enablement of booting EFI with the SCTLR.WXN control enabled, which makes all writeable memory regions non-executable by default, introduce a memory type that we will use to describe the flash region that carries the SEC and PEIM modules that execute in place. Even if these are implicitly read-only due to the ROM nature, they need to be mapped with read-only attributes in the page tables to be able to execute from them. Also add the XP counterpart which will be used for all normal DRAM right at the outset. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/Mmu: Remove handling of NONSECURE memory regionsArd Biesheuvel2023-03-164-76/+24
| | | | | | | | | | | | Non-secure memory is a distinction that only matters when executing code in the secure world that reasons about the secure vs non-secure address spaces. EDK2 was not designed for that, and the AArch64 version of the MMU handling library already treats them as identical, so let's just drop the ARM memory region types that mark memory as 'non-secure' explicitly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe: Implement EFI memory attributes protocolArd Biesheuvel2023-03-164-0/+326
| | | | | | | | Expose the protocol introduced in v2.10 that permits the caller to manage mapping permissions in the page tables. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Add Memory Attribute Protocol definitionArd Biesheuvel2023-03-162-0/+145
| | | | | | | | | | Add the Memory Attribute Protocol definition, which was adopted and included in version 2.10 of the UEFI specification. Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3519 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe: Expose unified region-to-EFI attribute conversionArd Biesheuvel2023-03-163-0/+69
| | | | | | | | | | In preparation for introducing an implementation of the EFI memory attributes protocol that is shared between ARM and AArch64, unify the existing code that converts a page table descriptor into a EFI_MEMORY_xx bitfield, so it can be called from the generic code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Avoid splitting block entries if possibleArd Biesheuvel2023-03-162-0/+21
| | | | | | | | | | | | | | | | | Currently, the ARM MMU page table logic will break down any block entry that overlaps with the region being mapped, even if the block entry in question is using the same attributes as the new region. This means that creating a non-executable mapping inside a region that is already mapped non-executable at a coarser granularity may trigger a call to AllocatePages (), which may recurse back into the page table code to update the attributes on the newly allocated page tables. Let's avoid this, by preserving the block entry if it already covers the region being mapped with the correct attributes. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmVirtPkg: Enable stack guardArd Biesheuvel2023-03-161-0/+2
| | | | | | | | | Enable the stack guard in ArmVirtPkg builds, so that stack overflows are caught as they occur, rather than when they happen to hit a read-only memory region. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Implement EFI_MEMORY_RP using access flagArd Biesheuvel2023-03-164-4/+144
| | | | | | | | | | | Implement support for read-protected memory by wiring it up to the access flag in the page table descriptor. The resulting mapping is implicitly non-writable and non-executable as well, but this is good enough for implementing this attribute, as we never rely on write or execute permissions without read permissions. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Clear individual permission bitsArd Biesheuvel2023-03-161-13/+81
| | | | | | | | | | | | | | | | | Currently, the MMU code that is supposed to clear the RO or XP attributes from a region just clears both unconditionally. This approximates the desired behavior to some extent, but it does mean that setting the RO bit first on a code region, and then clearing the XP bit results both RO and XP being cleared, and we end up with writable code, and avoiding that is the point of all these protections. Once we introduce RP support, this will only get worse, so let's fix this up, by reshuffling the attribute update code to take the entry mask from the caller, and use the mask to preserve other attributes when clearing RO or XP. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Isolate the access flag from AP maskArd Biesheuvel2023-03-165-40/+64
| | | | | | | | | | | Split the ARM permission fields in the short descriptors into an access flag and AP[2:1] as per the recommendation in the ARM ARM. This makes the access flag available separately, which allows us to implement EFI_MEMORY_RP memory analogous to how it will be implemented for AArch64. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe ARM: Fix page-to-section attribute conversionArd Biesheuvel2023-03-162-0/+5
| | | | | | | | | | | | | | | | The section-to-page attribute conversion takes the shareability and execute-never attributes into account, whereas the page-to-section counterpart does not. The result is that GetMemoryRegionPage () -which takes a section attribute argument (via *RegionAttributes) that is ostensibly based on the first page in the range, but differs from the actual page attributes when converted back- may return with a RegionLength of zero. This is incorrect, and confuses code that scans a region by calling GetMemoryRegion () in sequence. So fix the conversion, and ASSERT () on a non-zero region length. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Split off XN page descriptor bit from type fieldArd Biesheuvel2023-03-162-11/+9
| | | | | | | | | | | With large page support out of the picture, we can treat bits 1 and 0 of the page descriptor as individual valid and XN bits, instead of treating XN as a page type. Doing so aligns the handling of the attribute with the section descriptor layout, as well as the XN handling on AArch64, and this is beneficial for maintainability. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib ARM: Remove half baked large page supportArd Biesheuvel2023-03-165-39/+20
| | | | | | | | | | | | | | | | | | Large page support on 32-bit ARM is essentially a glorified contiguous bit where 16 consecutive entries describing a contiguous range with the same attributes are presented in a way that permits the TLB to cache its translation with a single entry. This was never wired up completely, and does not add a lot of value in EFI, where the page granularity is 4k and we expect to be able to set RO and XP permissions on individual pages. Given that large page support complicates the handling of the XN bit at the page level (which is in a different place depending on whether the page is small or large), let's just rip it out. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix InvalidateInstructionCacheRangeTuan Phan2023-03-161-1/+6
| | | | | | | | When the range instruction cache invalidating not supported, the whole instruction cache should be invalidated instead. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/PlatformCI: Add CI coverage for RiscVVirtQemuSunil V L2023-03-162-0/+46
| | | | | | | | | | | Add support for building RiscVVirtQemu platform in CI. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiPayloadPkg: Correct MAX_LOGICAL_PROCESSORS valueMarsX Lin2023-03-141-1/+1
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4372 Correct MAX_LOGICAL_PROCESSORS value to 1024 Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix S3 failure in SmmRestoreCpuWu, Jiaxin2023-03-141-13/+1
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4368 This issue is caused by the commit: ec07fd0e35d90dbcc36be300a9ceeac29c5de2ad GetFirstGuidHob() should not be used after exit boot service. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* ShellPkg/Library: Fix 32-bit truncation of pointer valuesMichael D Kinney2023-03-135-44/+12
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4366 Update C and UNI files that are incorrectly using %x or %08x instead of %p for pointer values. On 64-bit systems, this is truncating pointer values above 4GB. In reviewing ShellPkg for this issue some unused UNI strings with incorrect format specifiers were removed instead of being fixed. Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* BaseTools: Extend fields for module_report.jsonGuillermo Antonio Palomino Sosa2023-03-111-0/+4
| | | | | | | | | | | Adding following fields to module_report.json: * LibraryClass * ModuleEntryPointList * ConstructorList * DestructorList Signed-off-by: Guillermo Antonio Palomino Sosa <guillermo.a.palomino.sosa@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* BaseTools: Generate compile information in build reportPalomino Sosa, Guillermo A2023-03-112-3/+140
| | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2850 Add "-Y REPORT_INFO" option to build command to generate compile information as part of BuildReport. This option generates files to be used by external tools as IDE's to enhance functionality. Files are created inside build folder: <Build>/<BuildTarget>/<ToolChain>/CompileInfo Files created: * compile_commands.json - Compilation Database. To be used by IDE's to enable advance features * cscope.files - List of files used in compilation. Used by Cscope to parse C code and provide browse functionality. * module_report.json - Module data form buildReport in Json format. Signed-off-by: Guillermo Antonio Palomino Sosa <guillermo.a.palomino.sosa@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* DynamicTablesPkg: Add SMBIOS String table helper librarySami Mujawar2023-03-106-2/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Section 6.1.3, SMBIOS specification version 3.6.0 describes the handling of test strings in SMBIOS tables. Text strings are added at the end of the formatted portion of the SMBIOS structure and are referenced by index in the SMBIOS structure. Therefore, introduce a SmbiosStringTableLib to simplify the publishing of the string set. SmbiosStringTableLib introduces a concept of string table which records the references to the SMBIOS strings as they are added and returns an string reference which is then assigned to the string field in the formatted portion of the SMBIOS structure. Once all strings are added, the library provides an interface to get the required size for the string set. This allows sufficient memory to be allocated for the SMBIOS table. The library also provides an interface to publish the string set in accordance with the SMBIOS specification. Example: EFI_STATUS BuildSmbiosType17Table () { STRING_TABLE StrTable; UINT8 DevLocatorRef; UINT8 BankLocatorRef; SMBIOS_TABLE_TYPE17 *SmbiosRecord; CHAR8 *StringSet; ... // Initialize string table for 7 strings StringTableInitialize (&StrTable, 7); StringTableAddString (&StrTable, "SIMM 3", &DevLocatorRef); StringTableAddString (&StrTable, "Bank 0", &BankLocatorRef); ... SmbiosRecord = AllocateZeroPool ( sizeof (SMBIOS_TABLE_TYPE17) + StringTableGetStringSetSize (&StrTable) ); ... SmbiosRecord->DeviceLocator = DevLocatorRef; SmbiosRecord->BankLocator = BankLocatorRef; ... // get the string set area StringSet = (CHAR8*)(SmbiosRecord + 1); // publish the string set StringTablePublishStringSet ( &StrTable, StringSet, StringTableGetStringSetSize (&StrTable) ); // free string table StringTableFree (&StrTable); return EFI_SUCCESS; } Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Cc: Alexei Fedorov <Alexei.Fedorov@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Ashish Singhal <ashishsingha@nvidia.com> Cc: Nick Ramirez <nramirez@nvidia.com> Cc: William Watson <wwatson@nvidia.com> Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
* UefiPayloadPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-104-4/+0
| | | | | | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-1015-15/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* SourceLevelDebugPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-101-1/+0
| | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Hao A Wu <hao.a.wu@intel.com> Acked-by: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* PcAtChipsetPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-101-1/+0
| | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* OvmfPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-1016-16/+0
| | | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* IntelFsp2Pkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-108-8/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* MdePkg: Move API and implementation from UefiCpuLib to CpuLibYu Pu2023-03-108-57/+74
| | | | | | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* OvmfPkg: Add CpuLib to module INFs that depend on UefiCpuLib.Zhiguang Liu2023-03-105-0/+5
| | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build failure, add CpuLib dependency to all modules that depend on UefiCpuLib. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/MicrocodeMeasurementDxe: Fix exceptionDarbin Reyes2023-03-101-1/+1
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4360 An incorrect format specifier is being used in a DEBUG print, specifically, a variable of type EFI_STATUS was being printed with the %a format specifier (pointer to an ASCII string), thus the value of the Status variable was being treated as the address of a string, leading to a CPU exception, when encountered this bug manifests itself as a hang near "Ready to Boot Event", with the last DEBUG print being "INFO: Got MicrocodePatchHob with microcode patches starting address" followed by a CPU Exception dump. Signed-off-by: Darbin Reyes <darbin.reyes@intel.com> Reviewed-by: Jacob Narey <jacob.narey@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CryptoPkg/OpensslLib: Upgrade OpenSSL to 1.1.1tSheng Wei2023-03-106-0/+5
| | | | | | | | | | | | Upgrade openssl to 1.1.1t Pick up bugfixes from the latest openssl release. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Sheng Wei <w.sheng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Fix GCC Compiler warning.S, Ashraf Ali2023-03-101-0/+1
| | | | | | | | | | | | | | | Function definition should match with declaration. [-Wlto-type-mismatch] Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* OvmfPkg/SmbiosPlatformDxe: tweak fallback release dateGerd Hoffmann2023-03-091-1/+1
| | | | | | | | | | In case PcdFirmwareReleaseDateString is not set use a valid date as fallback. Using "unknown" makes Windows unhappy. Fixes: 4cb94f20b002 ("OvmfPkg/SmbiosPlatformDxe: use PcdFirmware*") Reported-by: ruifeng.gao@intel.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/SemihostFs: replace SetMem with ZeroMemGerd Hoffmann2023-03-091-1/+1
| | | | | | | | | | | | | SetMem arguments 2+3 are in the wrong order, resulting in the call having no effect because Length is zero. Fix this by using ZeroMem instead. Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4205 Reported-by: Jeremy Boone <jeremy.boone@nccgroup.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* UefiCpuPkg: BaseRiscV64CpuExceptionHandlerLib: clean upAndrei Warkentin2023-03-085-45/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RegisterCpuInterruptHandler did not allow setting exception handlers for anything beyond the timer IRQ. Beyond that, it didn't meet the spec around handling of inputs. RiscVSupervisorModeTrapHandler now will invoke set handlers for both exceptions and interrupts. Two arrays of handlers are maintained - one for exceptions and one for interrupts. For unhandled traps, RiscVSupervisorModeTrapHandler dumps state using the now implemented DumpCpuContext. For EFI_SYSTEM_CONTEXT_RISCV64, extend this with the trapped PC address (SEPC), just like on AArch64 (ELR). This is necessary for X86EmulatorPkg to work as it allows a trap handler to return execution to a different place. Add SSTATUS/STVAL as well, at least for debugging purposes. There is no value in hiding this. Fix nested exception handling. Handler code should not be saving SIE (the value is saved in SSTATUS.SPIE) or directly restored (that's done by SRET). Save and restore the entire SSTATUS and STVAL, too. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* UefiCpuPkg: CpuTimerDxeRiscV64: fix tick duration accountingAndrei Warkentin2023-03-081-14/+21
| | | | | | | | | | | | | | | The TimerDxe implementation doesn't account for the physical time passed due to timer handler execution or (perhaps even more importantly) time spent with interrupts masked. Other implementations (e.g. like the Arm one) do. If the timer tick is always incremented at a fixed rate, then you can slow down UEFI's perception of time by running long sections of code in a critical section. Cc: Daniel Schaefer <git@danielschaefer.me> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdeModulePkg: Dxe: add RISCV64 to mMachineTypeInfoAndrei Warkentin2023-03-081-1/+2
| | | | | | | | | | | This fixes messages like: "Image type AARCH64 can't be loaded on <Unknown> UEFI system" Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BaseCpuLib: Fix RISCV CpuSleep symbol name.Andrei Warkentin2023-03-081-2/+2
| | | | | | | | | | | CpuSleep, not _CpuSleep. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BaseLib: don't log in RISCV InternalSwitchStackAndrei Warkentin2023-03-081-8/+0
| | | | | | | | | | | | | | InternalSwitchStack may be called with a TPL high enough for a DebugLib implementation to assert. Other arch implementations don't log either. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg: BasePeCoffLib: Allow AArch64 and x64 images in ImageFormatSupportedAndrei Warkentin2023-03-081-1/+9
| | | | | | | | | | | | | ARM64 and X64 may allow such foreign images to be used when driver implementing EDKII_PECOFF_IMAGE_EMULATOR_PROTOCOL is present. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* OvmfPkg: RiscVVirt: add SATA supportAndrei Warkentin2023-03-082-0/+14
| | | | | | | | | Tested with a PCIe pass-thru'd AHCI controller. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
* SecurityPkg/RngDxe: Conditionally install EFI_RNG_PROTOCOLPierre Gondois2023-03-071-5/+14
| | | | | | | | | | | | On Arm platforms, the number of available RNG algorithms is dynamically detected and can be 0 in the absence of FEAT_RNG and firmware TRNG. In this case, the EFI_RNG_PROTOCOL should not be installed to prevent from installing an empty protocol. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> [ardb: return EFI_REQUEST_UNLOAD_IMAGE instead of an error] Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* SecurityPkg/RngDxe: Correctly update mAvailableAlgoArrayCountPierre Gondois2023-03-072-1/+9
| | | | | | | | | | | mAvailableAlgoArrayCount holds the count of available RNG algorithms. In a following patch, its value will be used to prevent the EFI_RNG_PROTOCOL to be installed if no RNG algorithm is available. Correctly set/reset the value for all implementations. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg: Calculate DisplayFamily correctlyLiu, Zhiguang2023-03-072-6/+6
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4348 Per SDM: DisplayFamily = Extended_Family_ID + Family_ID. DisplayModelID = (Extended_Model_ID << 4) + Family_ID. Correct the related code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* CryptoPkg/BaseCryptLib: avoid using SHA512()Gerd Hoffmann2023-03-071-3/+13
| | | | | | | | | In openssl 3.0 SHA512() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* CryptoPkg/BaseCryptLib: avoid using SHA384()Gerd Hoffmann2023-03-071-3/+13
| | | | | | | | | In openssl 3.0 SHA384() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* CryptoPkg/BaseCryptLib: avoid using SHA256()Gerd Hoffmann2023-03-071-3/+13
| | | | | | | | | In openssl 3.0 SHA256() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* CryptoPkg/BaseCryptLib: avoid using SHA1()Gerd Hoffmann2023-03-071-3/+13
| | | | | | | | | In openssl 3.0 SHA1() goes through the provider logic, requiring a huge amount of openssl code. The individual functions do not, so use them instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasmXie, Yuanhao2023-03-072-169/+170
| | | | | | | | | | | | Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 14:12:37 +0000