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* UefiCpuPkg/CpuPageTableLib: Reduce the number of random testsDun Tan2023-03-271-5/+5
| | | | | | | | | | | | | | Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE pagingDun Tan2023-03-273-6/+11
| | | | | | | | | | | Add RandomTest for PAE paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable PAE pagingDun Tan2023-03-273-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Combine branch for non-present and leaf ParentEntryDun Tan2023-03-271-53/+32
| | | | | | | | | | | | | Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for page table creationDun Tan2023-03-271-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Modify UnitTest code since tested API is changedZhiguang Liu2023-03-273-59/+67
| | | | | | | | | | | | Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.infZhiguang Liu2023-03-273-89/+90
| | | | | | | | | | | | | | | | | | | The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModifiedDun Tan2023-03-271-12/+33
| | | | | | | | | | | | | | Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.Dun Tan2023-03-275-46/+88
| | | | | | | | | | | | | Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random testDun Tan2023-03-271-4/+4
| | | | | | | | | | | | | | Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/AttrDun Tan2023-03-272-26/+133
| | | | | | | | | | | | | | | | | | | | | Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-present, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointerDun Tan2023-03-271-8/+10
| | | | | | | | | | | Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex] in SingleMapEntryTest () of RandomTest. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTestDun Tan2023-03-271-22/+21
| | | | | | | | | | | | | | Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and AttrDun Tan2023-03-271-2/+127
| | | | | | | | | | | | | | | | | | | | Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Add check for Mask and AttrDun Tan2023-03-272-1/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Add code to initialize MapMaskDun Tan2023-03-271-4/+1
| | | | | | | | | | | | | In function CreatePageTable(), add code to initialize MapMask to MAX_UINT64. When creating new page table or map non-present range to present, all attributes should be provided. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entryDun Tan2023-03-271-8/+11
| | | | | | | | | | | | | | | | | | When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leafDun Tan2023-03-271-1/+2
| | | | | | | | | | | | | Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issueDun Tan2023-03-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginningDun Tan2023-03-271-9/+12
| | | | | | | | | | | | Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for input LengthDun Tan2023-03-272-3/+7
| | | | | | | | | | | | Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' conditionDun Tan2023-03-271-10/+1
| | | | | | | | | | | | | | Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present == 0) is always FALSE. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* PcAtChipsetPkg: Add PCD for RTC default yearMichael D Kinney2023-03-274-2/+13
| | | | | | | | | | | | | Add PcdRtcDefaultYear to specify the default year to use when the RTC is in an invalid state. Make sure PcdRtcDefaultYear is >= PcdMinimalValidYear and <= PcdMaximalValidYear. Set the default value for this PCD to PcdMinimalValidYear to preserve the existing behavior. A platform DSC file can override this default value setting. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Solve that stack top address is not mapped in pagetableXie, Yuanhao2023-03-271-0/+1
| | | | | | | | | | | | | For the case CPU logic index is 0, RSP points to the very top of all AP stacks. That address is not mapped in page table. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiPayloadPkg: Add gUefiAcpiBoardInfoGuid supportGua Guo2023-03-271-3/+6
| | | | | | | | | | | | | if system both exist gUefiAcpiBoardInfoGuid and rsdp, we may need to use gUefiAcpiBoardInfoGuid as final config to have backward support. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* MdePkg/Include: Add IPMI KCS definitionsAbner Chang2023-03-262-0/+82
| | | | | | | | | | | | | | | | | | | | BZ #4354 This change adds definitions for IPMI KCS. Spec ref: https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
* MdePkg/Include: Add DMTF MCTP definitionsAbner Chang2023-03-261-0/+139
| | | | | | | | | | | | | | | | | | | | BZ #4355 This change adds definitions for DMTF MCTP base specification. Spec ref: https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Acked-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include/Ppi: Remove Itanium leftover data structurePaweł Poławski2023-03-261-46/+5
| | | | | | | | | | | | | | | | | | | | | | | | Itanium support has been removed from EDK2 around 2019. ITANIUM_HANDOFF_STATUS data structure looks to be some leftover from that process. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1560 GitHub: https://github.com/tianocore/edk2/commit/4e1daa60f5372c22a11503961061ffa569eaf873 There is also positive side effect of this data structure removal. Due to HOB allocation type used in PEI stage there is a limit how much data about virtual CPU can be hold. This limit result in only 1024 vCPU can be used by VM. With Itanium related data structure removed more allocated space can be used for vCPU data and with current allocation limit will change from 1024 to around 8k vCPUs. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paweł Poławski <ppolawsk@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* IntelFsp2Pkg: Fix NASM X64 build warnings.Chasel Chiu2023-03-242-11/+9
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* BaseTools: Replace duplicate __PcdSet prototype with __PcdGetRebecca Cran2023-03-241-7/+6
| | | | | | | | Replace the duplicate __PcdSet prototype in PcdValueCommon.h with the prototype for __PcdGet. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: Source/C/Common: Fix doc block locations and convert to DoxygenRebecca Cran2023-03-2429-4065/+2072
| | | | | | | | | | Move the documentation blocks from between the parameter list and function body to above the function. Convert all the documentation blocks to Doxygen format. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* OvmfPkg/PlatformBootManagerLib: use utf8 for the serial console.Gerd Hoffmann2023-03-232-5/+5
| | | | | | | | Time to leave behind relics from the last century and arrive in the modern world. Drop PC-ANSI Terminal Type for the serial console, use UTF-8 instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: fix error handlingGerd Hoffmann2023-03-221-0/+6
| | | | | | | | ASSERT() is not proper handling of allocation failures, it gets compiled out on RELEASE builds. Print a message and enter dead loop instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: drop support for obsolete processorsGerd Hoffmann2023-03-221-14/+4
| | | | | | | | | It's highly unlikely the code ever runs on processors which are almost 30 years old. Drop the code handling them. Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4345 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* SecurityPkg/DxeImageVerificationLib: Check result of GetEfiGlobalVariable2Gerd Hoffmann2023-03-211-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Call gRT->GetVariable() directly to read the SecureBoot variable. It is one byte in size so we can easily place it on the stack instead of having GetEfiGlobalVariable2() allocate it for us, which avoids a few possible error cases. Skip secure boot checks if (and only if): (a) the SecureBoot variable is not present (EFI_NOT_FOUND) according to the return value, or (b) the SecureBoot variable was read successfully and is set to SECURE_BOOT_MODE_DISABLE. Previously the code skipped the secure boot checks on *any* gRT->GetVariable() error (GetEfiGlobalVariable2 sets the variable value to NULL in that case) and also on memory allocation failures. Fixes: CVE-2019-14560 Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=2167 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Suggested-by: Marvin Häuser <mhaeuser@posteo.de> Reviewed-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* RedfishPkg: Update Readme.mdAbner Chang2023-03-204-8/+1001
| | | | | | | | | | Update readme.md and add figures to delineate the relationship of edk2 Redfish, USB NIC and IPMI. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
* RedfishPkg: Update Redfish DSCAbner Chang2023-03-201-0/+7
| | | | | | | | | | Update Redfish DSC for PlatformHostInterfaceBmcUsbNicLib. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
* RedfishPkg/Library: Redfish BMC USBNIC Host InterfaceAbner Chang2023-03-205-1/+1435
| | | | | | | | | | BMC exposed USB NIC platform Redfish Host Interface library implementation. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Nickle Wang <nicklew@nvidia.com>
* MdePkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-03-177-33/+33
| | | | | | | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout MdePkg. Visual Studio versions before VS 2015 don't support __func__ and so will fail to compile. A workaround is to define __func__ as __FUNCTION__ : #define __func__ __FUNCTION__ Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Update Base.h to be compliant with C11Rebecca Cran2023-03-171-6/+6
| | | | | | | | | | | | | | | | With the introduction of the use of _Static_assert, edk2 requires a C11 compatible compiler. Update Include/Base.h to be compliant with C11. As of C11, the maximum type of an enum is type `int`. Since the UEFI Specification 2.3.1 Errata C allows either `int` or `unsigned int`, fix the 32-bit enum check to use a signed int. Since the UEFI 2.3 Specification only allowed signed int, update the comment to reference 2.3.1 Errata C where the change was made to allow unsigned int. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* CryptoPkg/Library: add -Wno-unused-but-set-variable for opensslGang Chen2023-03-175-0/+10
| | | | | | | | | | The GCC warning fix is not in 1.1.1x. Ignore the warning type -Wno-unused-but-set-variable with GCC compiler in the build option. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* MdeModulePkg/BmBoot: Skip removable media if it is not presentMatt DeVillier2023-03-171-0/+9
| | | | | | | | | | | | | Only enumerate devices that have media present. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* ArmVirtPkg/ArmVirtQemu: Use PEI flavor of ArmMmuLib for all PEIMsArd Biesheuvel2023-03-161-6/+4
| | | | | | | | | | | | | | | The PEI flavor of the ArmMmuLib will install a HOB that exposes its implementation of the special helper routine that is used to update live entries, so that other instantiations of ArmMmuLib can invoke it. This is needed to ensure that splitting page tables using break-before-make (BBM) does not unmap the code that is performing the split. However, the BASE variety of ArmMmuLib discovers the HOB and sets a global pointer to refer to it, which is not possible in PEIMs, and so all PEIMs must use the PEI variety of this library if one does. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Introduce region types for RO/XP WB cached memoryArd Biesheuvel2023-03-163-6/+47
| | | | | | | | | | | | | | | | To prepare for the enablement of booting EFI with the SCTLR.WXN control enabled, which makes all writeable memory regions non-executable by default, introduce a memory type that we will use to describe the flash region that carries the SEC and PEIM modules that execute in place. Even if these are implicitly read-only due to the ROM nature, they need to be mapped with read-only attributes in the page tables to be able to execute from them. Also add the XP counterpart which will be used for all normal DRAM right at the outset. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/Mmu: Remove handling of NONSECURE memory regionsArd Biesheuvel2023-03-164-76/+24
| | | | | | | | | | | | Non-secure memory is a distinction that only matters when executing code in the secure world that reasons about the secure vs non-secure address spaces. EDK2 was not designed for that, and the AArch64 version of the MMU handling library already treats them as identical, so let's just drop the ARM memory region types that mark memory as 'non-secure' explicitly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe: Implement EFI memory attributes protocolArd Biesheuvel2023-03-164-0/+326
| | | | | | | | Expose the protocol introduced in v2.10 that permits the caller to manage mapping permissions in the page tables. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Add Memory Attribute Protocol definitionArd Biesheuvel2023-03-162-0/+145
| | | | | | | | | | Add the Memory Attribute Protocol definition, which was adopted and included in version 2.10 of the UEFI specification. Link: https://bugzilla.tianocore.org/show_bug.cgi?id=3519 Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/CpuDxe: Expose unified region-to-EFI attribute conversionArd Biesheuvel2023-03-163-0/+69
| | | | | | | | | | In preparation for introducing an implementation of the EFI memory attributes protocol that is shared between ARM and AArch64, unify the existing code that converts a page table descriptor into a EFI_MEMORY_xx bitfield, so it can be called from the generic code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg/ArmMmuLib: Avoid splitting block entries if possibleArd Biesheuvel2023-03-162-0/+21
| | | | | | | | | | | | | | | | | Currently, the ARM MMU page table logic will break down any block entry that overlaps with the region being mapped, even if the block entry in question is using the same attributes as the new region. This means that creating a non-executable mapping inside a region that is already mapped non-executable at a coarser granularity may trigger a call to AllocatePages (), which may recurse back into the page table code to update the attributes on the newly allocated page tables. Let's avoid this, by preserving the block entry if it already covers the region being mapped with the correct attributes. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmVirtPkg: Enable stack guardArd Biesheuvel2023-03-161-0/+2
| | | | | | | | | Enable the stack guard in ArmVirtPkg builds, so that stack overflows are caught as they occur, rather than when they happen to hit a read-only memory region. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 08:31:20 +0000