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* MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE registerLuo, Heng2022-06-221-2/+8
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni <ray.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiPayloadPkg: UniversalPayloadBuild.py to support --pcd featureGua Guo2022-06-211-0/+8
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3955 Currently, UPL freezed all PCD and only known UPL hob can hook DXE Drivers behavior, add optional feature on UniversalPayloadBuild.py to have another way to hook PCD value. Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: : Ray Ni <ray.ni@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* UefiPayloadPkg: Always split page table entry to 4K if it covers stack.Liu, Zhiguang2022-06-201-10/+2
| | | | | | | | | | | | | | | | | | | | | | | We observed page fault in the following situation: 1.PayloadEntry uses 2M entry in page table to cover DXE stack range. 2.In DXE phase, image protection code needs to mark some sub-range in this 2M entry as readonly. So the the 2M page table entry is split to 512 4K entries, and some of the entries are marked as readonly. (the entries covering stack still remain R/W) 3.Page fault exception happens when trying to access stack. Always split the page table entry to 4K if it covers stack to avoid this issue. More discussion about this issue can be seen at below link https://edk2.groups.io/g/devel/topic/91446026 Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Increase the PcdMaximumUnicodeStringLengthXie, Yuanhao2022-06-171-0/+1
| | | | | | | | | | | | | | The maximum Unicode string could be as large as 1800000 in certain platforms when HII code builds the configuration strings. This causes assertion in PrintLib. The patch increases the PcdMaximumUnicodeStringLength to 1800000 to avoid the assertion. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com>
* BaseTools: output the intermediate library instance when error occursNi, Ray2022-06-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a module "Module" depends on a library instance "Lib1" which depends on "Lib2" which depends on "Lib3" ... depends on "LibN", but "LibN" doesn't support the type (e.g.: SEC) of the "Module", the following error messages are printed by build tool: <DSC path>(...): error 1001: Module by library instance [<LibN path>] consumed by [<Module path>] But it's unclear to user how LibN is consumed by the Module. With the patch, following errors are printed: <DSC path>(...): error 1001: Module by library instance [<LibN path>] consumed by library instance [<Lib N-1 path>] which is consumed by module[<Module path>] It doesn't print all the intermediate library instances between the Module and LibN but at least the path of Lib N-1 can help users to help how to fix the build errors. I hope this patch can be a trigger point that a better solution could be developed by tool experts to print all the library instances between the Module and LibN. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.fen@intel.com>
* SecurityPkg/HashLibTdx: Return EFI_UNSUPPORTED if it is not Tdx guestMin M Xu2022-06-161-1/+7
| | | | | | | | | | | HashLibTdx is designed for the Tdx guest. So if is not a Tdx guest, return EFI_UNSUPPORTED in RegisterHashInterfaceLib. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Use PcdOvmfWorkAreaBase instead of PcdSevEsWorkAreaBaseMin M Xu2022-06-162-3/+3
| | | | | | | | | | | | | It is an typo error that HobList pointer should be stored at PcdOvmfWorkAreaBase, not PcdSevEsWorkAreaBase. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* DxeMain: Fix the bug that StackGuard is not enabledRay Ni2022-06-141-0/+8
| | | | | | | | | | | | Commit e7abb94d1 removed InitializeCpuExceptionHandlersEx and updated DxeMain to call InitializeCpuExceptionHandlers for exception setup. But the old behavior that calls *Ex() sets up the stack guard as well. To match the old behavior, the patch calls InitializeSeparateExceptionStacks. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn>
* ArmPkg/ArmExceptionLib: Follow new CpuExceptionHandlerLib APIsRay Ni2022-06-141-47/+11
| | | | | | | | | | | | | | | | | CpuExceptionHandlerLib has been refactored with following changes: 1. Removed InitializeCpuInterruptHandlers in 2a09527ebcb459b40 2. Removed InitializeCpuExceptionHandlersEx and added InitializeSeparateExceptionStacks in e7abb94d1fb8a0e7 The patch updates ARM version of CpuExceptionHandlerLib to follow the API changes. The functionality to ARM platforms should be none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: Add CRC16-ANSI and CRC32c implementationsPedro Falcato2022-06-132-1/+178
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3871 Add the CRC16-ANSI and CRC32C implementations previously found at Features/Ext4Pkg/Ext4Dxe/Crc{16,32c}.c to BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove "assert" from SmmCpuRendevousLibNull.cZhihao Li2022-06-131-1/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3931 Some drivers will break down when they use SmmWaitForAllProcessor() which from SmmCpuRendezvousLibNull.c. Removing the code "ASSERT(False)" will make consumer work normally if they keep default setting for sync mode. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhihao Li <zhihao.li@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* Revert "OvmfPkg/Sec: fix stack switch"Gerd Hoffmann2022-06-102-7/+3
| | | | | | | | | This reverts commit ff36b2550f94dc5fac838cf298ae5a23cfddf204. Has no effect because GCC_IA32_CC_FLAGS and GCC_X64_CC_FLAGS are unused. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitializeRay Ni2022-06-101-24/+29
| | | | | | | | | | | | | | | | | The AP vector consists of 2 parts: 1. the initial 16-bit code that should be under 1MB and page aligned. 2. the 32-bit/64-bit code that can be anywhere in the memory with any alignment. The need of part #2 is because the memory under 1MB is temporary "stolen" for use and will "give" back after all AP wake up. The range of memory is not marked as code page in page table. CPU may trigger exception as soon as NX is enabled. The part #2 memory allocation can be done in the MpInitLibInitialize. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Only allocate below 1MB memory for 16bit codeRay Ni2022-06-103-56/+46
| | | | | | | | | | | | | | | | | | | Today's implementation allocates below 1MB memory for the 16bit, 32bit and 64bit code. But it's not necessary since now the 32bit and 64bit code run at high memory no matter in PEI and DXE phase. The patch simplifies the logic to remove the code that handles the case when WakeupBufferHigh is 0. It also reduce the memory foot print under 1MB by allocating memory for 16bit code only. MP_CPU_EXCHANGE_INFO is still under 1MB which is immediate after the 16bit code. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Put SEV logic in separate fileRay Ni2022-06-106-172/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | The patch does several simplifications: 1. Treat SwitchToRealProc as part of RendezvousFunnelProc. So the common logic in MpLib.c doesn't need to be aware of SwitchToRealProc. As a result, SwitchToRealSize/Offset are removed from MP_ASSEMBLY_ADDRESS_MAP. 2. Move SwitchToRealProc to AmdSev.nasm. All other assembly code in AmdSev.nasm is called through OneTimeCall. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* MpInitLib: remove unneeded global ASM_PFXRay Ni2022-06-102-15/+3
| | | | | | | | | global in NASM file is used for symbols that are referenced in C files. Remove unneeded global keyword in NASM file. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Allocate code buffer for PEI phaseRay Ni2022-06-104-8/+13
| | | | | | | | | | Today's implementation assumes PEI phase runs at 32bit so the execution-disable feature is not applicable. It's not always TRUE. The patch allocates 32bit&64bit code buffer for PEI phase as well. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuException: Add InitializeSeparateExceptionStacksRay Ni2022-06-109-184/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today InitializeCpuExceptionHandlersEx is called from three modules: 1. DxeCore (links to DxeCpuExceptionHandlerLib) DxeCore expects it initializes the IDT entries as well as assigning separate stacks for #DF and #PF. 2. CpuMpPei (links to PeiCpuExceptionHandlerLib) and CpuDxe (links to DxeCpuExceptionHandlerLib) It's called for each thread for only assigning separate stacks for #DF and #PF. The IDT entries initialization is skipped because caller sets InitData->X64.InitDefaultHandlers to FALSE. Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib also implement such API and the behavior of the API is simply to initialize IDT entries only. Because it mixes the IDT entries initialization and separate stacks assignment for certain exception handlers together, in order to know whether the function call only initializes IDT entries, or assigns stacks, we need to check: 1. value of InitData->X64.InitDefaultHandlers 2. library instance This patch cleans up the code to separate the stack assignment to a new API: InitializeSeparateExceptionStacks(). Only when caller calls the new API, the separate stacks are assigned. With this change, the SecPei and Smm instance can return unsupported which gives caller a very clear status. The old API InitializeCpuExceptionHandlersEx() is removed in this patch. Because no platform module is consuming the old API, the impact is none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
* CpuException: Remove InitializeCpuInterruptHandlersRay Ni2022-06-108-262/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | InitializeCpuExceptionHandlers() expects caller allocates IDT while InitializeCpuInterruptHandlers() allocates 256 IDT entries itself. InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated by caller. If caller allocates 10 entries, the API just fills 10 IDT entries. The inconsistency between the two APIs makes code hard to unerstand and hard to share. Because there is only one caller (CpuDxe) for InitializeCpuInterruptHandler(), this patch updates CpuDxe driver to allocates 256 IDT entries then call InitializeCpuExceptionHandlers(). This is also a backward compatible change. With this change, InitializeCpuInterruptHandlers() is removed completely. And InitializeCpuExceptionHandlers() fills max 32 entries for PEI and SMM instance, max 256 entries for DXE instance. Such behavior matches to the original one. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Avoid allocating page but using global variablesRay Ni2022-06-101-19/+5
| | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Init global variables in-placeRay Ni2022-06-102-13/+12
| | | | | | | | | Additionally removed two useless global variables: "SPIN_LOCK mDisplayMessageSpinLock" from SMM instance. "UINTN mEnabledInterruptNum" from DXE instance. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Avoid allocating code pages for DXE instanceRay Ni2022-06-104-28/+9
| | | | | | | | | | | | | | | | | | | | | | | | Today the DXE instance allocates code page and then copies the IDT vectors to the allocated code page. Then it fixes up the vector number in the IDT vector. But if we update the NASM file to generate 256 IDT vectors, there is no need to do the copy and fix-up. A side effect is 4096 bytes (HOOKAFTER_STUB_SIZE * 256) is used for 256 IDT vectors while 32 IDT vectors only require 512 bytes without this change, in following library instances: 1. 32bit SecPeiCpuExceptionHandlerLib and PeiCpuExceptionHandlerLib 2. 64bit PeiCpuExceptionHandlerLib But considering the code logic simplification, 3.5K extra space is not a big deal. If 3.5K is too much, we can enhance the code further to generate 32 vectors for above mentioned library instances. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Acked-by: Eric Dong <eric.dong@intel.com>
* OvmfPkg/Sec: fix stack switchGerd Hoffmann2022-06-082-3/+7
| | | | | | | | | | | | | | | | | | | | The ebp/rbp register can either be used for the frame pointer or as general purpose register. With gcc (and clang) this depends on the -f(no-)omit-frame-pointer switch. This patch updates tools_def.template to explicitly set the compiler option and also add a define to allow conditionally compile code. The new define is used to fix stack switching in TemporaryRamMigration. The ebp/rbp must not be touched when the compiler can use it as general purpose register. With version 12 gcc starts actually using the register, so changing it leads to firmware crashes in some configurations. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3934 Reported-by: Jiri Slaby <jirislaby@kernel.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Delete SecMeasurementLibTdxMin M Xu2022-06-074-420/+0
| | | | | | | | | | The feature of SecMeasurementLibTdx is replaced by SecTpmMeasurementLibTdx (which is in SecurityPkg). So SecMeasurementLibTdx is deleted. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Implement MeasureHobList/MeasureFvImageMin M Xu2022-06-075-3/+224
| | | | | | | | | | | | | | | | | | | | | MeasureHobList and MeasureFvImage once were implemented in SecMeasurementTdxLib. The intention of this patch-set is to refactor SecMeasurementTdxLib to be an instance of TpmMeasurementLib. So these 2 functions (MeasureHobList/MeasureFvImage) are moved to PeilessStartupLib. This is because: 1. RTMR based trusted boot is implemented in Config-B (See below link) 2. PeilessStartupLib is designed for PEI-less boot and it is the right place to do the measurement for Hoblist and Config-FV. Config-B: https://edk2.groups.io/g/devel/message/76367 Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* Security: Add SecTpmMeasurementLibTdxMin M Xu2022-06-073-0/+212
| | | | | | | | | | | | | | | | SecTpmMeasurementLitTdx is an instance of TpmMeasurementLib. It is designed to used in a Td guest. This lib measures and logs data, and extendx the measurement result into a specific RTMR. SecTpmMeasurementLibTdx is a refactored lib of OvmfPkg/Library/SecMeasurementLibTdx and it just copies GetMappedRtmrIndex/TdxMeasureAndLogData from that lib. At the end of this patch-set SecMeasurementLibTdx will be deleted. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package pathKun Qin2022-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942 `IgnoreFiles` tag is specified in the CI YAML files in each individual packages. The current logic for UncrustifyCheck script bases specified file paths from workspace, which requires the package name to be included in each entry. This change updates the ignore checking logic to be based on current package path in order to reduce redundancy. It also keeps the consistency of `IgnoreFiles` field other pytools such as SpellCheck and EccCheck. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* BaseTools: Fix dependency issue in PcdValueInitJake Garver2022-06-061-1/+2
| | | | | | | | | The generated Makefile was missing a dependency. This resulted in a build-time race condition if the recursive make is multi-threaded and shares job control. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* OvmfPkg/IntelTdx: Enable RTMR based measurement and measure bootMin Xu2022-06-032-1/+16
| | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 Enable RTMR based measurement and measure boot for Td guest. Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ken Lu <ken.lu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/IntelTdx: Add TdTcg2DxeMin Xu2022-06-033-0/+2997
| | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 TdTcg2Dxe mimics the Security/Tcg/Tcg2Dxe. It does below tasks: - Set up and install CC_EVENTLOG ACPI table - Parse the GUIDed HOB (gCcEventEntryHobGuid) and create CC event log - Measure handoff tables, Boot##### variables etc - Measure Exit Boot Service failed - Install CcMeasurement Protocol Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ken Lu <ken.lu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* MdePkg: Define CC Measure EventLog ACPI TableMin Xu2022-06-031-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 TDVF set up an ACPI table (EFI_CC_EVENTLOG_ACPI_TABLE) to pass the event-log information. The event log created by the TD owner contains the hashes to reconstruct the MRTD and RTMR registers. Please refer to Sec 4.3.3 in blow link: https://www.intel.com/content/dam/develop/external/us/en/documents/ intel-tdx-guest-hypervisor-communication-interface-1.0-344426-002.pdf Please be noted, the definition of EFI_CC_EVENTLOG_ACPI_TABLE is a little different from the above document. This difference is based on below discussion: - https://edk2.groups.io/g/devel/message/87396 - https://edk2.groups.io/g/devel/message/87402 This change will be reflected in the next version of the above document. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ken Lu <ken.lu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg: Add PCDs for LAML/LASA field in CC EVENTLOG ACPI tableMin Xu2022-06-031-0/+6
| | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 Add PCDs to records LAML/LASA field in CC EVENTLOG ACPI table. Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ken Lu <ken.lu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/IntelTdx: Measure Td HobList and Configuration FVMin Xu2022-06-035-2/+221
| | | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 TdHobList and Configuration FV are external data provided by Host VMM. These are not trusted in Td guest. So they should be validated , measured and extended to Td RTMR registers. In the meantime 2 EFI_CC_EVENT_HOB are created. These 2 GUIDed HOBs carry the hash value of TdHobList and Configuration FV. In DXE phase EFI_CC_EVENT can be created based on these 2 GUIDed HOBs. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg: Introduce SecMeasurementLibMin Xu2022-06-034-0/+420
| | | | | | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 SecMeasurementLib is designed to do the measurement in SEC phase. In current stage there are 2 functions introduced: - MeasureHobList: Measure the Hoblist passed from the VMM. - MeasureFvImage: Measure the FV image. SecMeasurementLibTdx is the TDX version of the library. Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ken Lu <ken.lu@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* SecurityPkg: Add definition of EFI_CC_EVENT_HOB_GUIDMin Xu2022-06-032-0/+26
| | | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 EFI_CC_EVENT_HOB_GUID is the global ID of a GUIDed HOB used to pass TDX_DIGEST_VALUE from SEC to a DXE Driver ( This DXE driver will be introduced in the following commit in this patch-sets ). In that DXE driver this GUIDed HOB will be parsed and the TDX_DIGEST_VALUE then will be extracted. After that a EFI_CC_EVENT will be created based on it. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* CryptoPkg: Add SecCryptLibMin Xu2022-06-038-0/+1023
| | | | | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 This is the Cryptographic library instance for SEC. The motivation of this library is to support SHA384 in SEC phase for Td guest. So only Hash/CryptSha512.c is included which supports SHA384 and SHA512. Other cryptographics are added with the null version, such as CryptMd5Null.c. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* Security: Add HashLibTdxMin Xu2022-06-033-0/+254
| | | | | | | | | | | | | | RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3853 This library provides hash service by registered hash handler in Td guest. Currently only SHA384 is supported. After that the hash value is extended to Td RTMR registers which is similar to TPM PCRs. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg: Don't access A20 gate register on Cloud HypervisorSebastien Boeuf2022-06-031-1/+3
| | | | | | | | | Since Cloud Hypervisor doesn't emulate an A20 gate register on I/O port 0x92, it's better to avoid accessing it when the platform is identified as Cloud Hypervisor. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementationSebastien Boeuf2022-06-031-2/+2
| | | | | | | | | | Since Cloud Hypervisor doesn't support the fw_cfg mechanism, it's more appropriate to rely on QemuFwCfgLibNull implementation of QemuFwCfgLib since it provides a null implementation that will not issue any PIO accesses to ports 0x510 and 0x511. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Check for QemuFwCfg availability before accessing itSebastien Boeuf2022-06-032-6/+11
| | | | | | | | | There are few places in the codebase assuming QemuFwCfg will be present and supported, which can cause some issues when trying to rely on the QemuFwCfgLibNull implementation of QemuFwCfgLib. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: CloudHv: Fix FW_BASE_ADDRESSSebastien Boeuf2022-06-032-1/+66
| | | | | | | | | | | | | | | | The FW_BASE_ADDRESS value provided by OvmfPkgDefines.fdf.inc is incorrect for the CloudHv target. We know the generated firmware contains a PVH ELF header, meaning it will be loaded according to the address provided through this header. And since we know this address isn't going to change as it's part of CloudHvElfHeader.fdf.inc, we can hardcode it through a new include file CloudHvDefines.fdf.inc, which replaces the generic one OvmfPkgDefines.fdf.inc. With this change, we prevent the firmware from accessing MMIO addresses from the address range 0xffc00000-0xffffffff since we know the firmware hasn't been loaded on this address range. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
* OvmfPkg/Microvm/pcie: add pcie supportGerd Hoffmann2022-06-032-16/+26
| | | | | | | | Link in pcie and host bridge bits. Enables support for PCIe in microvm (qemu-system-x86_64 -M microvm,pcie=on). Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3777 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/Microvm/pcie: mPhysMemAddressWidth tweakGerd Hoffmann2022-06-032-1/+42
| | | | | | | | | | | | | | microvm places the 64bit mmio space at the end of the physical address space. So mPhysMemAddressWidth must be correct, otherwise the pci host bridge setup throws an error because it thinks the 64bit mmio window is not addressable. On microvm we can simply use standard cpuid to figure the address width because the host-phys-bits option (-cpu ${name},host-phys-bits=on) is forced to be enabled. Side note: For 'pc' and 'q35' this is not the case for backward compatibility reasons. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/Microvm/pcie: no vbeshim pleaseGerd Hoffmann2022-06-031-0/+2
| | | | | | | Those old windows versions which need the vbeshim hack will not run on microvm anyway. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/Platform: unfix PcdPciExpressBaseAddressGerd Hoffmann2022-06-034-6/+8
| | | | | | | Will be set by FdtPciHostBridgeLib, so it can't be an fixed when we want use that library. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/FdtPciHostBridgeLib: io range is not mandatoryGerd Hoffmann2022-06-031-22/+23
| | | | | | | io range is not mandatory according to pcie spec, so allow host bridges without io address space. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/Microvm: drop CODE and VARS filesGerd Hoffmann2022-06-031-26/+0
| | | | | | | | microvm doesn't support pflash and loads the firmware via -bios, so we can't use the separate CODE and VARS files. Remove them. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/AmdSev: remove unused SMM bits from .dsc and .fdf filesGerd Hoffmann2022-06-032-62/+0
| | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Dov Murik <dovmurik@linux.ibm.com> Reviewed-by: Dov Murik <dovmurik@linux.ibm.com>
* OvmfPkg: Search EFI_RESOURCE_MEMORY_UNACCEPTED for Fw hoblistMin Xu2022-06-021-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current TDVF implementation all unaccepted memory passed in Hoblist are tagged as EFI_RESOURCE_MEMORY_UNACCEPTED. They're all accepted before they can be accessed. After accepting memory region, the Hob ResourceType is unchanged (still be EFI_RESOURCE_MEMORY_UNACCEPTED). TDVF Config-B skip PEI phase and it tries to find a memory region which is the largest one below 4GB. Then this memory region will be used as the firmware hoblist. So we should walk thru the input hoblist and search for the memory region with the type of EFI_RESOURCE_MEMORY_UNACCEPTED. Because EFI_RESOURCE_MEMORY_UNACCEPTED has not been officially in PI spec. So it cannot be defined in MdePkg/Include/Pi/PiHob.h. As a temporary solution it is defined in Hob.c. There is a patch-set for lazy-accept very soon. In that patch-set EFI_RESOURCE_MEMORY_UNACCEPTED will be defined in MdeModulePkg. Config-B: https://edk2.groups.io/g/devel/message/76367 Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg: Fix TDVMCALL error in ApRunLoop.nasmMin Xu2022-06-021-1/+2
| | | | | | | | | | | | | | | According to GHCI Spec Table 2-1, in TDVMCALL R10 should be cleared to 0 in input operands, and be checked for the return result. https://cdrdv2.intel.com/v1/dl/getContent/726790 Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 15:44:04 +0000