summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* UefiCpuPkg/PiSmmCpuDxeSmm: Reduce one round BSP & AP syncJiaxin Wu2023-12-261-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After BSP returned from SmmCoreEntry, there are several rounds BSP and AP sync in BSP handler: 1 .ReleaseAllAPs(); /// Notify all APs to exit. if (SmmCpuFeaturesNeedConfigureMtrrs()) { 2. SmmCpuSyncWaitForAPs(); /// Wait for all APs to program MTRRs. 3. ReleaseAllAPs(); /// Signal APs to restore MTRRs. } 4. SmmCpuSyncWaitForAPs(); /// Wait for all APs to complete pending tasks including MTRR. 5. ReleaseAllAPs(); /// Signal APs to Reset states. 6. SmmCpuSyncWaitForAPs(); /// Gather APs to exit SMM synchronously. Before step 6 and after step 5, BSP performs below items: A. InitializeDebugAgent() /// Stop source level debug. B. SmmCpuUpdate() /// Perform pending operations for hot-plug. C. Present = FALSE; /// Clear the Present flag of BSP. For InitializeDebugAgent(), BSP needs to wait all APs complete pending tasks and then notify all APs to stop source level debug. So, above step 4 & step 5 are required for InitializeDebugAgent(). For SmmCpuUpdate(), it's to perform pending operations for hot-plug CPUs take effect in next SMI. Existing APs in SMI do not reply on the CPU switch & hot-add & hot-remove operations. So, no need step 4 and step 5 for additional one round BSP & AP sync. Step 6 can make sure all APs are ready to exit SMM, then hot-plug operation can take effect in next SMI. For BSP "Present" flag, AP does not reply on it. No need step 4 and step 5 for additional one round BSP & AP sync. Based on above analysis, step 4 and step 5 are only required if need configure MTRR and support SMM source level debug. So, we can reduce one round BSP and AP sync if both are unsupported. With this change, SMI performance can be improved. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Invert ReleaseAllAPs & InitializeDebugAgentJiaxin Wu2023-12-261-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing BSP handler stops source level debug, then call ReleaseAllAPs to tell all APs can reset the Present flag to FALSE: InitializeDebugAgent (); /// Stop source level debug ReleaseAllAPs (); /// Tell APs can reset "Present" flag. This patch is to invert ReleaseAllAPs & InitializeDebugAgent: ReleaseAllAPs (); /// Tell APs can reset "Present" flag. InitializeDebugAgent (); /// Stop source level debug After this change, there is no negative impact since SMM source level debug feature doesn't depend on AP's "Present" flag, no impact to the SMM source level debug capability. Instead, the change will benefit the AP source level debug capability to trace its "Present" flag change for SMI exit since the source level debug feature will be stopped after each AP has the chance to reset the state. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Align BSP and AP sync logic for SMI exitJiaxin Wu2023-12-261-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below piece of code is the BSP and AP sync logic for SMI exit. 1. AP after finish the scheduled procedure: if (SmmCpuFeaturesNeedConfigureMtrrs ()) { SmmCpuSyncReleaseBsp (); SmmCpuSyncWaitForBsp (); ... } SmmCpuSyncReleaseBsp (); SmmCpuSyncWaitForBsp (); SmmCpuSyncReleaseBsp (); 2. BSP after return from SmmCoreEntry: SmmCpuSyncWaitForAPs (); if (SmmCpuFeaturesNeedConfigureMtrrs ()) { ReleaseAllAPs (); ... SmmCpuSyncWaitForAPs (); } ReleaseAllAPs (); SmmCpuSyncWaitForAPs(); This patch is to make BSP same as AP sync logic: if (SmmCpuFeaturesNeedConfigureMtrrs ()) { SmmCpuSyncWaitForAPs (); ReleaseAllAPs (); ... } SmmCpuSyncWaitForAPs (); ReleaseAllAPs (); SmmCpuSyncWaitForAPs(); With the change, it will be easy to understand the sync flow as below: BSP: SmmCpuSyncWaitForAPs <-- AP: SmmCpuSyncReleaseBsp BSP: ReleaseAllAPs --> AP: SmmCpuSyncWaitForBsp This patch doesn't have function impact. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check SMM Debug Agent support or notJiaxin Wu2023-12-264-11/+23
| | | | | | | | | | | | | | This patch is to check SMM Debug Agent support or not before InitializeDebugAgent. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* MdeModulePkg/DebugAgentLibNull: Indicate SMM Debug Agent support or notJiaxin Wu2023-12-261-0/+12
| | | | | | | | | | | This patch is to use the Context to indicate SMM Debug Agent support or not if InitFlag is DEBUG_AGENT_INIT_SMM. Context must point to a BOOLEAN if it's not NULL. Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* SourceLevelDebugPkg/Library: Indicate SMM Debug Agent support or notJiaxin Wu2023-12-261-2/+19
| | | | | | | | | | This patch is to use the Context to indicate SMM Debug Agent support or not if InitFlag is DEBUG_AGENT_INIT_SMM. Context must point to a BOOLEAN if it's not NULL. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* StandaloneMmPkg/Core: Remove dead codeRay Ni2023-12-252-184/+0
| | | | | | | | | | | Load-module-at-fixed-address feature does not work in standalone MM core. The patch removes the 2 dead functions and related global variables that are related to the feature. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg: Support customized FV Migration InformationCheng Sun2023-12-256-75/+106
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4533 There are use cases which not all FVs need be migrated from TempRam to permanent memory before TempRam tears down. This new guid is introduced to avoid unnecessary FV migration to improve boot performance. Platform can publish MigrationInfo hob with this guid to customize FV migration info, and PeiCore will only migrate FVs indicated by this Hob info. This is a backwards compatible change, PeiCore will check MigrationInfo hob before migration. If MigrationInfo hobs exists, only migrate FVs recorded by hobs. If MigrationInfo hobs not exists, migrate all FVs to permanent memory. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Cheng Sun <chengx.sun@intel.com>
* DynamicTablesPkg: AML Code generation to invoke a methodAbdul Lateef Attar2023-12-222-0/+353
| | | | | | | | | | | | Adds API to generate AML code to invoke/call another method. Also provides ability to pass arguments of type integer, string, ArgObj or LocalObj. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Corrects function pointer typedef of AML_PARSE_FUNCTIONAbdul Lateef Attar2023-12-221-2/+1
| | | | | | | | | | | Corrects the function pointer typedef AML_PARSE_FUNCTION, otherwise some compiler like VS2019 gives error. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Corrects AmlCodeGenRdWordBusNumber parametersAbdul Lateef Attar2023-12-222-10/+10
| | | | | | | | | | | Corrects the parameters of AmlCodeGenRdWordBusNumber() to UINT16 to generate word bus number. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: AML Code generation for word I/O rangesAbdul Lateef Attar2023-12-222-0/+153
| | | | | | | | | | | Add helper functions to generate AML resource data for word I/O. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* BaseTools/GenFw: Correct offset when relocating an ADRJake Garver2023-12-211-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When converting ELF to PE/COFF for the AArch64 target, we may encounter an R_AARCH64_ADR_GOT_PAGE relocation that refers to an ADR instruction instead of an ADRP instruction. This can happen when the toolchain is working around Cortex-A53 erratum #843419. If that's the case, be sure to calculate the offset appropriately. This resolves an issue experienced when building a StandaloneMm image (which is built with -fpie) with stack protection enabled on GCC compiled with "--enable-fix-cortex-a53-843419". In this case, the linker may convert an ADRP instruction appearing at an offset of 0xff8 or 0xffc modulo 4KiB into an ADR instruction, but will leave the original R_AARCH64_ADR_GOT_PAGE relocation in place. (This is not a bug in the linker, given that there is no other relocation type that it could reasonably convert it into) In this scenario, the following code is being generated by the toolchain: # Load to set the stack canary 2ffc: 10028020 adr x0, 8000 <mErrorString+0x1bc> 3008: f940d400 ldr x0, [x0, #424] # Load to check the stack canary 30cc: b0000020 adrp x0, 8000 <mErrorString+0x1bc> 30d0: f940d400 ldr x0, [x0, #424] GenFw rewrote that to: # Load to set the stack canary 2ffc: 10000480 adr x0, 0x308c 3008: 912ec000 add x0, x0, #0xbb0 # Load to check the stack canary 30cc: f0000460 adrp x0, 0x92000 30d0: 912ec000 add x0, x0, #0xbb0 Note that we're now setting the stack canary from the wrong address, resulting in an erroneous stack fault. After this fix, the offset will be calculated correctly for an ADR and the stack canary is set correctly. Note that there is a corner case where this may cause the conversion to fail: if the original GOT entry is just within -/+ 1 MiB of the reference, but the actual variable it refers to is not, the resulting offset cannot be represented by the immediate offset field in a ADR instruction. Given that this issue only affects PIE executables, which are rare and usually tiny, this is unlikely to cause problems in practice. Ref: https://edk2.groups.io/g/devel/topic/102202314 [ardb: expand commit log, add reference] Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* BaseTools: Resolve regex syntax warningsJoey Vagedes via groups.io2023-12-2118-60/+60
| | | | | | | | | | | | | Switches regex patterns to raw text to resolve python 3.12 syntax warnings in regards to invalid escape sequences, as is suggested by the re (regex) module in python. Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Joey Vagedes <joey.vagedes@gmail.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* BaseTools: FMMT GuidTool Auto Select Config file EnablingRebecca Cran2023-12-201-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4624 Currently, Python FMMT tool does not support automatically select FMMTConf.ini file which saves GuidTool settings. This patch supports this features. Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Signed-off-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuSyncLibJiaxin Wu2023-12-203-213/+68
| | | | | | | | | | | | | | | | | | | There is the SmmCpuSyncLib Library class define the SMM CPU sync flow, which is aligned with existing SMM CPU driver sync behavior. This patch is to consume SmmCpuSyncLib instance directly. With this change, SMM CPU Sync flow/logic can be customized with different implementation no matter for any purpose, e.g. performance tuning, handle specific register, etc. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Simplify RunningApCount decrementJiaxin Wu2023-12-201-1/+1
| | | | | | | | | | | | | | | | To decrease the count of RunningApCount, InterlockedDecrement is enough to achieve that. This patch is to simplify RunningApCount decrement. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiPayloadPkg: Specifies SmmCpuSyncLib instanceJiaxin Wu2023-12-201-0/+1
| | | | | | | | | | | | | | | This patch is to specify SmmCpuSyncLib instance for UefiPayloadPkg. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* OvmfPkg: Specifies SmmCpuSyncLib instanceJiaxin Wu2023-12-204-0/+4
| | | | | | | | | | | | | | | | This patch is to specify SmmCpuSyncLib instance for OvmfPkg. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Implements SmmCpuSyncLib library instanceJiaxin Wu2023-12-203-0/+688
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implements SmmCpuSyncLib Library instance. The instance refers the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation and behavior: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/MdeLibs.dsc.inc: Add SafeIntLib instanceJiaxin Wu2023-12-201-0/+1
| | | | | | | | | | | | | This patch is to add SafeIntLib in MdeLibs.dsc.inc Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Adds SmmCpuSyncLib library classJiaxin Wu2023-12-202-0/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. For the new SmmCpuSyncLib, it provides 3 sets of APIs: 1. ContextInit/ContextDeinit/ContextReset: ContextInit() is called in driver's entrypoint to allocate and initialize the SMM CPU Sync context. ContextDeinit() is called in driver's unload function to deinitialize SMM CPU Sync context. ContextReset() is called before CPU exist SMI, which allows CPU to check into the next SMI from this point. 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: When SMI happens, all processors including BSP enter to SMM mode by calling CheckInCpu(). The elected BSP calls LockDoor() so that CheckInCpu() will return the error code after that. CheckOutCpu() can be called in error handling flow for the CPU who calls CheckInCpu() earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. The 4 APIs are used to synchronize the running flow among BSP and APs. BSP and AP Sync flow can be easy understand as below: BSP: ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Optimize Semaphore Sync between BSP and APJiaxin Wu2023-12-201-14/+58
| | | | | | | | | | | | | | | | | | This patch is to define 3 new functions (WaitForBsp & ReleaseBsp & ReleaseOneAp) used for the semaphore sync between BSP & AP. With the change, BSP and AP Sync flow will be easy understand as below: BSP: ReleaseAllAPs or ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAllAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/UefiBootManagerLib: Signal ReadyToBoot on platform recoveryNeal Gompa2023-12-191-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the ReadyToBoot event is only signaled when a formal Boot Manager option is executed (in BmBoot.c -> EfiBootManagerBoot ()). However, the introduction of Platform Recovery in UEFI 2.5 makes it necessary to signal ReadyToBoot when a Platform Recovery boot loader runs because otherwise it may lead to the execution of a boot loader that has similar requirements to a regular one that is not launched as a Boot Manager option. This is especially critical to ensuring that the graphical console is actually usable during platform recovery, as some platforms do rely on the ConsolePrefDxe driver, which only performs console initialization after ReadyToBoot is triggered. This patch fixes that behavior by calling EfiSignalEventReadyToBoot () in EfiBootManagerProcessLoadOption () when invoking platform recovery, which is the function that sets up the platform recovery boot process. The expected behavior has been clarified in the UEFI 2.10 specification to explicitly indicate this behavior is required for correct operation. This is a rebased version of the patch originally written by Pete Batard. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2831 Co-authored-by: Pete Batard <pete@akeo.ie> Signed-off-by: Neal Gompa <ngompa@fedoraproject.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* OvmfPkg/RiscVVirt: Override for RISC-V CPU FeaturesDhaval2023-12-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | This PCD provides a way for platform to override any HW features that are default enabled by previous stages of FW (like OpenSBI). For the case where previous/prev stage has disabled the feature, this override is not useful and its usage should be avoided. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Utilize Cache Management Operations Implementation For RISC-VDhaval Sharma2023-12-194-28/+165
| | | | | | | | | | | | | | | | Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* MdePkg: Implement RISC-V Cache Management OperationsDhaval2023-12-194-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
* MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval2023-12-193-8/+8
| | | | | | | | | | | | | | | | | | | | There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Move RISC-V Cache Management Declarations Into BaseLibDhaval Sharma2023-12-192-20/+20
| | | | | | | | | | | | | | | The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* StandaloneMmPkg/Core: Fix the failure to find uncompressed inner FVWei6 Xu2023-12-191-0/+22
| | | | | | | | | | | | | | | The MmCoreFfsFindMmDriver only checks for encapsulated compressed FVs. When an inner FV is uncompressed, StandaloneMmCore will miss the FV and all the MM drivers in the FV will not be dispatched. Add checks for uncompressed inner FV to fix this issue. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* StandaloneMmPkg/Core: Fix issue that offset calculation might be wrongWei6 Xu2023-12-191-14/+15
| | | | | | | | | | | | | | | | | | | MmCoreFfsFindMmDriver() assumes FileHeader is EFI_FFS_FILE_HEADER. If FileHeader is an EFI_FFS_FILE_HEADER2, 'FileHeader + 1' will get a wrong section address. Use FfsFindSection to get the section directly, instead of 'FileHeader + 1' to avoid this issue. MmCoreFfsFindMmDriver() also assumes section is EFI_COMMON_SECTION_HEADER. If Section is EFI_COMMON_SECTION_HEADER2, 'Section + 1' will get a wrong wrong InnerFvHeader adress. Add section head detection and calculate the address accordingly. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* StandaloneMmPkg/Core: Fix potential memory leak issueWei6 Xu2023-12-191-9/+22
| | | | | | | | | | | | | | | | | | | | In MmCoreFfsFindMmDriver(), - ScratchBuffer is not freed in the error return path that DstBuffer page allocation fails. Free ScratchBuffer before return with error. - If the decoded buffer is identical to the data in InputSection, ExtractGuidedSectionDecode() will change the value of DstBuffer rather than changing the contents of the buffer that DstBuffer points at, in which case freeing DstBuffer is wrong. Introduce a local variable AllocatedDstBuffer for buffer free, free AllocatedDstBuffer immediately if it is not used. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* StandaloneMmPkg/Core: Limit FwVol encapsulation section recursionWei6 Xu2023-12-196-13/+49
| | | | | | | | | | | | | | | MmCoreFfsFindMmDriver() is called recursively for encapsulation sections. Currently this recursion is not limited. Introduce a new PCD (fixed-at-build, or patchable-in-module), and make MmCoreFfsFindMmDriver() track the section nesting depth against that PCD. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ShellPkg: Tidy for code readabilityDaniel Nguyen2023-12-181-19/+24
| | | | | | | | | | | Use error handling instead of success handling. Less indented logic is easier to read. Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Daniel Nguyen <daniel.nguyen@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* FatPkg/FatPei: Check array offset before useMichael Kubacki2023-12-141-1/+1
| | | | | | | | | Move the range check before array access to enforce the bounds as expected. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* ArmPkg/DebugPeCoffExtraActionLib: Drop RVCT and Cygwin supportArd Biesheuvel2023-12-141-69/+31
| | | | | | | | | | | | | | | | | The DebugPeCoffExtraActionLib implemention in ArmPkg contains some cruft that dates back to the original RVCT based ARM port, and support for RVCT was dropped a while ago. Also drop the handling of Cygwin specific paths, which is highly unlikely to be still depended upon by anyone. Tweak the logic so that only two versions of the DEBUG() invocations remain: one for __GNUC__ when PdbPointer is set, and the fallback that just prints the image address and the address of the entrypoint. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* CloudHv: Add CI for CloudHv on AArch64Jianyong Wu2023-12-142-0/+45
| | | | | | | | | | Add the long lost CI for CloudHv on AArch64. As CloudHv CI works nearly the same way with other VMMs like KvmTool, thus we can easily create its CI configuration based on KvmTool. Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* RedfishPkg/RedfishDicovery: Remedy Redfish service discovery flowAbner Chang2023-12-131-70/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remedy Redfish service discovery flow changes made in commit 8736b8fd. The above fix creates the dependency with SMBIOS 42h record, which has a problem as SMBIOS 42h may not be created when RedfishDiscovery.Supported() is invoked even all of the required protocols are ready on the ControllerHandle. We can’t guarantee SMBIOS 42 structure will be always created before ConnectController(). USB NIC maybe detected late and it means PlatformHostInterfaceBmcUsbNicLib can populate SMBIOS 42h information late as well. Calling to RedfishServiceGetNetworkInterface with the previous fix may result in no network interface for BMC-exposed NIC as SMBIOS 42h is not ready yet.This is the first issue. Second, to skip the network interface when NetworkInterfaceGetSubnetInfo() returns a failure also has problem, as the NIC may be configured via RestEx->Configure(). This happens after the Host interface is discovered, as at this moment we have the sufficient network information to configure BMC-exposed NIC. Base on Redfish spec in 31.1.5.2, “EFI Redfish Client may provide selection UI of network interfaces for Redfish service discovery.", This means edk2 Redfish client gets all network interfaces through RedfishServiceGetNetworkInterface and choose the desired network interface at its discretion for Redfish service. So the fix here is: 1. In BuildNetworkInterface(), we don’t skip any network interface. In RedfishServiceGetNetworkInterface, we don’t skip any network interface even the subnet information is not retrieved. We will still return all of network interfaces to client. 2. In RedfishServiceAcquireService for EFI_REDFISH_RISCOVER_HOST_INTERFACE case, we don’t skip any network interface even the subnet information is not retrieved. 3. Added some more debug information. Note: The subnet information is used for the scenario the system is managed by a centralized Redfish service (not on BMC), says the multiple Redfish computer system instances. As it mentions in 31.1.5.2, Redfish client they may have to know the subnet information so they can know the network domain the NIC is connected. There may have multiple subnets in the corporation network environment. So the subnet information provides client an idea when they choose the network interface, so does VLAN ID. Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com> Acked-by: Mike Maslenkin <mike.maslenkin@gmail.com>
* ArmVirtQemu: Allow EFI memory attributes protocol to be disabledArd Biesheuvel2023-12-123-0/+73
| | | | | | | | | | | | | | | | | | | | | | | Shim's PE loader uses the EFI memory attributes protocol in a way that results in an immediate crash when invoking the loaded image, unless the base and size of its executable segment are both aligned to 4k. If this is not the case, it will strip the memory allocation of its executable permissions, but fail to add them back for the executable region, resulting in non-executable code. Unfortunately, the PE loader does not even bother invoking the protocol in this case (as it notices the misalignment), making it very hard for system firmware to work around this by attempting to infer the intent of the caller. So let's introduce a QEMU command line option to indicate that the protocol should not be exposed at all, and a PCD to set the default for this option when it is omitted. Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Link: https://gitlab.com/qemu-project/qemu/-/issues/1990 Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg: Avoid assuming only one smmbasehobDun Tan2023-12-121-32/+149
| | | | | | | | | | | | | | Modify the gSmmBaseHobGuid consumption code to remove the asuumption that there is only one gSmmBaseHobGuid. If the CPU number is big enough, there will be more than one SmmBaseHob in the HOB list. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Cache core type in MpInfo2 HOBDun Tan2023-12-122-2/+59
| | | | | | | | | | Cache core type in MpInfo2 HOB by CpuMpPei module. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Add a new field in MpInfo2 HOBDun Tan2023-12-121-0/+2
| | | | | | | | | | Add new field CoreType in gMpInformationHobGuid2 Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Consume MpInfo2Hob in PiSmmCpuDxeDun Tan2023-12-123-51/+168
| | | | | | | | | | | | | | Consume MpInfo2Hob in PiSmmCpuDxe driver to get NumberOfProcessors, MaxNumberOfCpus and EFI_PROCESSOR_INFORMATION for all CPU from the MpInformation2 HOB. This can avoid calling MP service. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Build MpInfo2HOB in CpuMpPeiDun Tan2023-12-123-2/+96
| | | | | | | | | | | | | | | | Build MpInfo2HOB in CpuMpPei module so that later PiSmmCpuDxe or other StandaloneMm module can consume the HOB. Since there might be more one gMpInformationHobGuid2 in HOB list, CpuMpPei create a gMpInformationHobGuid2 with 0 value NumberOfProcessors field in the end of the process to indicate it's the last MP_INFORMATION2_HOB. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Create gMpInformationHobGuid2 in UefiCpuPkgDun Tan2023-12-122-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create gMpInformationHobGuid2 in UefiCpuPkg. Currently, there is a gMpInformationHobGuid defined, created and consumed only in StandaloneMmPkg. The HOB contains the EFI_PROCESSOR_INFORMATION structure for each CPU and the number of processors. This is the same as the information that PiSmmCpuDxeSmm uses MpService Protocol to get. This new gMpInformationHobGuid2 also contains the NumberOfProcessors and the EFI_PROCESSOR_INFORMATION for each CPU. Also the HOB is extended to support the case that the maximum HOB length is not enough for all CPU. So there might be more than one HOB instance in the HOB list. Each HOB describes the corresponding CPU index range. The plan is to create gMpInformationHob2Guid in CpuMpPei module(implemented in next commit). Then PiSmmCpuDxeSmm and other MM_STANDALONE modules can consume the hob. This can avoid calling MpService Protocol in PiSmmCpuDxeSmm. Also the issue that one gMpInformationHobGuid might be not enough when CPU number is 1~2000 or bigger can be solved. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg:simplify Fifo API in BaseIoLibIntrinsicDun Tan2023-12-114-259/+222
| | | | | | | | | | | | | | | | | | Simplify IoRead/WriteFifo implement by repeatedly calling IoRead/Write in the C code. This can avoid calling assembly code to use string I/O instructions. With this change Ia32/IoFifo.nasm and X64/IoFifo.nasm can be removed. Then the source files for IA32 and X64 are the same. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Change IoLibFifo.c to IoLibFifoCc.cDun Tan2023-12-112-2/+2
| | | | | | | | | | | | | | | | Change IoLibFifo.c to IoLibFifoCc.c since the file is for Tdx and SEV in BaseIoLibIntrinsicSev. It's also to distinguish with a new incoming IoLibFifo.c for BaseIoLibIntrinsic. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg: Sync debug level comments in ArmVirt.dsc.incRebecca Cran2023-12-111-20/+22
| | | | | | | | | Update the debug level comments in ArmVirt.dsc.inc to sync with MdePkg/Include/Library/DebugLib.h. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg: Update MdePkg.uni with manageability debug levelRebecca Cran2023-12-111-0/+2
| | | | | | | Update MdePkg.uni with the manageability debug level. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add manageability debug level to PcdFixedDebugPrintErrorLevelRebecca Cran2023-12-111-0/+1
| | | | | | | | Update MdePkg.dec to add the manageability debug level to PcdFixedDebugPrintErrorLevel. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 10:28:58 +0000