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* pip: bump edk2-basetools from 0.1.48 to 0.1.49dependabot/pip/edk2-basetools-0.1.49dependabot[bot]2023-06-301-1/+1
| | | | | | | | | | | | | Bumps [edk2-basetools](https://github.com/tianocore/edk2-basetools) from 0.1.48 to 0.1.49. - [Commits](https://github.com/tianocore/edk2-basetools/commits) --- updated-dependencies: - dependency-name: edk2-basetools dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] <support@github.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove unnecessary functionDun Tan2023-06-303-40/+6
| | | | | | | | | | | Remove unnecessary function SetNotPresentPage(). We can directly use ConvertMemoryPageAttributes to set a range to non-present. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Refinement to smm runtime InitPaging() codeDun Tan2023-06-302-228/+100
| | | | | | | | | | | | | | | | This commit is code refinement to current smm runtime InitPaging() page table update code. In InitPaging(), if PcdCpuSmmProfileEnable is TRUE, use ConvertMemoryPageAttributes() API to map the range in mProtectionMemRange to the attrbute recorded in the attribute field of mProtectionMemRange, map the range outside mProtectionMemRange as non-present. If PcdCpuSmmProfileEnable is FALSE, only need to set the ranges not in mSmmCpuSmramRanges as NX. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Sort mProtectionMemRange when ReadyToLockDun Tan2023-06-301-0/+32
| | | | | | | | | | | Sort mProtectionMemRange in InitProtectedMemRange() when ReadyToLock. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Sort mSmmCpuSmramRanges in FindSmramInfoDun Tan2023-06-301-0/+32
| | | | | | | | | | | Sort mSmmCpuSmramRanges after get the SMRAM info in FindSmramInfo() function. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Use GenSmmPageTable() to create Smm S3 page tableDun Tan2023-06-303-147/+5
| | | | | | | | | | | Use GenSmmPageTable() to create both IA32 and X64 Smm S3 page table. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Add GenSmmPageTable() to create smm page tableDun Tan2023-06-304-195/+107
| | | | | | | | | | | | | | | This commit is code refinement to current smm pagetable generation code. Add a new GenSmmPageTable() API to create smm page table based on the PageTableMap() API in CpuPageTableLib. Caller only needs to specify the paging mode and the PhysicalAddressBits to map. This function can be used to create both IA32 pae paging and X64 5level, 4level paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.hDun Tan2023-06-305-8/+3
| | | | | | | | | | | Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove extern for mSmmShadowStackSize in c files to simplify code. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR0.WP before modify page tableDun Tan2023-06-302-0/+16
| | | | | | | | | | | | | | | | | | | | Clear CR0.WP before modify smm page table. Currently, there is an assumption that smm pagetable is always RW before ReadyToLock. However, when AMD SEV is enabled, FvbServicesSmm driver calls MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit in smm page table for this range: [PcdOvmfFdBaseAddress,PcdOvmfFdBaseAddress+PcdOvmfFirmwareFdSize] If page slpit happens in this process, new memory for smm page table is allocated. Then the newly allocated page table memory is marked as RO in smm page table in this FvbServicesSmm driver, which may lead to PF if smm code doesn't clear CR0.WP before modify smm page table when ReadyToLock. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add 2 function to disable/enable CR0.WPDun Tan2023-06-302-49/+90
| | | | | | | | | | | | Add two functions to disable/enable CR0.WP. These two unctions will also be used in later commits. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid setting non-present range to RO/NXDun Tan2023-06-301-22/+107
| | | | | | | | | | | | | | | In PiSmmCpuDxeSmm code, SetMemMapAttributes() marks memory ranges in SmmMemoryAttributesTable to RO/NX. There may exist non-present range in these memory ranges. Set other attributes for a non-present range is not permitted in CpuPageTableMapLib. So add code to handle this case. Only map the present ranges in SmmMemoryAttributesTable to RO or NX. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Add DEBUG_CODE for special case when clear RPDun Tan2023-06-301-0/+48
| | | | | | | | | | | | | | | | | | In ConvertMemoryPageAttributes() function, when clear RP for a specific range [BaseAddress, BaseAddress + Length], it means to set the present bit to 1 and assign default value for other attributes in page table. The default attributes for the input specific range are NX disabled and ReadOnly. If there is existing present range in [BaseAddress, BaseAddress + Length] and the attributes are not NX disabled or not ReadOnly, then output the DEBUG message to indicate that the NX and ReadOnly attributes of the existing present range are modified in the function. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Use CpuPageTableLib to convert SMM paging attribute.Dun Tan2023-06-305-325/+121
| | | | | | | | | | | | | | Simplify the ConvertMemoryPageAttributes API to convert paging attribute by CpuPageTableLib. In the new API, it calls PageTableMap() to update the page attributes of a memory range. With the PageTableMap() API in CpuPageTableLib, we can remove the complicated page table manipulating code. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* MdeModulePkg: Remove other attribute protection in UnsetGuardPageDun Tan2023-06-301-1/+15
| | | | | | | | | | | | | | | | In UnsetGuardPage(), before SmmReadyToLock, remove NX and RO memory attribute protection for guarded page since EfiConventionalMemory in SMRAM is RW and executable before SmmReadyToLock. If UnsetGuardPage() happens after SmmReadyToLock, then apply EFI_MEMORY_XP to the guarded page to make sure EfiConventionalMemory in SMRAM is NX since EfiConventionalMemory in SMRAM is marked as NX in PiSmmCpuDxe driver when SmmReadyToLock. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
* OvmfPkg:Remove code that apply AddressEncMask to non-leaf entryDun Tan2023-06-301-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove code that sets AddressEncMask for non-leaf entries when modifing smm page table by MemEncryptSevLib. In FvbServicesSmm driver, it calls MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit in page table for a specific range. In AMD SEV feature, this AddressEncMask bit in page table is used to indicate if the memory is guest private memory or shared memory. But all memory accessed by the hardware page table walker is treated as encrypted, regardless of whether the encryption bit is present. So remove the code to set the EncMask bit for smm non-leaf entries doesn't impact AMD SEV feature. The reason encryption mask should not be set for non-leaf entries is because CpuPageTableLib doesn't consume encryption mask PCD. In PiSmmCpuDxeSmm module, it will use CpuPageTableLib to modify smm page table in next patch. The encryption mask is overlapped with the PageTableBaseAddress field of non-leaf page table entries. If the encryption mask is set for smm non-leaf page table entries, issue happens when CpuPageTableLib code use the non-leaf entry PageTableBaseAddress field with the encryption mask set to find the next level page table. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Variable: Introduce MM based variable read service in PEIKun Qin2023-06-284-0/+556
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4464 This change introduced the Standalone MM based variable read capability in PEI phase for applicable platforms (such as ARM platforms). Similar to the x86 counterpart, MM communicate PPI is used to request variable information from Standalone MM environment. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jian J Wang <jian.j.wang@intel.com> Co-authored-by: Ronny Hansen <hansen.ronny@microsoft.com> Co-authored-by: Shriram Masanamuthu Chinnathurai <shriramma@microsoft.com> Co-authored-by: Preshit Harlikar <pharlikar@microsoft.com> Signed-off-by: Kun Qin <kuqin@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* ArmPkg: MmCommunicationPei: Introduce MM communicate in PEIKun Qin2023-06-283-0/+263
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4464 This change introduced the MM communicate support in PEI phase for ARM based platforms. Similar to the DXE counterpart, `PcdMmBufferBase` is used as communicate buffer and SMC will be invoked to communicate to TrustZone when MMI is requested. Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Co-authored-by: Ronny Hansen <hansen.ronny@microsoft.com> Co-authored-by: Shriram Masanamuthu Chinnathurai <shriramma@microsoft.com> Co-authored-by: Preshit Harlikar <pharlikar@microsoft.com> Signed-off-by: Kun Qin <kuqin@microsoft.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* NetworkPkg: Correct the length of EAP Identity when in ASCII formatdevel@edk2.groups.io2023-06-281-4/+17
| | | | | | | | | | | | | | FIX: https://bugzilla.tianocore.org/show_bug.cgi?id=4477 Tls connection fail over WiFi in AMT OCR flow due to invalid identity. This was due to missing conversion between unicode and ascii string which resulted in invalid strlen. Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Zachary Clark-Williams <zachary.clark-williams@intel.com> Signed-off-by: Yi Li <yi1.li@intel.com> Reviewed-by: Zachary Clark-Williams <zachary.clark-williams@intel.com>
* Maintainers.txt: Update NetworkPkg maintainers and reviewersSaloni Kasbekar2023-06-281-2/+2
| | | | | | | | | | | | Add Zack, Saloni and remove unused IDs Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Zachary Clark-willilams <zachary.clark-williams@intel.com> Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com> Reviewed-by: Zachary Clark-willilams <zachary.clark-williams@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseTools/tools_def: Add "-fno-unwind-tables" to GCC5_RISCV64_CC_FLAGSSunil V L2023-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | gcc-13 for RISC-V enables unwind tables by default similar to ARM64. This generates .eh_frame_hdr section which is not handled well by GenFw causing failures. Disable the unwind tables by adding -fno-unwind-tables flag similar to [1]. [1] - https://github.com/tianocore/edk2/commit/cbf00651eda6 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* OvmfPkg/VirtioSerialDxe: Remove noisy debug print on supported() callArd Biesheuvel2023-06-271-2/+0
| | | | | | | | | | | | The UEFI driver model invokes the supported() method on every driver every time a connection attempt is made on any handle, and so doing an unconditional DEBUG() print inside this method produced a lot of noise. So let's drop this DEBUG() call from the VirtioSerial driver's Supported() method. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* ArmPkg/OpteeLib: Map shared communication buffer non-executableArd Biesheuvel2023-06-271-1/+6
| | | | | | | | | | The OP-TEE secure OS exposes a non-secure memory region for communication between the secure OS itself and any clients in the non-secure firmware. This memory is writable by non-secure and is not used for code only data, and so it should be mapped non-executable. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg: Drop individual memory permission helpersArd Biesheuvel2023-06-274-304/+4
| | | | | | | | | | Now that we have a sane API to set and clear memory permissions that works the same on ARM and AArch64, we no longer have a need for the individual set/clear no-access/read-only/no-exec helpers so let's drop them. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* StandaloneMmPkg: Include correct MmuLib headerArd Biesheuvel2023-06-272-2/+2
| | | | | | | | | | StandaloneMm has its own version of the ArmMmuLib library class, but includes the ArmMmuLib header. This happens to work because the prototypes that are referenced are the same, but this will no longer be the case after a future patch. So correct the #includes. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* UefiCpuPkg/ResetVector: Remove pre-built binariesRay Ni2023-06-2716-199/+9
| | | | | | | | | | | | Because it's simpler for a platform to include the ResetVector source and having pre-built binaries add burdens of updating the pre-built binaries. This patch removes the pre-built binaries and the script that buids the pre-built binaries. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/ResetVector: Add guidance of FDF ffs ruleRay Ni2023-06-272-21/+25
| | | | | | | | | | | | | | | | | | | ResetVector assembly implementation puts "ALIGN 16" in the end to guarantee the final executable file size is multiple of 16 bytes. Because the module uses a special GUID which guarantees it's put in the very end of a FV, which should be also the end of the FD. All of these (file size is multiple of 16B, and the module is put at end of FV, FV is put at end of FD) guarantee the "JMP xxx" instruction is at FFFF_FFF0h. This patch updates INF file and ReadMe.txt to add guidance of FDF ffs rule for the ResetVector. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Include ResetVector in DSCRay Ni2023-06-271-2/+2
| | | | | | | | | | Since ResetVector source module shares the same GUID as the binary module, the binary INF file is just removed from DSC. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* CI: Use latest image for Linux jobs (Qemu 8, gcc 12)Oliver Steffen2023-06-271-1/+1
| | | | | | | | | | | Use the latest Linux container image (from 2023-05-30). It uses Qemu 8.0.0 and gcc 12. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4324 Signed-off-by: Oliver Steffen <osteffen@redhat.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* OvmfPkg/PciHotPlugInitDxe: fix io window sizeGerd Hoffmann2023-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smallest IO window size for PCI bridges is 0x1000. Fix default size accordingly. Avoids broken resource assignments like this: [ ... ] PciBus: Resource Map for Root Bridge PciRoot(0x0) Type = Io16; Base = 0x6000; Length = 0x7000; Alignment = 0xFFF [ ... ] Base = 0xC000; Length = 0x200; Alignment = 0xFFF; Owner = PPB [00|02|00:**] Base = 0xC200; Length = 0x40; Alignment = 0x3F; Owner = PCI [00|1F|03:20] Base = 0xC240; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|1F|02:20] [ ... ] ... which the linux kernel fixes up later: [ 0.644657] pci 0000:00:1f.3: BAR 4: assigned [io 0x1000-0x103f] [ 0.646833] pci 0000:00:1f.2: BAR 4: assigned [io 0x1040-0x105f] With the patch applied: { ... ] PciBus: Resource Map for Root Bridge PciRoot(0x0) Type = Io16; Base = 0x6000; Length = 0x8000; Alignment = 0xFFF [ ... ] Base = 0xC000; Length = 0x1000; Alignment = 0xFFF; Owner = PPB [00|02|00:**] Base = 0xD000; Length = 0x40; Alignment = 0x3F; Owner = PCI [00|1F|03:20] Base = 0xD040; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|1F|02:20] [ ... ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* ArmPkg/CpuDxe: Simplify memory attributes protocol implementationArd Biesheuvel2023-06-261-48/+2
| | | | | | | | | | | Now that ArmSetMemoryAttributes() permits a mask to be provided, we can simplify the implementation the UEFI memory attribute protocol substantially, and just pass on the requested mask to be set or cleared directly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdeModulePkg/DxeIpl ARM AARCH64: Switch to generic handoff codeArd Biesheuvel2023-06-262-81/+1
| | | | | | | | | | | Now that we have a generic method to manage memory permissions using a PPI, we can switch to the generic version of the DXE handoff code in DxeIpl, and drop the ARM specific version. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* ArmPkg/CpuPei: Implement the memory attributes PPIArd Biesheuvel2023-06-262-0/+80
| | | | | | | | | | | Implement the newly defined PPI that permits the PEI core and DXE IPL to manage memory permissions on ranges of DRAM, for doing things like mapping the stack non-executable, or granting executable permissions to shadowed PEIMs. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* ArmPkg/ArmMmuLib: Extend API to manage memory permissions betterArd Biesheuvel2023-06-265-17/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, ArmSetMemoryAttributes () takes a combination of EFI_MEMORY_xx constants describing the memory type and permission attributes that should be set on a region of memory. In cases where the memory type is omitted, we assume that the memory permissions being set are final, and that existing memory permissions can be discarded. This is problematic, because we aim to map memory non-executable (EFI_MEMORY_XP) by default, and only relax this requirement for code regions that are mapped read-only (EFI_MEMORY_RO). Currently, setting one permission clears the other, and so code managing these permissions has to be aware of the existing permissions in order to be able to preserve them, and this is not always tractable (e.g., the UEFI memory attribute protocol implements an abstraction that promises to preserve memory permissions that it is not operating on explicitly). So let's add an AttributeMask parameter to ArmSetMemoryAttributes(), which is permitted to be non-zero if no memory type is being provided, in which case only memory permission attributes covered in the mask will be affected by the update. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdeModulePkg/DxeIpl: Use memory attribute PPI to remap the stack NXArd Biesheuvel2023-06-262-4/+30
| | | | | | | | | | | | If the associated PCD is set to TRUE, use the memory attribute PPI to remap the stack non-executable. This provides a generic method for doing so, which will be used by ARM and AArch64 as well once they move to the generic DxeIpl handoff implementation. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/DxeIpl: Merge EBC, RISCV64 and LOONGARCH codeArd Biesheuvel2023-06-264-147/+3
| | | | | | | | | | | | | | | The Risc-V and LoongArch specific versions of the DXE core handoff code in DxeIpl are essentially copies of the EBC version (modulo the copyright in the header and some debug prints in the code). In preparation for introducing a generic PPI based method to implement the non-executable stack, let's merge these versions, so we only need to add this logic once. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Define memory attribute PPIArd Biesheuvel2023-06-262-0/+86
| | | | | | | | | | | | | Define a PPI interface that may be used by the PEI core or other PEIMs to manage permissions on memory ranges. This is primarily intended for restricting permissions to what is actually needed for correct execution by the code in question, and for limiting the use of memory mappings that are both writable and executable at the same time. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* IntelFsp2WrapperPkg: Get HobListPtr before calling the Multiphase FSPSAishwarya, KurugoduMelmatamX2023-06-261-7/+8
| | | | | | | | | | | | | | | | | | | | REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480 In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will be able to get the correct FspHobListPtr value Signed-off-by: kurugodx <kurugodumelmatamx.aishwarya@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Chen Gang C <gang.c.chen@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* OvmfPkg/Bhyve: include TPM driverCorvin Köhne2023-06-232-2/+22
| | | | | | | | | | Bhyve will gain support for TPM emulation in the near future. Therefore, prepare OVMF by copying all TPM driver used by qemu's OVMF DSC into the bhyve OVMF DSC. Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/Bhyve: install Acpi tables provided by FwCfgCorvin Köhne2023-06-231-0/+5
| | | | | Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Peter Grehan <grehan@freebsd.org>
* OvmfPkg: move QemuFwCfgAcpi into AcpiPlatformLibCorvin Köhne2023-06-236-11/+14
| | | | | | | This makes the InstallQemuFwcfgTables function reusable by bhyve. Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Peter Grehan <grehan@freebsd.org>
* OvmfPkg: move BootScript into AcpiPlatformLibCorvin Köhne2023-06-235-31/+30
| | | | | | | This is required to move InstallQemuFwCfgTables into AcpiPlatformLib. Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Peter Grehan <grehan@freebsd.org>
* OvmfPkg: move PciEncoding into AcpiPlatformLibCorvin Köhne2023-06-2319-274/+38
| | | | | | | | | Bhyve supports providing ACPI tables by FwCfg. Therefore, InstallQemuFwCfgTables should be moved to AcpiPlatformLib to reuse the code. As first step, move PciEncoding into AcpiPlatformLib. Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Peter Grehan <grehan@freebsd.org>
* OvmfPkg: avoid including AcpiPlatformLib twiceCorvin Köhne2023-06-231-0/+5
| | | | | Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Acked-by: Peter Grehan <grehan@freebsd.org>
* OvmfPkg/Library: fix definition of GetAcpiRsdpFromMemoryCorvin Köhne2023-06-231-2/+2
| | | | | | | | | | | | The definition and declaration of GetAcpiRsdpFromMemory doesn't match. We don't get a compile error yet because UINTN is the same as UINT64 on 64bit machines. As the function works on memory addresses, UINTN is the correct type of the input parameters. Signed-off-by: Corvin Köhne <corvink@FreeBSD.org> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Peter Grehan <grehan@freebsd.org>
* SecurityPkg: SubClassTpm: Updated default valueKun Qin2023-06-232-4/+4
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This change updated the default value of TPM device subclass PCD to `0x010E0000` in order to match the definition of EFI_PERIPHERAL_TPM from PI specification v1.8. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Qi Zhang <qi1.zhang@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add TPM subclass definition to MdePkgKun Qin2023-06-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This change introduces a new peripheral subclass definition from PI specification v1.8. The new subclass definition will cover system reboot events under the status reports from Trusted Platform Modules (TPMs). These definition could provide helpful datapoints to OEMs to analyze system security state and healthiness, as well as avoid definition collision with other existing peripheral subclass definitions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: PiStatusCode: Add new Host Software class Error Code to MdePkgKun Qin2023-06-231-20/+21
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794 This change introduces a new error code definitions under Host Software class according to PI specification v1.8. The new error code definition will cover system reboot events under the conditions of inconsistent memory map from one boot to another. These error codes could provide helpful datapoints to OEMs to investigate and prevent system failures in general. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* OvmfPkg/RiscVVirt: Add a readme for build and testSunil V L2023-06-231-0/+49
| | | | | | | | | | | | | Add a readme file which provides information regarding how to build and test EDK2 on RISC-V qemu virt platform. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* OvmfPkg/RiscVVirt: Add support for separate code and variable storeSunil V L2023-06-233-13/+19
| | | | | | | | | | | | | | | | | | | Currently, RiscVVirtQemu supports unified code and variable store mainly because only one pflash devices was available in qemu for EDK2. However, this doesn't allow to map the code part as read-only. With recent qemu enhancements, it is now possible for EDK2 to make use of both pflash devices in RISC-V virt machine. So, add support to create code and vars images separately. This also allows easy firmware code updates without losing the variable store. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* OvmfPkg/RiscVVirt: Add VirtNorFlashDeviceTreeLib librarySunil V L2023-06-232-0/+177
| | | | | | | | | | | | | This library is required to support separate code and variable store images. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-09 22:39:54 +0000