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* pip: bump edk2-pytool-library from 0.14.1 to 0.18.2dependabot/pip/edk2-pytool-library-0.18.2dependabot[bot]2023-10-051-1/+1
| | | | | | | | | | | | | | Bumps [edk2-pytool-library](https://github.com/tianocore/edk2-pytool-library) from 0.14.1 to 0.18.2. - [Release notes](https://github.com/tianocore/edk2-pytool-library/releases) - [Commits](https://github.com/tianocore/edk2-pytool-library/compare/v0.14.1...v0.18.2) --- updated-dependencies: - dependency-name: edk2-pytool-library dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] <support@github.com>
* MdePkg/DxeRngLib: Add missing GUID declaration in infPierre Gondois2023-10-041-0/+1
| | | | | | | | | | | | Add missing GUID declaration in DxeRngLib.inf. Fixes: bd1f0eecc1df ("MdePkg/DxeRngLib: Request raw algorithm instead of default") Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Leif Lindholm <quic_llindhol@quicinc.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: fix typo in Arm SetJumpLeif Lindholm2023-10-031-1/+1
| | | | | | | | | | RO -> R0 Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: ensure ARM LongJump never returns 0Leif Lindholm2023-10-022-0/+4
| | | | | | | | | | | The ARM implementation of InternalLongJump always returned the value Value - but it is not supposed to ever return 0. Add the test to prevent that, and return 1 if Value is 0 - as is already present in AArch64. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: correct register sizes in AArch64 SetJump/LongJumpLeif Lindholm2023-10-022-8/+8
| | | | | | | | | | | | | | | | Both in SetJump and in InternalLongJump, 32-bit w register views were used for the UINTN return value. In SetJump, this did not cause errors; it was only counterintuitive. But in InternalLongJump, it meant the top 32 bits of Value were stripped off. Change all of these to use the 64-bit x register views. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reanimated-by: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* MdePkg/BaseLib: use normal register init in ARM SetJump implementationsLeif Lindholm2023-10-022-2/+2
| | | | | | | | | | | | | There may be architectures on which there are benefits to eor r0, r0(, r0) but ARM was never one of them. Change to more readable mov r0, #0 instead. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: add ASSERT in ARM* SetJump implementationsLeif Lindholm2023-10-022-0/+16
| | | | | | | | | | | | | The SetJump comment header states that: If JumpBuffer is NULL, then ASSERT(). However, this was not currently done. Add a call to InternalAssertJumpBuffer. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: fix comments in ARM* SetJump/LongJump implementationsLeif Lindholm2023-10-024-8/+4
| | | | | | | | | | | | | | Drop redundant comment about IPF (clearly copied across from now deleted code). Also change "Instead is resumes execution" -> "Instead it resumes execution" Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* Maintainers.txt: add Sami as maintainer of arm-architectural subdirsLeif Lindholm2023-10-021-0/+1
| | | | | | | | | | | | | | | | We added Sami as a reviewer to ArmPkg early last year, and I think it was always our intention to have him as a reviewer of Arm architectural stuff in general, but we seem to have missed out the Arm/AArch64 subdir wildcards. So let's fix that. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Andrew Fish <afish@apple.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdeModulePkg/Xhci: Skip size round up for TRB during address translationGao Cheng2023-09-286-63/+103
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560 TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI device/host memory address, it may exceed xHCI host memory pool and cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate whether to enforce 64byte size alignment and round up. For TRB case, should set it to FALSE to skip the size round up. Signed-off-by: Gao Cheng <gao.cheng@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* EmulatorPkg: Fix Terminal IssuesNate DeSimone2023-09-272-2/+57
| | | | | | | | | | | | After running EmulatorPkg, one will notice that their terminal acts strangely. This is caused by the EmulatorPkg Host changing the terminal mode and not restoring the original mode, which is now fixed. Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* MdeModulePkg/SmbiosDxe: Fix BcdRevision is not match with SMBIOS versionHoraceX Lien2023-09-261-8/+12
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4544 These value of Major/Minor version are updated from SMBIOS memory data, but BCD Revision is updated from PCD PcdSmbiosVersion. We should also update BCD Revision from SMBIOS memory data, to ensure that get consistent version value. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: HoraceX Lien <horacex.lien@intel.com>
* MdeModulePkg: Fix misspellingNate DeSimone2023-09-261-2/+2
| | | | | | | | | | confroms should be conforms. Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Dandan Bi <dandan.bi@intel.com>
* UefiPayloadPkg: Add FIT supportBrucex.Wang2023-09-2614-103/+1899
| | | | | | | | | | | | | | Provide Fit format for UniversalPayload, developer can use argument "--Fit" to build UniversalPayload.fit Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* MdePkg/BaseFdtLib: Add Fdt function.Brucex.Wang2023-09-262-0/+74
| | | | | | | | | | | | | | Add FdtGetName() and FdtNodeDepth() function. Cc: Benny Lin <benny.lin@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Benny Lin <benny.lin@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: BruceX Wang <brucex.wang@intel.com>
* BaseTools/GenFw: Add support for LOONGARCH64 relax relocationDongyan Qian2023-09-252-1/+32
| | | | | | | | | | | | | | | | Correct relax id from 99 to 100 and added relocation support up to 109 fix gcc14 adds new relocation, and the generated relocation causes the build and compilation to fail. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4559 Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn>
* MdeModulePkg/XhciDxe: Abort the Address Device cmd when time outCai, Xianglei2023-09-251-0/+36
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4552 Following XHCI spec 4.6.1.2, software may abort the execution of Address Device Command when command failed due to timeout. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: More Shih <more.shih@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Signed-off-by: Xianglei Cai <xianglei.cai@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/XhciDxe: Use Performance Timer for XHCI TimeoutsHenz, Patrick2023-09-255-87/+204
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2948 XhciDxe uses the timer functionality provided by the boot services table to detect timeout conditions. This breaks the driver's ExitBootServices call back, as CoreExitBootServices halts the timer before signaling the ExitBootServices event. If the host controller fails to halt in the call back, the timeout condition will never occur and the boot gets stuck in an indefinite spin loop. Use the free running timer provided by TimerLib to calculate timeouts, avoiding the potential hang. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Patrick Henz <patrick.henz@hpe.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* DynamicTablesPkg: AcpiSsdtPcieLibArm: Use QWord to describe I/O rangeVidya Sagar2023-09-221-1/+1
| | | | | | | | | | Use AmlCodeGenRdQWordIo() to generate the I/O range in _CRS instead of AmlCodeGenRdDWordIo() to cater to the scenarios where 64-bit addresses can be used to generate I/O packets over the PCIe bus. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: AML Code generation for I/O rangesVidya Sagar2023-09-222-0/+157
| | | | | | | | | Add helper functions to generate AML Resource Data describing I/O ranges of four words long. API AmlCodeGenRdQWordIo () is exposed. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add Aml NameUnicodeString APIJeff Brasen2023-09-222-0/+117
| | | | | | | | Add API to generate a Name that contains a Unicode string buffer. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add support to add Strings to packageJeff Brasen2023-09-222-0/+101
| | | | | | | Add API to add a String to a package created with NamedPackage API. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add support for simple method invocation.Jeff Brasen2023-09-222-0/+292
| | | | | | | | Add support to add Return objects via AML that pass a single integer argument to the named method. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add ThermalZone CodeGen functionJeff Brasen2023-09-222-0/+144
| | | | | | | | Add API to generate a ThermalZone object to AmlLib. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg/Bus/Pci/UhciDxe: Fix FORWARD_NULL Coverity issuesRanbir Singh2023-09-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | The function UsbHcGetPciAddressForHostMem has ASSERT ((Block != NULL)); and and the function UsbHcFreeMem has ASSERT (Block != NULL); statement after for loop, but these are applicable only in DEBUG mode. In RELEASE mode, if for whatever reasons there is no match inside for loop and the loop exits because of Block != NULL; condition, then there is no "Block" NULL pointer check afterwards and the code proceeds to do dereferencing "Block" which will lead to CRASH. Hence, for safety add NULL pointer checks always. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4211 Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Co-authored-by: Veeresh Sangolli <veeresh.sangolli@dellteam.com> Signed-off-by: Ranbir Singh <Ranbir.Singh3@Dell.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Bus/Pci/UhciDxe: Fix BAD_SHIFT Coverity issueRanbir Singh2023-09-221-1/+9
| | | | | | | | | | | | | | | | | | | | The function UhciConvertPollRate has a check ASSERT (Interval != 0); but this comes into play only in DEBUG mode. In Release mode, there is no handling if the Interval parameter value is ZERO. To avoid shifting by a negative amount later in the code flow in this undesirable case, it is better to handle it as well by treating it same as if 1 is sent. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4211 Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Co-authored-by: Veeresh Sangolli <veeresh.sangolli@dellteam.com> Signed-off-by: Ranbir Singh <Ranbir.Singh3@Dell.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* RedfishPkg/JsonLib: fix JsonObjectGetValue issueNickle Wang2023-09-222-0/+36
| | | | | | | | | | | | | | | JsonObjectGetValue() cannot find corresponding JSON value when the EDKII_JSON_VALUE object is created by another UEFI driver. This is because "hashtable_seed" is initialized by current time while JsonLib is loaded. So, "hashtable_seed" will be different in each individual UEFI driver. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* RISCV: Fix InternalLongJump to return correct valueAndrei Warkentin2023-09-211-5/+2
| | | | | | | | | | | | | | | InternalLongJump was not returning the 2nd parameter passed to LongJmp (Value) as the return value from SetJmp. Seen with code compiled with -Os, where an LongJmp (Buffer, -1) somehow translated to SetJmp returning 0... Cc: Yong Li <yong.li@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Tuan Phan <tphan@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* ArmPkg/ArmLib: Add ArmHasVhe () helper functionLeif Lindholm2023-09-203-0/+36
| | | | | | | | | | | | | Create a helper function to query whether ID_AA64MFR1_EL1 indicates presence of the Virtualization Host Extensions. This feature is only visible in AARCH64 state. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
* MdeModulePkg/Bus/Pci/NvmExpressPei: Fix DEADCODE Coverity issueRanbir Singh2023-09-201-4/+0
| | | | | | | | | | | | | | | The code can reach line 65 only through the else path above at line 53. The else path already has the same NULL check at line 55 and hence the duplicate code lines are totally redundant which can be deleted. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4220 Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Co-authored-by: Veeresh Sangolli <veeresh.sangolli@dellteam.com> Signed-off-by: Ranbir Singh <Ranbir.Singh3@Dell.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* MdeModulePkg/Bus/Ata/AtaBusDxe: Fix SIGN_EXTENSION Coverity issueRanbir Singh2023-09-201-1/+1
| | | | | | | | | | | | | | | Line number 365 does contain a typecast with UINT32, but it is after all the operations (16-bit left shift followed by OR'ing) are over. To avoid any SIGN_EXTENSION, typecast the intermediate result after 16-bit left shift operation immediately with UINT32. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4209 Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ranbir Singh <Ranbir.Singh3@Dell.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* ArmVirtPkg: handle virtual EL2 timer in DTLeif Lindholm2023-09-197-3/+14
| | | | | | | | | | | | | | | | | | | FEAT_VHE, introduced in ARMv8.1, adds a virtual EL2 timer. However, this library verifies that exactly 3 or 4 12-byte timer interrupts are provided in input DT, ASSERTing when the new timer is added. Change the assert to >= 36. Extend the current logic, also initializing PcdArmArchTimerHypVirtIntrNum if 5 interrupts are provided. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Peter Maydell <peter.maydell@linaro.org>
* ArmPkg: add EL2 virtual timer interrupt PcdLeif Lindholm2023-09-191-0/+1
| | | | | | | | | | | | | | PcdArmArchTimerHypVirtIntrNum, defaults to 28 as defined in Arm's Base System Architecture (current version DEN0094C 1.0C). Relevant for systems implementing FEAT_VHE, added in ARMv8.1. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* RedfishPkg/RedfishRestExDxe: return HTTP status code to caller.Nickle Wang2023-09-192-14/+16
| | | | | | | | | | | | | | | | Return unsupported HTTP status code to caller so caller can handle HTTP error status code. Current implementation only return EFI error to caller. Without knowing the HTTP status code, caller has trouble to handle HTTP request failure. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Acked-by: Mike Maslenkin <mike.maslenkin@gmail.com>
* BaseTools/Plugin: Add DebugMacroCheckMichael Kubacki2023-09-198-0/+2256
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds a plugin that finds debug macro formatting issues. These errors often creep into debug prints in error conditions not frequently executed and make debug more difficult when they are encountered. The code can be as a standalone script which is useful to find problems in a large codebase that has not been checked before or as a build plugin that notifies a developer of an error right away. The script was already used to find numerous issues in edk2 in the past so there's not many code fixes in this change. More details are available in the readme file: .pytool\Plugin\DebugMacroCheck\Readme.md Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* OvmfPkg/PlatformCI: Disable DebugMacroCheckMichael Kubacki2023-09-191-0/+1
| | | | | | | | | | | | Disables the DebugMacroCheck CI plugin to reduce CI checks performed in the package. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* DynamicTablesPkg.ci.yaml: Add debug macro exceptionMichael Kubacki2023-09-191-0/+8
| | | | | | | | | | | | Adds a CI YAML entry to acknowledge a case where custom strings contain print specifiers for a single debug macro. Cc: Sami Mujawar <Sami.Mujawar@arm.com> Cc: Alexei Fedorov <Alexei.Fedorov@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* ArmVirtPkg.ci.yaml: Add debug macro exceptionMichael Kubacki2023-09-191-0/+8
| | | | | | | | | | | | | Adds a CI YAML entry to acknowledge a case where a macro is expanded that contains a print specifier. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* SecurityPkg.ci.yaml: Add debug macro exceptionMichael Kubacki2023-09-191-0/+9
| | | | | | | | | | Adds a CI YAML entry to acknowledge a case where a single argument is matched to a format specifier with a ternary operator. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* pip-requirements.txt: Add regexMichael Kubacki2023-09-191-1/+1
| | | | | | | | | | | | | | regex is a popular PIP module for regular expression support. https://pypi.org/project/regex/ This change adds regex for the upcoming DebugMacroCheck plugin. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* RedfishPkg/PlatformHostInterfaceBmcUsbNicLib: Fix DEBUG macro argsMichael Kubacki2023-09-191-4/+4
| | | | | | | | | | | Some macros added have a mismatched number of print specifiers to arguments. Cc: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Cc: Igor Kulchytskyy <igork@ami.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdeModulePkg: Memory Bin Range Update Accounts for Guard PageTaylor Beebe2023-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | When finding a free page range for allocation, if the found range starts below the tracked memory bin address range, the lowest memory bin address is updated which will not include the guard page if present. When CoreConvertPagesWithGuard() is called on the range being allocated, the memory range is adjusted to include guard pages which can push it out of the memory bin address range and cause the memory type statistics to be unaltered. This patch updates the lowest memory bin address range to account for the guard page if NeedGuard is TRUE so the memory type statistics are updated correctly. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Taylor Beebe <t@taylorbeebe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg/ResetVector: Remove AP waking vector from ResetVectorZhiguang Liu2023-09-182-19/+3
| | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494 Current reset vector uses 0xffffffe0 as AP waking vector, and expects GenFv generates code aligned on a 4k boundary which will jump to this location. However, some issues are listed below 1. GenFV doesn't generate code as the comment expects, because GenFv assumes no modifications are required to the VTF-0 'Volume Top File'. 2. Even if removing VFT0 signature and let GenFv to modify, Genfv is hard-code using another flash address 0xffffffd0. 3. In the same patch series, AP waking vector code is removed from GenFv, because no such usage anymore. The existing of first two issues also approve the usage is not available for a long time. Therefore, remove AP waking vector related code. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* OvmfPkg: Remove applicationProcessorEntryPointZhiguang Liu2023-09-182-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494 Current reset vector uses 0xffffffe0 as AP waking vector, and expects GenFv generates code aligned on a 4k boundary which will jump to this location. However, some issues are listed below 1. GenFV doesn't generate code as the comment expects, because GenFv assumes no modifications are required to the VTF-0 'Volume Top File'. 2. Even if removing VFT0 signature and let GenFv to modify, Genfv is hard-code using another flash address 0xffffffd0. 3. In the same patch series, AP waking vector code is removed from GenFv, because no such usage anymore. The existing of first two issues also approve the usage is not available for a long time. Therefore, remove AP waking vector related code. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien@xen.org> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/SecCore: Remove AP waking Vector logic in SecCoreZhiguang Liu2023-09-181-33/+3
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494 There are two part of AP waking Vector logic in SecCore. The first one working with GenFv to find a free 4K aligned space, use the 4K aligned address as AP waking Vector and jump to 4G-30h, and finally jump to ApStartup.. The second one hard code uses 4G-1000h as AP waking Vector and jump to ApStartup. Both usages are no longer used. Remove them. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* BaseTools: Remove logic to create AP waking vector in GenFvZhiguang Liu2023-09-181-199/+0
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494 Today for SEC core(not VTF-0), GenFv finds free 4K aligned space in FV for AP waking vector and JMP to 4G-30h in the waking vector. There is no usage of this today. Remove the logic to avoid confusing and save spaces in reset vector. Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* OvmfPkg/RiscVVirt/README: document direct kernel bootLaszlo Ersek2023-09-141-1/+32
| | | | | | | | | | | | | | | | | | | Direct (fw_cfg) kernel boot works on the RiscVVirt firmware platform too; I've tested it after extracting the kernel, initrd, and kernel command line from "openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw". Document this type of boot, because at least historically, fw_cfg kernel boot was implemented differently between OVMF and ArmVirtQemu. Thanks: Drew, Sunil. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Andrew Jones <ajones@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine propertyLaszlo Ersek2023-09-141-0/+5
| | | | | | | | | | | | | | | | "acpi=off" is arguably unusual with UEFI guest OSes; add a note to explain it. Original explanation by Drew Jones. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Andrew Jones <ajones@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCGLaszlo Ersek2023-09-141-0/+5
| | | | | | | | | | | | | | | | | Riscv64 KVM services SBI calls internally, so OpenSBI is not used in such setups. Restrict the "-bios" flag accordingly. Thanks: Andrei, Drew. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Andrew Jones <ajones@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: '-bios' is rejected with KVM accel (Drew)] Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* Pyrite support - Secure erase is only available if encryption is supported.Linus Liu2023-09-131-1/+5
| | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3004 Cc: Qi Zhang <qi1.zhang@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tina Chen <tina.chen@intel.com> Cc: Xiao X Chen <xiao.x.chen@intel.com> Signed-off-by: Linus Liu <linus.liu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 11:56:54 +0000