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* ArmPkg/DefaultExceptionHandlerLib ARM: avoid endless loop in RELEASE buildsArd Biesheuvel2018-12-191-0/+2
| | | | | | | | | | | | | Ensure that we prevent the CPU from proceeding after having taken an unhandled exception on a RELEASE build, which does not contain the ASSERT() which ensures this on DEBUG and NOOPT builds. Retain the code following the deadloop so that we can keep going when running in a debugger. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* BaseTools/tools_def ARM: emit PIC veneersArd Biesheuvel2018-12-191-1/+1
| | | | | | | | | | | | | | | | | The ARM linker may emit veneers, i.e., trampolines, when ordinary direct relative branches cannot be used, e.g., for Thumb interworking or branch targets that are out of range. Usually, such veneers carry an absolute reference to the branch target, which is problematic for us, since these absolute references are not covered by annotations that are visible to GenFw in the PE/COFF conversion, and so these absolute references are not fixed up by the PE/COFF loader at runtime. So switch to all ARM GNU ld toolchains to position independent veneers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* EmbeddedPkg: remove GdbDebugAgent libraryArd Biesheuvel2018-12-1911-4738/+0
| | | | | | | | | The GdbDebugAgent library is unused and unmaintained, and now it turns out it doesn't build with Clang, so let's just get rid of it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: drop ArmBds remnant Pcds from .decLeif Lindholm2018-12-191-20/+0
| | | | | | | | | | | | | | | | The following Pcds - gArmTokenSpaceGuid.PcdArmLinuxSpinTable - gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment remained defined, without actual users. So get rid of them. One reference to be deleted separately from edk2-platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* BaseTools: Fix GenFds error doesn't break build.Derek Lin2018-12-191-2/+5
| | | | | | | | | Fix a bug because of b3497bad1221704a5dbc5da0b10f42625f1ad2ed. Before the patch, when GenFds fail, the build continue and return success. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Derek Lin <derek.lin2@hpe.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* Vlv2TbltDevicePkg: Remove PcdPeiCoreMaxXXX PCDs' statementStar Zeng2018-12-193-6/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 The codes have been updated to not use PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported, so their statement in platform DSC could be removed. Cc: Zailiang Sun <zailiang.sun@intel.com> Cc: Yi Qian <yi.qian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Zailiang Sun <zailiang.sun@intel.com> Reviewed-by: Yi Qian <yi.qian@intel.com>
* OvmfPkg: Remove PcdPeiCoreMaxXXX PCDs' statementStar Zeng2018-12-193-6/+0
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 The codes have been updated to not use PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported, so their statement in platform DSC could be removed. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien.grall@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPpiSupportedStar Zeng2018-12-195-199/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPpiSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxFvSupportedStar Zeng2018-12-194-24/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update PeiCore to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxFvSupported in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* SecurityPkg Tcg(2)Pei: Remove the using of PcdPeiCoreMaxFvSupportedStar Zeng2018-12-194-46/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update PeiCore to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxFvSupported in Tcg(2)Pei. Cc: Chao Zhang <chao.b.zhang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
* MdeModulePkg PeiCore: Remove the using of PcdPeiCoreMaxPeimPerFvStar Zeng2018-12-194-108/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1405 Background as below. Problem: As static configuration from the PCDs, the binary PeiCore (for example in FSP binary with dispatch mode) could not predict how many FVs, Files or PPIs for different platforms. Burden: Platform developers need configure the PCDs accordingly for different platforms. To solve the problem and remove the burden, we can update code to remove the using of PcdPeiCoreMaxFvSupported, PcdPeiCoreMaxPeimPerFv and PcdPeiCoreMaxPpiSupported by extending buffer dynamically for FV, File and PPI management. This patch removes the using of PcdPeiCoreMaxPeimPerFv in PeiCore. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* BaseTools: Add $(INC)-like support when compiling .nasm filesZhiju.Fan2018-12-191-1/+19
| | | | | | | | | | | | | | | | | | | | current edk2\BaseTools\Conf\build_rule.template, the compile of nasm source files does not have the $(INC) support. The '-I' option only includes the directory of the nasm source file (${s_path}(+)). Hence, it will be impossible for nasm files to include files outside of the nasm source file directory. As a comparison, the compile of both .s and .asm have $(INC) support in their compile commands. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=1085 Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* BaseTools: Update nasm file build rule to support $(INC)zhijufan2018-12-181-1/+2
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1085 Update the build rule to: "$(NASM)" -I${s_path}(+) $(NASM_INC) $(NASM_FLAGS) -o $dst ${d_path}(+)${s_base}.iii Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* ShellPkg/UefiShellDebug1CommandsLib: Remove the unused function CharToUpperShenglei Zhang2018-12-181-28/+0
| | | | | | | | | | | | | | | CharToUpper is an unused function, so it will be removed. https://bugzilla.tianocore.org/show_bug.cgi?id=1399 v2:Update the title. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* BaseTools: Fixed metafile parser issuesFeng, Bob C2018-12-184-31/+34
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1406 This patch is going to fix the regressions that is introduced by commit 2f818ed0fb57d98985d151781a2ce9b8683129ee The internal array for storing the metadata info should be cached so that the meta file is parsed only once in one build. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Fix PcdArray issueFeng, Bob C2018-12-184-23/+99
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1390 1. support hex number for array index 2. support Non-Dynamic Pcd for array data type 3. support {} and {CODE()} for array data type 4. Change GetStructurePcdMaxSize to be a static function since it need to be called in another static function. And this function does not depend on it's class instance. 5. Add unittest for RemoveCComments function and ArrayIndex regular expression. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Philippe Mathieu-Daud? <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmVirtPkg: Remove redundant library instances in ArmVirtQemuKernel.dscFu Siyuan2018-12-182-4/+1
| | | | | | | | | | | | | | | | | Commit 9a67ba261fe9 ("ArmVirtPkg: Replace obsoleted network drivers from platform DSC/FDF") incorrectly added the BaseCryptLib, OpensslLib and IntrinsicLib to "ArmVirtPkg/ArmVirtQemuKernel.dsc", it's redundant and the library instances from "ArmVirt.dsc.inc" is already sufficient. This patch also adjust the order of network drivers in "ArmVirtPkg/ ArmVirtQemuFvMain.fdf.inc" to make it same as the DSC file. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Julien Grall <julien.grall@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/PciBus: Fix system hang when no PCI Option ROM existsRuiyu Ni2018-12-171-4/+6
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1394 When there is no PCI option ROM exists, today's logic still creates virtual BAR for option ROM using Length = 0, Alignment = (-1). It causes the final MEM32 alignment requirement is as big as 0xFFFFFFFF_FFFFFFFF. The patch fixes this issue by only creating virtual BAR for option ROM when there is PCI option ROM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* MdeModulePkg/NonDiscoverablePciDeviceDxe: add missing validationVladimir Olovyannikov2018-12-171-1/+49
| | | | | | | | | | UEFI SCT crashed and failed in NonDiscoverablePciDeviceDxe becase required checks were not performed. Perform parameters validation in NonDiscoverablePciDeviceDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
* ArmPkg: remove redundant _ARM_PLATFORM_FLAGS overridesArd Biesheuvel2018-12-151-3/+0
| | | | | | | | | | Our default is already armv7-a, so no need to rewrite the PLATFORM_FLAGS for that. Also, setting -mfpu=neon is not entirely inappropriate, since NEON is not mandatory under v7. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* BaseTools: Fixed the build fail issue for casesFeng, Bob C2018-12-152-2/+2
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1386 This patch is going to fix the regression issue that is introduced by commit 72a1d77694d51914c0dd6aa97dbfa58634b0a4a5 The issue will happen in the following cases: 1. There is no Pcd value assignment in Dsc file 2. There are duplicate Pcd filed assignment Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Fixed bugs in CopyDict functionFeng, Bob C2018-12-152-2/+4
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1387 This patch is going to fix the regression issue which is introduced by commit bf9e636605188e291d33ab694ff1c5926b6f0800. This patch Remove the CopyDict incorrect usage for non-dict input data. Add a check for CopyDict input. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Fix PcdNvStoreDefaultValueBuffer Value.Feng, Bob C2018-12-152-7/+15
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1385 This patch is going to fix the regression issue that is introduced by commit e6eae3b4c7b9b756263ecec79694de5f1e85b73a and commit 0b6c5954e1d9a17e01eee7d5ef840a5b4790e2e8. PcdNvStoreDefaultValueBuffer value is update to Vpd Info File, but it is not update into a internal cache. This patch will fix this incorrect value in that internal cache. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmVirtPkg/ArmVirt.dsc.inc: define TcpIoLib resolution unconditionallyArd Biesheuvel2018-12-141-2/+0
| | | | | | | | | | | | | Commit 9a67ba261fe9 ("ArmVirtPkg: Replace obsoleted network drivers from platform DSC/FDF") failed to take into account that the now unconditionally included IScsiDxe.inf from NetworkPkg requires a resolution for TcpIoLib. Since specifying such a resolution is harmless for platforms that have no networking enabled, let's just fix things by dropping the conditionals around it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg: Replace obsoleted network drivers from platform DSC/FDF.Fu Siyuan2018-12-144-23/+12
| | | | | | | | | | | | | This patch replaces the MdeModulePkg TCP, PXE and iSCSI driver with those ones in NetworkPkg. These 3 drivers in MdeModulePkg are not being actively maintained and will be removed from edk2 master soon. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Julien Grall <julien.grall@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmVirtPkg/PrePi ARM CLANG35: drop incompatible command line optionArd Biesheuvel2018-12-132-10/+0
| | | | | | | | | | | Drop the -mno-movt command line option override, which is no longer needed, and actually incompatible with versions of Clang before 3.6. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools/tools_def ARM CLANG35: work around -mno-movt option name changeArd Biesheuvel2018-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PE/COFF only has a very limited id space for runtime relocations, and so it defines only a single relocation for movw/movt instruction pairs, which can be combined to load a 32-bit symbol reference into a register. For this to work as expected, these instructions must always appear in the same order and adjacently, and this is something few compilers take into account, unless they target PE/COFF explicitly (and this is not the case for our ELF based toolchains) For Clang 3.6 and later, we can pass the -mno-movt option to suppress movw/movt pairs entirely, which works around the issue. Unfortunately, for Clang 3.5, the option is called differently (-mllvm -arm-use-movt=0) and mutually incompatible between 3.5 and 3.6. Since it is desirable for the CLANG35 toolchain to be usable on newer versions of Clang as well (given that it is the only non-LTO alternative to CLANG38), let's work around this issue in a way that permits versions 3.5 and newer of Clang to be used with the CLANG35 profile. So pass the -mkernel flag instead (and add -Qunused-argument so Clang does not complain about the -mno-unaligned-access in ARM_CC_XIPFLAGS). This also inhibits movw/movt generation, along with some other changes (e.g., long calls) which do affect code generation but not in an undesirable manner. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseMemoryLibOptDxe ARM: add missing function annotationsArd Biesheuvel2018-12-134-0/+8
| | | | | | | | | | | | | | | | | | | | | ARM uses the low order bit of a branch target address to decide in which execution mode (ARM or Thumb) a function needs to be called. In order for this to work across object files, ELF function symbols will have the low bit set if they were emitted in Thumb mode and cleared otherwise. This annotation is only emitted if the ELF symbols are annotated as function, since taking the address of some data symbol (e.g., a literal) should not produce a value with the low bit set, even if it appears in an object file containing Thumb code. This means that all functions coded in assembler must have this function annotation, or they may end up getting called in the wrong mode, crashing the program. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* Maintainers.txt: Change package maintainer and reviewer of CryptoPkg.Ye Ting2018-12-131-1/+2
| | | | | | | | | | Cc: Gang Wei <gang.wei@intel.com> Cc: Jian Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ting Ye <ting.ye@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Gang Wei <gang.wei@intel.com>
* BaseTools/GenFw ARM: don't permit R_ARM_GOT_PREL relocationsArd Biesheuvel2018-12-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently permit R_ARM_GOT_PREL relocations in the ELF32 conversion routines, under the assumption that relative relocations are fine as long as the section layout is the same between ELF and PE/COFF. However, as is the case with any proxy generating relocation, it is up to the linker to emit an entry in the GOT table and populate it with the correct absolute address, which should also be fixed up at PE/COFF load time. Unfortunately, the relocations covering the GOT section are not emitted into the static relocation sections processed by GenFw, but only in the dynamic relocation section as a R_ARM_RELATIVE relocation, and so GenFw fails to emit the correct PE/COFF relocation data for GOT entries. Since GOT indirection is pointless anyway for PE/COFF modules running in UEFI context, let's just drop the references to R_ARM_GOT_PREL from GenFw, resulting in a build time failure rather than a runtime failure if such relocations do occur. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmVirtPkg/PrePiUniCoreRelocatable CLANG38: work around build issuesArd Biesheuvel2018-12-114-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The self-relocating PrePi module that is used by the ArmVirtQemuKernel and ArmVirtXen targets runs the linker in PIE mode so that it emits dynamic relocations into the final image in a way that permits the module to relocate itself into place before calling into the C code. When building these targets using the CLANG38 toolchain, we switch from the BFD to the GOLD linker, which behaves a bit differently when building PIE executables, and insists on emitting GOT indirected symbol references throughout, which means a) that we end up with absolute addresses (which need to be fixed up at load time) for no good reason, and b) we have to add support for handling GOT entries to GenFw if we want to convert them into PE/COFF. So instead, let's emit a shared library. Since the ELF image only serves as the input to GenFw, this does not lead to any loss of functionality, although it does require the -Bsymbolic linker option to be added to ensure that no symbol based dynamic relocations are emitted (which would, e.g., permit lazy binding for shared libraries). So for all other toolchains, the linker option changes are a no-op. Then, we have to convince CLANG38/GOLD that there is no need to refer to symbols via a GOT entry. This is done by forcing hidden visibility for all symbols in all components that make up the PrePi SEC module: this informs the linker that a symbol is never exported or preempted, making it safe to refer to it directly from anywhere in the code, rather than indirectly via a GOT entry. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg/ArmVirtQemuKernel ARM: make some PCD settings apply to ARMArd Biesheuvel2018-12-111-11/+9
| | | | | | | | | | Move some PCD settings outs of the [PcdsFixedAtBuild.AARCH64] block, so that they apply to 32-bit ARM as well. Without this change, the ARM build doesn't work. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* BaseTools/tools_def AARCH64 RELEASE: move GCC49/GGC5 to 4 KB alignmentArd Biesheuvel2018-12-111-12/+14
| | | | | | | | | | | | | | | Since 4 KB section alignment is required when mapping PE/COFF images with strict permissions, update the default section alignment when using GCC49 and GCC5 in RELEASE mode. Note that XIP modules such as SEC, PEIMs or PEI core are not affected by this change, since the override to 32 byte aligment remains in effect. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/FileExplorerLib: avoid packed struct for program dataArd Biesheuvel2018-12-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Struct packing is only necessary for data structures whose in-memory representation is covered by the PI or UEFI specs, and may deviate from the ordinary C rules for alignment. So in case of FileExplorerLib, this applies to the device path struct only, and other structures used to carry program data should not be packed, or we may end up with alignment faults on architectures such as ARM, which don't permit load/store double or multiple instructions to access memory locations that are not 32-bit aligned. E.g., the following call in FileExplorerLibConstructor() InitializeListHead (&gFileExplorerPrivate.FsOptionMenu->Head); which is emitted as follows for 32-bit ARM/Thumb2 by Clang-5.0 3de0: b510 push {r4, lr} 3de2: 4604 mov r4, r0 ... 3de8: e9c4 4400 strd r4, r4, [r4] 3dec: bd10 pop {r4, pc} will perform a double-word store on the first argument, passed in register r0, assuming that the pointer type of the argument is enough to guarantee that the value is suitably aligned. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* ArmPkg/OpteeLib: Add OPTEE_SUCCESS return codeSumit Garg2018-12-111-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* SecurityPkg: Remove dead code and inf redundant definitions.Chen A Chen2018-12-1014-632/+0
| | | | | | | | | | | Fix BZ1065, https://bugzilla.tianocore.org/show_bug.cgi?id=1065. Remove dead code and inf redundant definitions from SecurityPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Zhang Chao B <chao.b.zhang@intel.com> Reviewed-by: Zhang Chao B <chao.b.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Cpuid: Add code to support new definition.Eric Dong2018-12-101-5/+141
| | | | | | | | | | | Add code to support new definitions added in SDM 2018'11 version. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM.Eric Dong2018-12-101-23/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CPUID definition to follow SDM 2018'11 version, changes Include: 1. Add new fields to the existed data structure, impact CPUIDs include: 1. CPUID_THERMAL_POWER_MANAGEMENT 0x06 CPUID_THERMAL_POWER_MANAGEMENT_EAX 2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX 3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX 4. CPUID_EXTENDED_STATE 0x0D CPUID_EXTENDED_STATE_MAIN_LEAF_EAX CPUID_EXTENDED_STATE_SUB_LEAF_ECX 5. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX 6. CPUID_INTEL_SGX 0x12 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX 2. Add new data structures which not existed before, impact CPUID includes: 1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX 3. Remove fields which defined before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX 4. Add new sub leaf which not existed before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 5. Add new CPUIDs which not exist before, new CPUIDs include: 1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* CryptoPkg/IntrinsicLib: add missing BaseLib declarationJian J Wang2018-12-101-0/+1
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=596 BaseLib interfaces are used in this library but not declared in module's inf file. This patch fix this situation to keep inf and its code in consistency. No functionality or interface change are involved. Cc: Qin Long <qin.long@intel.com> Cc: Ting Ye <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
* MdeModulePkg/PciBus: Shadow option ROM after BARs are programmedRuiyu Ni2018-12-104-62/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1376 Today's implementation reuses the 32bit MMIO resource requested by all PCI devices MMIO BARs when shadowing the option ROM. Take a simple example, a system has only one PCI device. It requires 8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation only requests 8MB (max of 4M and 8M) 32bit MMIO from PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range [3GB, 3GB+8MB) is allocated. The 3GB base address is firstly programmed to the option ROM BAR for option ROM shadow. Then the option ROM decoding is turned off and 3GB base address is programmed to the 32bit MMIO BAR. It doesn't cause issues when the device doesn't request too much MMIO. But when the device contains a 64bit MMIO BAR which requests 4GB MMIO and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is allocated for the option ROM. When the option ROM is being shadowed, 64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is given to the 64bit BAR. The range overlaps with the option ROM range which may cause the device malfunction (e.g.: option ROM cannot be read out) when the device has two separate decoders: one for MMIO BAR, the other for option ROM. The patch requests dedicated MEM32 resource for Option ROMs and moves the Option ROM shadow logic after all MMIO BARs are programmed. The MMIO BAR setting to 0 when shadowing Option ROM is also skipped because the MMIO BAR already contains the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* StandaloneMM: Update permissions for Standalone MM drivers memory areaSughosh Ganu2018-12-092-0/+267
| | | | | | | | | | | | | | | | The StandaloneMM image executes in S-EL0 on reference Arm platforms and is deployed by the trusted firmware as BL32 image. Memory for the Standalone MM drivers is marked as RW+XN initially, allowing the drivers to be loaded into the memory. Once loaded, the memory attributes need to be changed to RO+XN for rodata sections and RO+X for code sections. Achieve this through the extra action 'UpdatePeCoffPermissions' to request the privileged firmware in EL3 to update the permissions. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMM: Include the newly added library class for MMU functionsSughosh Ganu2018-12-091-1/+1
| | | | | | | | | | | The MMU functions needed for StandaloneMM image are now exported through a separate library class. Make the corresponding change in the core's entry point inf file so that it references the correct library class for modifying the MMU attributes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMmPkg: Update dependency on PeCoffExtraActionLibAchin Gupta2018-12-091-1/+1
| | | | | | | | | Replace DebugPeCoffExtraActionLib with StandaloneMmExtraActionLib Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMmPkg: Replace dependency on ArmMmuLibAchin Gupta2018-12-091-1/+1
| | | | | | | | | Use StandaloneMmMmuLib instead of ArmMmuLib in StandaloneMmPkg for AArch64 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMmPkg: Zero data structure explicitlyAchin Gupta2018-12-091-1/+2
| | | | | | | | | | | | Introduction of the -mstrict-align flag results in GCC attempting to use memset to zero out the InitMmFoundationSvcArgs structure. In the absence of this C library function, this patch explicitly zeroes this data structure prior to use. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMmPkg: Enforce alignment check for AArch64Achin Gupta2018-12-091-1/+2
| | | | | | | | | | | | On AArch64, Standalone MM during the SEC phase runs in S-EL0 with SCTLR_EL1.A=1. This patch adds the -mstrict-align compiler flag to ensure that the generated code is compliant with the runtime alignment checks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* StandaloneMmPkg: Add missing dependency on PL011UartClockLibAchin Gupta2018-12-091-0/+1
| | | | | | | | | | This patch fixes the dependency PL011UartLib has on PL011UartClockLib by including its implementation path in the StandaloneMm DSC file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Achin Gupta <achin.gupta@arm.com>
* Revert "MdePkg/ProcessorBind.h AARCH64: limit MAX_ADDRESS to 48 bits"Ard Biesheuvel2018-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 82379bf6603274e81604d5a6f6bb14bdde616286. On AArch64, we can only use 48 address bits while running in UEFI, while the GCD and UEFI memory maps may describe up to 52 bits of physical address space. For this reason, MAX_ADDRESS was reduced to 48 bits, to ensure that the firmware does not inadvertently attempt to allocate memory that we cannot access. However, MAX_ADDRESS is used in runtime drivers as well, and runtime drivers may deal with kernel virtual addresses, which have bits [63:48] set. In fact, the OS may be running with 64 KB pages and pass addresses into the runtime services that use up to 52 bits of address space, either with the top bits set or cleared, even if the physical address space does not extend beyond 48 bits. In summary, changing MAX_ADDRESS is a mistake, and needs to be reverted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* BaseTools: Correct CCFLAG for PcdValueInitBobCF2018-12-071-12/+12
| | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1361 This patch is going to correct the CCFlag for building PcdValueInit Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: BobCF <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Customize deepcopy function.BobCF2018-12-075-5/+88
| | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1288 This patch is one of build tool performance improvement series patches. This patch is going to customize the deepcopy function for SkuClass, PcdClassObject and python dictionary. python deepcopy copy everything of a object, but for our current usage we just need to copy the data we care about recursively. By implementing __deepcopy__ for SkuClass, PcdClassObject, we can customize deepcopy function for them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: BobCF <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-19 08:27:25 +0000