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* SecurityPkg: Cache TPM interface type infoZhang, Chao B2018-06-2513-145/+148
| | | | | | | | | | Cache TPM interface type info to avoid excessive interface ID register read Cc: Long Qin <qin.long@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
* FatPkg/FatPei: Add the recognition of recovery capsule on NVME deviceHao Wu2018-06-252-2/+7
| | | | | | | | | | The driver now can recognize the BlockIo2 PPI for NVM Express devices. And support identifying the recovery capsule on those devices. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg: Add GUID for recovery capsule on NVM Express devicesHao Wu2018-06-252-0/+12
| | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/NvmExpressPei: Add the NVME device PEI BlockIo supportHao Wu2018-06-2513-0/+3424
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=256 This commit adds the PEI BlockIo support for NVM Express devices. The driver will consume the EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI for NVM Express host controllers within the system. And then produces the BlockIo(2) PPIs for each controller. The implementation of this driver is currently based on the NVM Express 1.1 Specification, which is available at: http://nvmexpress.org/resources/specifications/ Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Add definitions for EDKII PEI NVME host controller PPIHao Wu2018-06-252-0/+95
| | | | | | | | | | | | | | | | | | | | | | Introduces the below PPI: struct EDKII_NVM_EXPRESS_HOST_CONTROLLER_PPI { EDKII_NVM_EXPRESS_HC_GET_MMIO_BAR GetNvmeHcMmioBar; EDKII_NVM_EXPRESS_HC_GET_DEVICE_PATH GetNvmeHcDevicePath; }; The GetNvmeHcMmioBar service will provide the caller with the MMIO BAR address of each NVMe HC within the system; The GetNvmeHcDevicePath service will provide the caller with the device path information of each NVMe HC. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelFsp2Pkg: SplitFspBin.py to support x64 driversChasel, Chiu2018-06-251-12/+70
| | | | | | | | | | | FSP binary potentially can include X64 drivers to simplify implementation or support new features so update SplitFspBin.py to support x64 image headers. Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* Vlv2TbltDevicePkg: Set SMM Stack size to 16 KBMichael D Kinney2018-06-243-0/+15
| | | | | | | | | | | | Stack overflows were observed at the default SMM stack size of 8 KB. Increase stack size to 16 KB to prevent SMM stack overflows. Cc: David Wei <david.wei@intel.com> Cc: Mang Guo <mang.guo@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
* ArmPkg/ArmScmiDxe: Dynamically allocate buffer for protocol idsGirish Pathak2018-06-223-12/+21
| | | | | | | | | | | | Dynamically allocate the buffer to receive the SCMI protocol list. This makes MAX_PROTOCOLS redundant, so it is removed. It also fixes one minor code alignment issue and removes an unused macro PROTOCOL_MASK. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmScmiDxe: Fix ASSERT error in SCMI DXEGirish Pathak2018-06-222-21/+23
| | | | | | | | | | | | | | | | | | | | | This change fixes a bug in the SCMI DXE which is observed with the upcoming release of the SCP firmware. The PROTOCOL_ID_MASK (0xF) which is used to generate an index in the ProtocolInitFxns is wrong because protocol ids can be anywhere in 0x10 - 15 or 0x80 - FF range. This mask generates the same index for two different protocols e.g. for protocol ids 0x10 and 0x90, which causes duplicate initialization of a protocol resulting in a failure. This change removes the use of PROTOCOL_ID_MASK and instead uses a list of protocol ids and their initialization functions to identify a supported protocol and initialize it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* BaseTools: introduce !error statementYunhua Feng2018-06-224-2/+24
| | | | | | | | | | | | | | The DSC and FDF file can use `!error` statement. The argument of this statement is an error message, it causes build tool to stop at the location where the statement is encountered and error message following the `!error` statement is output as a message. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=701 Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools: Enhance BaseTools supports FeaturePcd usage in VFR fileYonghong Zhu2018-06-221-2/+3
| | | | | | | | | | Bugzilla 348 only fixed FixedAtBuild Pcd type, now this patch also add support for FeaturePcd type. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=348 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: remove the unneeded codeYonghong Zhu2018-06-221-17/+0
| | | | | | | | Do a clean up to remove the unneeded code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead of table baseChris Co2018-06-211-1/+1
| | | | | | | | | | | | | Mva address calculation should use the left-shifted current section index instead of the left-shifted table base address. Using the table base address here has the side-effect of potentially causing an access violation depending on the base address value. Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Christopher Co <christopher.co@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memoryArd Biesheuvel2018-06-212-13/+3
| | | | | | | | | | | | Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contentsArd Biesheuvel2018-06-211-12/+0
| | | | | | | | | | | | | | | | | | | Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by page and section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ShellPkg/comp: return NOT_EQUAL when compared files are differentRuiyu Ni2018-06-211-1/+2
| | | | | | | | | | | Today's implementation returns 0 even when compared files are different. The patch returns 27 (SHELL_NOT_QUAL) in such case to follow the shell spec. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
* SignedCapsulePkg/SystemFirmwareUpdateDxe: Fix ECC issuesDandan Bi2018-06-211-0/+5
| | | | | | | | | | | Make function comments align with functions. Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: Enable SATA Controller PCI mem spaceSami Mujawar2018-06-212-1/+86
| | | | | | | | | | | | | The SATA controller driver crashes while accessing the PCI memory [AHCI Base Registers (ABAR)], as the PCI memory space is not enabled. Enable the PCI memory space access to prevent the SATA Controller driver from crashing. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/NetworkPkg: Checking for NULL pointer before use.Fu Siyuan2018-06-213-3/+9
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sivaraman Nainar <sivaramann@amiindia.co.in> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
* MdeModulePkg/Core: remove SMM check for Heap Guard feature detectionJian J Wang2018-06-191-10/+0
| | | | | | | | | | | | | | | CpuDxe driver is updated to be able to access DXE page table in SMM mode, which means Heap Guard can get correct memory paging attributes in what environment. It's not necessary to exclude SMM from detecting Heap Guard feature support. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/CpuDxe: make register access more readableJian J Wang2018-06-191-15/+29
| | | | | | | | | | | | | | | Update code to use more meaningful constant macro or predefined register structure. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuDxe: allow accessing (DXE) page table in SMM modeJian J Wang2018-06-192-35/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MdePkg/Library/SmmMemoryAllocationLib, used only by DXE_SMM_DRIVER, allows to free memory allocated in DXE (before EndOfDxe). This is done by checking the memory range and calling gBS services to do real operation if the memory to free is out of SMRAM. If some memory related features, like Heap Guard, are enabled, gBS interface will turn to EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), provided by DXE driver UefiCpuPkg/CpuDxe, to change memory paging attributes. This means we have part of DXE code running in SMM mode in certain circumstances. Because page table in SMM mode is different from DXE mode and CpuDxe always uses current registers (CR0, CR3, etc.) to get memory paging attributes, it cannot get the correct attributes of DXE memory in SMM mode from SMM page table. This will cause incorrect memory manipulations, like fail the releasing of Guard pages if Heap Guard is enabled. The solution in this patch is to store the DXE page table information (e.g. value of CR0, CR3 registers, etc.) in a global variable of CpuDxe driver. If CpuDxe detects it's in SMM mode, it will use this global variable to access page table instead of current processor registers. This can avoid retrieving wrong DXE memory paging attributes and changing SMM page table attributes unexpectedly. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors.Eric Dong2018-06-192-8/+16
| | | | | | | | | | | | | | | | | On AMD processors the second SendIpi in the SendInitSipiSipi and SendInitSipiSipiAllExcludingSelf routines is not required, and may cause undesired side-effects during MP initialization. This patch leverages the StandardSignatureIsAuthenticAMD check to exclude the second SendIpi and its associated MicroSecondDelay (200). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.duran@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/IndustryStandard/Ipmi: Use union for bitmap fieldsHao Wu2018-06-195-536/+1076
| | | | | | | | | | | | This commit enhances the bitmap fields defined in the IPMI header files, union types will be used to provide the users with both the individual bitmap access and the whole byte/word access. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/IndustryStandard/Ipmi: Update IPMI header filesHao Wu2018-06-196-60/+789
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=814 This commit updates the IPMI related header files. Cc: Younas Khan <pmdyounaskhan786@gmail.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/AtaAtapiPassThru: Fix VS2010/VS2012 build failureRuiyu Ni2018-06-191-1/+1
| | | | | | | | | The patch doesn't have functionality impact. It is just to make VS2010/VS2012 happy. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* SourceLevelDebugPkg/DebugCommunicationLibUsb: Add endpoint config.Marvin H?user2018-06-192-3/+17
| | | | | | | | | | | | | | | | | | Currently, DebugCommunicationLibUsb uses the hardcoded endpoints 0x82 and 0x01 to communicate with the EHCI Debug Device. These, however, are not standardized and may vary across different hardware. To solve this problem, the endpoints are retrieved from the USB Device Descriptor directly. V2: - Store endpoint data in the USB Debug Port handle structure. V3: - Remove the static endpoint PCDs as requested. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* BaseTools/WorkspaceCommon: Import used BuildToolError messages.Marvin Haeuser2018-06-191-0/+3
| | | | | | | | | | | Commit c14b58614ffb992dfc668966a19becb86614aafc added a few build error message display calls to WorkspaceCommon.py without importing the message resources explicitely. This commit adds imports the missing directives. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* EmbeddedPkg/GdbSerialLib: avoid left shift of negative quantityArd Biesheuvel2018-06-191-5/+5
| | | | | | | | | | | | | | Clang complains about left shifting a negative value being undefined. EmbeddedPkg/Library/GdbSerialLib/GdbSerialLib.c:151:30: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value] OutputData = (UINT8)((~DLAB<<7)|((BreakSet<<6)|((Parity<<3)|((StopBits<<2)| Data)))); Redefine all bit pattern constants as unsigned to work around this. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMtlLib: fix prototype inconsistency in MtlWaitUntilChannelFreeArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | | Align the prototype of ArmMtlLib's MtlWaitUntilChannelFree () with the one in the ArmMtlNullLib implementation (rather than the other way around, since edk2-platforms has a conflicting implementation as well) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* BaseTools/tools_def CLANG35: add NOOPT build targetArd Biesheuvel2018-06-181-2/+4
| | | | | | | | | | | Create the missing NOOPT target for CLANG35 (which is ARM and AARCH64 only), and align it with the other toolchains: NOOPT has optimizations disabled entirely (for source level debugging), and DEBUG is changed from -O0 to -O1, as is the case for CLANG38 as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* Embedded/EmbeddedPkg.dsc: enable NOOPT build targetArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | Enable to NOOPT build target so we can build this package with optimizations disabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmPkg.dsc: enable NOOPT build targetArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | Enable to NOOPT build target so we can build this package with optimizations disabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* BaseTools/tools_def IA32: drop -no-pie linker option for GCC49Ard Biesheuvel2018-06-181-4/+4
| | | | | | | | | | | | | | | | As reported by Liming, GCC 4.9.2 does not support the -no-pie linker option that we added to the GCC49 and GCC5 toolchain profiles in commit c25d3905523a ("BaseTools/tools_def IA32: disable PIE code generation explicitly") to work around issues with recent distro toolchains that enable PIE code generation by default. So rollback the changes for GCC49 but preserve them for GCC5 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm rebootArd Biesheuvel2018-06-153-2/+32
| | | | | | | | | | | | | | Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: call ProcessCapsules() only onceArd Biesheuvel2018-06-152-27/+60
| | | | | | | | | | | | | ARM platforms have no restriction on when a system firmware update capsule can be applied, and so it is not necessary to call ProcessCapsules() twice. So let's drop the first invocation that occurs before EndOfDxe, and rewrite the second call so that all capsule updates will be applied when the console is up and able to provide progress feedback. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* MdeModulePkg/DxeCapsuleLibFmp: pass progress callback only if it worksArd Biesheuvel2018-06-151-3/+10
| | | | | | | | | | | | | If the first call to UpdateImageProgress() fails, there is no point in passing a pointer to it to Fmp->SetImage(), since it is highly unlikely to succeed on any subsequent calls. This permits the FMP implementation to fall back to an alternate means of providing feedback to the user, e.g., via the console. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/CapsuleRuntimeDxe: clean the capsule payload to DRAMArd Biesheuvel2018-06-155-29/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When capsule updates are staged for processing after a warm reboot, they are copied into memory with the MMU and caches enabled. When the capsule PEI gets around to coalescing the capsule, the MMU and caches may still be disabled, and so on architectures where uncached accesses are incoherent with the caches (such as ARM and AARCH64), we need to ensure that the data passed into UpdateCapsule() is written back to main memory before performing the warm reboot. Unfortunately, on ARM, the only type of cache maintenance instructions that are suitable for this purpose operate on virtual addresses only, and given that the UpdateCapsule() prototype includes the physical address of a linked list of scatter/gather data structures that are mapped at an address that is unknown to the firmware (and may not even be mapped at all when UpdateCapsule() is invoked), we can only perform this cache maintenance at boot time. Fortunately, both Windows and Linux only invoke UpdateCapsule() before calling ExitBootServices(), so this is not a problem in practice. In the future, we may propose adding a secure firmware service that permits performing the cache maintenance at OS runtime, in which case this code may be enhanced to call that service if available. For now, we just fail any UpdateCapsule() calls performed at OS runtime on ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* SecurityPkg/SecureBootConfigDxe: Fix invalid NV data issue.Nickle Wang2018-06-151-2/+4
| | | | | | | | | | | Check the return value of HiiGetBrowserData() before calling HiiSetBrowserData(). HiiGetBrowserData() failed to retrieve NV data during action EFI_BROWSER_ACTION_RETRIEVE. If NV data is invalid, stop sending it to form browser. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Nickle Wang <nickle.wang@hpe.com> Signed-off-by: cinnamon shia <cinnamon.shia@hpe.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
* ArmPlatformPkg: Include PL011UartClock LibUdit Kumar2018-06-152-2/+4
| | | | | | | | | This patch gets PL011 baud rate clock from pl011 uart clock lib instead of Pcd. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* BaseTools/BinToPcd: Follow PEP-8 indent of 4 spacesKinney, Michael D2018-06-141-178/+178
| | | | | | | | | | | https://www.python.org/dev/peps/pep-0008/ Cc: Yanyan Sun <yanyan.sun@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools/BinToPcd: Update for Python 3 compatibilityKinney, Michael D2018-06-141-41/+40
| | | | | | | | | | | | | Update to be compatible with both Python 2.x and Python 3.x. Also return error code 1 when an error is detected to support use of this tool in scripts. Cc: Yanyan Sun <yanyan.sun@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools/BinToPcd: --offset must be 8-byte alignedKinney, Michael D2018-06-141-1/+13
| | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=974 https://bugzilla.tianocore.org/show_bug.cgi?id=965 Update help to state that --offset must be 8-byte aligned. Verify that --offset is 8-byte aligned and print an error message if it is not 8-byte aligned. Cc: Yanyan Sun <yanyan.sun@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools/BinToPcd: Clarify error message for --type HIIKinney, Michael D2018-06-141-5/+2
| | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=963 Update error message for --type HII. If either --variable-guid or --variable-name is missing, then print an error message that states that both --variable-guid and --variable-name are required. Cc: Yanyan Sun <yanyan.sun@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools/BinToPcd: Fix typo in error messagesKinney, Michael D2018-06-141-4/+4
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=962 Change "PcdToBin" to "BinToPcd" Cc: Yanyan Sun <yanyan.sun@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* ArmVirtPkg: add QemuRamfbDxeGerd Hoffmann2018-06-143-0/+5
| | | | | | | | | Add QemuRamfbDxe to dsc and fdf files for ArmVirt package. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: add QemuRamfb to platform consoleGerd Hoffmann2018-06-141-0/+51
| | | | | | | | | | Add QemuRamfbDxe device path to the list of platform console devices, so ConSplitter will pick up the device even though it isn't a PCI GPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: add QemuRamfbDxeGerd Hoffmann2018-06-148-0/+459
| | | | | | | | | | | Add a driver for the qemu ramfb display device. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> [lersek@redhat.com: fix INF banner typo] [lersek@redhat.com: make some local variable definitions more idiomatic] Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: add QEMU_RAMFB_GUIDGerd Hoffmann2018-06-142-0/+26
| | | | | | | | | Add GUID header file for the QemuRamfbDxe driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/IncompPciDeviceSupport: Use correct descriptor lengthRuiyu Ni2018-06-141-2/+2
| | | | | | | | | | | Per PI spec, the Length value is the length of the ACPI descriptor in bytes, excluding the first two fields. The patch fixes the code to report the correct descriptor length by excluding 3-byte first two fields. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 16:35:39 +0000