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* IntelFsp2Pkg/SplitFspBin.py: adopt FSP 2.3 specification.Chasel Chiu2021-10-271-22/+44
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3705 FSP 2.3 has updated FSP_INFO_HEADER to support ExtendedImageRevision and SplitFspBin.py needs to support it. Also updated script to display integer value basing on length. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* FmpDevicePkg/FmpDxe: Use new Variable Lock interfaceYang Jie2021-10-264-40/+39
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3655 The code in FmpDevicePkg call the deprecated interface VariableLockRequestToLockc. So I changed the code in FmpDevicePkg using RegisterBasicVariablePolicy, instead of the deprecated interface. Signed-off-by: Yang Jie <jie.yang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Wei6 Xu <wei6.xu@intel.com>
* UefiPayloadPkg: Add SMM support and SMM variable supportGuo Dong2021-10-252-11/+128
| | | | | | | | | | | | Add SMM variable support for universal UEFI payload. By default they are disabled. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add a SMM dispatch moduleGuo Dong2021-10-253-0/+543
| | | | | | | | | | | | | | | | | PCH SMM module would install SMM SW dispatch2 protocol. And it supports to register SMI handlers based on SMI APM interrupt from the bootloader information gSmmRegisterInfoGuid. It is possible to extend bootloader HOB to pass other information to support more SMI sources. If this module is not required by bootloader for some reason, the bootloader could skip this HOB or build a HOB without EOS info. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add a common FVB SMM moduleGuo Dong2021-10-258-0/+1735
| | | | | | | | | | | | | | | | | | | This FVB module is used to initialize NV variable region and provide SMM FVB protocol to read/write SPI variable region. This module consume HOB gNvVariableInfoGuid and depends on FlashDeviceLib for the actual SPI device operate. During FVB initialization, it will initialize the variable region if the variable region is not valid. And it support to write initial variable data from FFS file if it is found. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add FlashDeviceLibGuo Dong2021-10-253-0/+311
| | | | | | | | | | | | This library provides FlashDeviceLib APIs based on SpiFlashLib and consumed by FVB driver. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add SpiFlashLibGuo Dong2021-10-258-0/+1669
| | | | | | | | | | | | | This is a common SPI Flash library used for the Intel platform that supports SPI hardware sequence. This library provides actual SPI flash operation via Intel PCH SPI controller. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add bootloader SMM support moduleGuo Dong2021-10-255-0/+576
| | | | | | | | | | | | | | | | | This module is only used for SMM S3 support for the bootloader that doesn't support SMM. The payload would save SMM rebase info to SMM communication area in normal boot and expect the bootloader in S3 path to rebase the SMM and trigger SMI by writing 0xB2 port with the given value from SMM communication area. The payload SMM handler would get chance to restore some registers in S3 path. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add a common SMM control Runtime DXE moduleGuo Dong2021-10-254-0/+356
| | | | | | | | | | | | | | This module consumes SMM Registers HOB (SMI_GBL_EN and SMI_APM_EN) to install SMM control 2 protocol gEfiSmmControl2ProtocolGuid. The protocol activate() would set SMI_GBL_EN and SMI_APM_EN and trigger SMI by writing to IO port 0xB3 and 0xB2. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg: Add a common SmmAccessDxe moduleGuo Dong2021-10-253-0/+342
| | | | | | | | | | | | | SmmAccessDxe module would consume EFI_SMRAM_HOB_DESCRIPTOR_BLOCK HOB to produce SMM access protocol gEfiSmmAccess2ProtocolGuid (open, close, lock, and GetCapabilities.) Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* OvmfPkg: Enable TDX in ResetVectorMin Xu2021-10-246-0/+286
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME) with a new kind of virutal machines guest called a Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the confidentiality of TD memory contents and the TD's CPU state from other software, including the hosting Virtual-Machine Monitor (VMM), unless explicitly shared by the TD itself. Note: Intel TDX is only available on X64, so the Tdx related changes are in X64 path. In IA32 path, there may be null stub to make the build success. This patch includes below major changes. 1. Ia32/IntelTdx.asm IntelTdx.asm includes below routines used in ResetVector - IsTdx Check if the running system is Tdx guest. - InitTdxWorkarea It initialize the TDX_WORK_AREA. Because it is called by both BSP and APs and to avoid the race condition, only BSP can initialize the WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY is set. - ReloadFlat32 After reset all CPUs in TDX are initialized to 32-bit protected mode. But GDT register is not set. So this routine loads the GDT then jump to Flat 32 protected mode again. - InitTdx This routine wrap above 3 routines together to do Tdx initialization in ResetVector phase. - IsTdxEnabled It is a OneTimeCall to probe if TDX is enabled by checking the CC_WORK_AREA. - CheckTdxFeaturesBeforeBuildPagetables This routine is called to check if it is Non-TDX guest, TDX-Bsp or TDX-APs. Because in TDX guest all the initialization is done by BSP (including the page tables). APs should not build the tables. - TdxPostBuildPageTables It is called after Page Tables are built by BSP. byte[TDX_WORK_AREA_PGTBL_READY] is set by BSP to indicate APs can leave spin and go. 2. Ia32/PageTables64.asm As described above only the TDX BSP build the page tables. So PageTables64.asm is updated to make sure only TDX BSP build the PageTables. TDX APs will skip the page table building and set Cr3 directly. 3. Ia16/ResetVectorVtf0.asm In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). But in Non-Td guest the initial state of CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit real mode, then jump to the corresponding entry point. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Add IntelTdxMetadata.asmMin Xu2021-10-246-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 In TDX when host VMM creates a new guest TD, some initial set of TD-private pages are added using the TDH.MEM.PAGE.ADD function. These pages typically contain Virtual BIOS code and data along with some clear pages for stacks and heap. In the meanwhile, some configuration data need be measured by host VMM. Tdx Metadata is designed for this purpose to indicate host VMM how to do the above tasks. More detailed information of Metadata is in [TDVF] Section 11. Tdx Metadata describes the information about the image for VMM use. For example, the base address and length of the TdHob, Bfv, Cfv, etc. The offset of the Metadata is stored in a GUID-ed structure which is appended in the GUID-ed chain from a fixed GPA (0xffffffd0). In this commit there are 2 new definitions of BFV & CFV. Tdx Virtual Firmware (TDVF) includes one Firmware Volume (FV) known as the Boot Firmware Volume (BFV). The FV format is defined in the UEFI Platform Initialization (PI) spec. BFV includes all TDVF components required during boot. TDVF also include a configuration firmware volume (CFV) that is separated from the BFV. The reason is because the CFV is measured in RTMR, while the BFV is measured in MRTD. In practice BFV is the code part of Ovmf image (OVMF_CODE.fd). CFV is the vars part of Ovmf image (OVMF_VARS.fd). Since AMD SEV has already defined some SEV specific memory region in MEMFD. TDX re-uses some of the memory regions defined by SEV. - MailBox : PcdOvmfSecGhcbBackupBase|PcdOvmfSecGhcbBackupSize - TdHob : PcdOvmfSecGhcbBase|PcdOvmfSecGhcbSize [TDVF] https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-virtual-firmware-design-guide-rev-1.pdf Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Clear WORK_AREA_GUEST_TYPE in Main.asmMin Xu2021-10-242-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Previously WORK_AREA_GUEST_TYPE was cleared in SetCr3ForPageTables64. This is workable for Legacy guest and SEV guest. But it doesn't work after Intel TDX is introduced. It is because all TDX CPUs (BSP and APs) start to run from 0xfffffff0, thus WORK_AREA_GUEST_TYPE will be cleared multi-times if it is TDX guest. So the clearance of WORK_AREA_GUEST_TYPE is moved to Main16 entry point in Main.asm. Note: WORK_AREA_GUEST_TYPE is only defined for ARCH_X64. For Intel TDX, its corresponding entry point is Main32 (which will be introduced in next commit in this patch-set). WORK_AREA_GUEST_TYPE will be cleared there. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Copy Main.asm from UefiCpuPkg to OvmfPkg's ResetVectorMin Xu2021-10-241-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Previously OvmfPkg/ResetVector uses the Main.asm in UefiCpuPkg/ReseteVector/Vtf0. In this Main.asm there is only Main16 entry point. This patch-set is to introduce Intel TDX into Ovmf. Main32 entry point is needed in Main.asm by Intel TDX. To reduce the complexity of Main.asm in UefiCpuPkg, OvmfPkg create its own Main.asm to meet the requirement of Intel TDX. This Main.asm is an unmodified copy (so no functional change) and the actual changes for tdx come as incremental patches. UefiCpuPkg/ResetVector/Vtf0/main.asm -> OvmfPkg/ResetVector/Main.asm Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* ArmPkg: Implement PlatformBootManagerLib for LinuxBootNhi Pham2021-10-234-0/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LinuxBoot is a firmware that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime. It is built-in UEFI image like an application, which is executed at the end of DXE phase. To achieve the LinuxBoot boot flow "SEC->PEI->DXE->BDS->LinuxBoot", today we use the common well-known GUID of UEFI Shell for LinuxBoot payload, so LinuxBoot developers can effortlessly find the UEFI Shell Application and replace it with the LinuxBoot payload without recompiling platform EDK2 (There might be an issue with a few systems that don't have a UEFI Shell). Also, we have a hard requirement to force the BDS to boot into the LinuxBoot as it is essentially required that only the LinuxBoot boot option is permissible and UEFI is an intermediate bootstrap phase. Considering all the above, it is reasonable to just have a new GUID for LinuxBoot and require a LinuxBoot specific BDS implementation. In addition, with making the BDS implementation simpler, we can reduce many DXE drivers which we think it is not necessary for LinuxBoot booting. This patch adds a new PlatformBootManagerLib implementation which registers only the gArmTokenSpaceGuid.PcdLinuxBootFileGuid for LinuxBoot payload as an active boot option. It allows BDS to jump to the LinuxBoot quickly by skipping the UiApp and UEFI Shell. The PlatformBootManagerLib library derived from ArmPkg/Library/PlatformBootManagerLib. Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Acked-by: Moritz Fischer <moritzf@google.com>
* NetworkPkg/HttpBootDxe: make file extension check case-insensitiveLin, Gary (HPS OE-Linux)2021-10-221-3/+3
| | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3694 HttpBootCheckImageType() was using the case-sensitive AsciiStrCmp() to check the file extensions and this could reject the images with upper-case file names. Using the case-insensitive AsciiStriCmp() to avoid the issue. Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Gary Lin <gary.lin@hpe.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
* ShellPkg: Parse I/O APIC and x2APIC structureAbdul Lateef Attar2021-10-211-0/+99
| | | | | | | | | | | Parse and print the below interrupt structures - I/O APIC Structure - Interrupt Source Override Structure - Processor Local x2APIC Structure - Local x2APIC NMI Structure Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* UefiCpuPkg/CpuCacheInfoLib: Add QuickSort function on BaseLibIanX Kuo2021-10-214-6/+2
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 Remove MdeModulePkg dependency Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: IanX Kuo <ianx.kuo@intel.com>
* MdeModulePkg/SortLib: Add QuickSort function on BaseLibIanX Kuo2021-10-212-223/+8
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 Use QuickSort instead of QuickSortWorker Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: IanX Kuo <ianx.kuo@intel.com>
* DynamicTablesPkg: Fix void pointer arithmeticPierre Gondois2021-10-201-1/+1
| | | | | | | | | | | | Building the DynamicTablesPkg with the additional -Wpointer-arith flag triggers the following error: "pointer of type ‘void *’ used in arithmetic [-Werror=pointer-arith]" Cast the void pointer to fix the error. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Fix unitialized variable useMoritz Fischer2021-10-201-1/+1
| | | | | | | | | In the success case we should return EFI_SUCCESS rather than returning a potentially unitialized value of Status. Cc: Sami Mujawar <Sami.Mujawar@arm.com> Cc: Alexei Fedorov <Alexei.Fedorov@arm.com> Signed-off-by: Moritz Fischer <moritzf@google.com>
* UefiCpuPkg: Cpu feature data stored in memory may be migratedLou, Yun2021-10-201-3/+6
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3634 The memory allocated through "PeiAllocatePool" is located in HOB, and in DXE phase, the HOB will be migrated to a different location. After the migration, the data stored in the HOB stays the same, but the address of pointer to the memory(such as the pointers in ACPI_CPU_DATA structure) changes, which may cause "PiSmmCpuDxeSmm" driver can't find the memory(the pointers in ACPI_CPU_DATA structure) that allocated in "PeiRegisterCpuFeaturesLib", so use "PeiAllocatePages" to allocate memory instead. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiPayloadPkg: Fix the build failure for non-universal payloadGuo Dong2021-10-191-2/+2
| | | | | | | | | | | | Applied an old patch which caused non-universal payload build failed since that code was added after the old patch. This patch fixed the build failure. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Fix ECC reported issuesGuo Dong2021-10-1925-99/+98
| | | | | | | | | | | | | | | V2: Fix more header files on #ifdef variable ECC reported some issues on UefiPayloadPkg, this patch fixed most of them except several files including ElfLib\Elf32.h, coreboot.h, CbParseLib.c, etc. It also removed unused functions in ResetSystemLib and Hob.c. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* UefiPayloadPkg: Replace MEMROY_ENTRY by MEMORY_ENTRYGuo Dong2021-10-195-8/+8
| | | | | | | | | | Fixes simple typo, no behavioral change. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* OvmfPkg/AmdSev: update the fdf to use new workarea PCDBrijesh Singh2021-10-191-1/+8
| | | | | | | | | | | | | | | | | | | | | The commit 80e67af9afca added support for the generic work area concept used mainly by the encrypted VMs but missed update the AmdSev package. Fixes: 80e67af9afca ("OvmfPkg: introduce a common work area") Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reported-by: Dov Murik <dovmurik@linux.ibm.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Dov Murik <dovmurik@linux.ibm.com> Tested-by: Dov Murik <dovmurik@linux.ibm.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* Ovmfpkg: update Ia32 build to use new work areaBrijesh Singh2021-10-192-1/+5
| | | | | | | | | | | | | | | | | | | | | | The commit 80e67af9afca added support for the generic work area concept used mainly by the encrypted VMs. In the past, the work area was preliminary used by the SEV-ES VMs. The SEV-ES support is available for the X64 builds only. But now, that work area header contains fields that nonencrypted VMs and SEV VMs can use. They can be built for IA32. So, moving the work area defines outside of X64. Fixes: 80e67af9afca ("OvmfPkg: introduce a common work area") Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* StandaloneMmPkg: Support CLANGPDB buildsMarvin Häuser2021-10-182-3/+18
| | | | | | | | | | | | | Currently, the flag "-fpie" is passed for all builds with a GCC family toolchain, including CLANGPDB. CLANGPDB however does not support this flag as it generates PE/COFF files directly. As the flag is mostly required for ARM-specific self-relocation, drop it for other architectures and document the limitation to enable e.g. X64 CLANGPDB builds of StandaloneMmCore. Signed-off-by: Marvin Häuser <mhaeuser@posteo.de> Acked-by: Shi Steven <steven.shi@intel.com>
* UefiPayloadPkg: Fix the build issue for corebootGuo Dong2021-10-152-3/+5
| | | | | | | | | | | | | V2: Fix GCC build issue. There is typo in previous change caused coreboot build failure. This patch fixed the build issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* ArmPkg/Smbios: Fix max cache size 2 wrong issueMing Huang2021-10-151-1/+1
| | | | | | | | | As SMBIOS spec, bit-31 of maximum cache size 2 should be 1 for 64K granularity. Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Reviewed-by: Rebecca Cran <rebecca@nuviainc.com> Acked-by: Leif Lindholm <leif@nuviainc.com>
* UefiPayloadPkg: Use SECURITY_STUB_ENABLE to control the SecurityStubDxeLiu, Zhiguang2021-10-141-0/+2
| | | | | | | | | | | | | The SecurityStubDxe driver may be provided by platform payload. In UefiPayloadPkg\UefiPayloadPkg.fdf file, SecurityStubDxe should only be included if SECURITY_STUB_ENABLE is TRUE Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* BaseTools: add edk2-test repo to SetupGit.pyHeinrich Schuchardt2021-10-141-1/+4
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3066 The SctPkg is managed in repository https://github.com/tianocore/edk2-test. Make SetupGit.py usable for this repository. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* ArmVirtPkg/VirtioFdtDxe: Relocate VirtioFdtDxe to OvmfPkg/FdtAbner Chang2021-10-149-8/+7
| | | | | | | | | | | | | | | | | | | Relocate VirtioFdtDxe to OvmfPkg/Fdt, this driver is leverage by both ARM and RISC-V archs. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/FdtPciHostBridgeLib: Add RISC-V in the supported arch.Abner Chang2021-10-141-1/+1
| | | | | | | | | | | | | Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* ArmVirtPkg/FdtPciHostBridgeLib: Relocate FdtPciHostBridgeLib to OvmfPkg/FdtAbner Chang2021-10-147-14/+10
| | | | | | | | | | | | | | | | | | | | | Relocate FdtPciHostBridgeLib to OvmfPkg/Fdt, this library is leverage by both ARM and RISC-V archs. Also use PcdPciMmio32Translation and PcdPciMmio64Translation PCDs provided by MdePkg instead of ArmPkg. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Add PcdPciMmio32(64)Translation PCDsAbner Chang2021-10-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | PcdPciMmio32Translation and PcdPciMmio64Translation PCDs are added to MdePkg as the common PCDs for ARM and RSIC-V archs. The one under ArmPkg is removed in the next patch. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/QemuFwCfgLibMmio: Add RISC-V arch supportAbner Chang2021-10-142-4/+5
| | | | | | | | | | | | | | Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* ArmVirtPkg/QemuFwCfgLib: Relocate QemuFwCfgLib to OvmfPkgAbner Chang2021-10-144-4/+3
| | | | | | | | | | | | | | | | | | | | Relocate QemuFwCfgLib to OvmfPkg/Library/QemuFwCfgLib and rename it to QemuFwCfgLibMmio, this library is leverage by both ARM and RISC-V archs. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg/HighMemDxe: Add RISC-V in the supported arch.Abner Chang2021-10-142-2/+4
| | | | | | | | | | | | | | | | Add RISC-V VM in the file header. Add RISC-V to the supported arch. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
* ArmVirtPkg/HighMemDxe: Relocate HighMemDxe to OvmfPkgAbner Chang2021-10-149-9/+8
| | | | | | | | | | | | | | | | | | | Relocate HighMemDxe to OvmfPkg/Fdt, this library is leverage by both ARM and RISC-V archs. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com>
* ArmVirtPkg/FdtPciPcdProducerLib: Relocate PciPcdProducerLib to OvmfPkgAbner Chang2021-10-147-18/+22
| | | | | | | | | | | | | | | | | | | | | Relocate PciPcdProducerLib to OvmfPkg/Fdt, this library is leverage by both ARM and RISC-V archs. Add OvmfPkg/Fdt maintainers in Maintainers.txt Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com>
* ArmPkg: Use PcdPciIoTranslation PCD from MdePkgAbner Chang2021-10-148-10/+9
| | | | | | | | | | | | | | | | | | PcdPciIoTranslation PCD is relocated to MdePkg and leveraged by both ARM and RISC-V arch. This patch removes the one from ArmPkg and address the corresponding changes required for other modules under ArmVirtPkg. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg: Add PcdPciIoTranslation PCDAbner Chang2021-10-141-0/+4
| | | | | | | | | | | | | | | | | | | | | This PCD is moved from ArmPkg that is used to set the base address of PCI MMIO window that provides I/O access. We relocate this PCD because this PCD is common to ARM and RSIC-V arch. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* ArmVirtPkg/FdtClintDxe: Move FdtClientDxe to EmbeddedPkgAbner Chang2021-10-1429-13/+25
| | | | | | | | | | | | | | | | | This is one of the series patches to restructure the location of modules under ArmVirtPkg for RiscVVirtPkg. RiscVVirtPkg leverage FDT Client protocol to parse FDT nodes. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* MdeModulePkg/Core/Dxe: Acquire a lock when iterating gHandleListHua Ma2021-10-144-41/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3680 This patch fixes the following issue: The global variable gHandleList is a linked list. This list is locked when a entry is added or removed from the list, but there is no lock when iterating this list in function CoreValidateHandle(). It can lead to "Handle.c (76): CR has Bad Signature" assertion if the iterated entry in the list is just removed by other task during iterating. Currently some caller functions of CoreValidateHandle() have CoreAcquireProtocolLock(), but some caller functions of CoreValidateHandle() do not CoreAcquireProtocolLock(). Add CoreAcquireProtocolLock() always when CoreValidateHandle() is called, Also, A lock check is added in the CoreValidateHandle(). Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Hua Ma <hua.ma@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Sd: Corrections for Extra.uni filesKonstantin Aladyshev2021-10-143-5/+8
| | | | | | | | | Add correct content to the 'SdDxeExtra.uni' file. Include 'EmmcDxeExtra.uni' and 'SdDxeExtra.uni' files to their appropriate INF files. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiPayloadPkg: Add PCI root bridge info hob support for SBLMa, Maurice2021-10-135-2/+84
| | | | | | | | | | | | | | | | | | | | Current UefiPayloadPkg can suport PCI root bridge info HOB provided by bootloader. For UniversalPayload, bootloader can directly provide this HOB for payload consumption. However, for legacy UEFI payload, it is required to migrate the HOB information from bootloader HOB space to UEFI payload HOB space. This patch added the missing part for the bootloader ParseLib in order to support both legacy and universal UEFI payload. This patch was tested on Slim Bootloader with latest UEFI payload, and it worked as expected. Cc: Ray Ni <ray.ni@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* BaseTools: Change RealPath to AbsPathChen, Christine2021-10-133-6/+6
| | | | | | | | | | | | | | | | Currently the realpath is used when parse modules, which shows the path with a drive letter in build log. In Windows 'subst' comand is used to associates a path with a drive letter, when use the mapped drive letter for build, with realpath function the build log will have different disk letter info which will cause confusion. In this situation, if use adspath function to show the path info, it will keep same letter with the mapped drive letter, which avoids confusion. This patch modifies the realpath to abspath. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.feng@Intel.com>
* MdePkg/BaseLib: Add QuickSort function on BaseLibIanX Kuo2021-10-134-1/+168
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 Add QuickSort function into BaseLib Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: IanX Kuo <ianx.kuo@intel.com>
* CryptoPkg/BaseCryptLib: Eliminate extra buffer copy in Pkcs7Verify()Bob Morgan2021-10-131-5/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3617 Create a read-only openSSL BIO wrapper for the existing input buffer passed to Pkcs7Verify() instead of copying the buffer into an empty writable BIO which causes memory allocations within openSSL. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Bob Morgan <bobm@nvidia.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 06:48:55 +0000