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* OvmfPkg/Bhyve: add USB supportCorvin Köhne2021-07-052-0/+17
| | | | | | | | | | | An USB driver is required to use a keyboard or mouse while installing an OS or while in a bootloader menu like grub when using GPU + USB Passthrough. Reviewed-by: Peter Grehan <grehan@freebsd.org> Acked-by: Rebecca Cran <rebecca@bsdio.com> Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> Message-Id: <20210705110842.14088-1-c.koehne@beckhoff.com>
* UefiPayloadPkg: Fix the build failureGuo Dong2021-07-012-5/+2
| | | | | | | | | | For non-universal payload, HandoffHobTable is used without initialization. This patch fixed this failure. Cc: Benjamin You <benjamin.you@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Signed-off-by: Guo Dong <guo.dong@intel.com>
* Maintainers.txt: Update Maintainers and reviewers for UefiPayloadPkgGuo Dong2021-07-011-2/+3
| | | | | | | | | | | | | | | Add Ray Ni as UefiPayloadPkg Maintainer. Update Maurice Ma and Benjamin You as reviewers to continue support UefiPayloadPkg patch review. Cc: Ray Ni <ray.ni@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Guo Dong <guo.dong@intel.com>
* NetworkPkg: introduce the NETWORK_ISCSI_MD5_ENABLE feature test macroLaszlo Ersek2021-06-303-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the NETWORK_ISCSI_MD5_ENABLE feature test macro for NetworkPkg. When explicitly set to FALSE, remove MD5 from IScsiDxe's CHAP algorithm list. Set NETWORK_ISCSI_MD5_ENABLE to TRUE by default, for compatibility reasons. Not just to minimize the disruption for platforms that currently include IScsiDxe, but also because RFC 7143 mandates MD5 for CHAP, and some vendors' iSCSI targets support MD5 only. With MD5 enabled, IScsiDxe will suggest SHA256, and then fall back to MD5 if the target requests it. With MD5 disabled, IScsiDxe will suggest SHA256, and break off the connection (and session) if the target doesn't support SHA256. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210629163337.14120-7-lersek@redhat.com>
* NetworkPkg/IScsiDxe: support SHA256 in CHAPLaszlo Ersek2021-06-302-1/+14
| | | | | | | | | | | | | | | | | | | Insert a SHA256 CHAP_HASH structure at the start of "mChapHash". Update ISCSI_CHAP_MAX_DIGEST_SIZE to SHA256_DIGEST_SIZE (32). This enables the initiator and the target to negotiate SHA256 for CHAP, in preference to MD5. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Message-Id: <20210629163337.14120-6-lersek@redhat.com>
* NetworkPkg/IScsiDxe: support multiple hash algorithms for CHAPLaszlo Ersek2021-06-304-23/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the "mChapHash" table, containing the hash algorithms supported for CHAP. Hash algos listed at the beginning of the table are preferred by the initiator. In ISCSI_CHAP_STEP_ONE, send such a CHAP_A value that is the comma-separated, ordered list of algorithm identifiers from "mChapHash". Pre-format this value string at driver startup, in the new function IScsiCHAPInitHashList(). (In IScsiCHAPInitHashList(), also enforce that every hash algo's digest size fit into ISCSI_CHAP_MAX_DIGEST_SIZE, as the latter controls the digest, outgoing challenge, and hex *allocations*.) In ISCSI_CHAP_STEP_TWO, allow the target to select one of the offered hash algorithms, and remember the selection for the later steps. For ISCSI_CHAP_STEP_THREE, hash the challenge from the target with the selected hash algo. In ISCSI_CHAP_STEP_THREE, send the correctly sized digest to the target. If the initiator wants mutual authentication, then generate a challenge with as many bytes as the target's digest will have, in ISCSI_CHAP_STEP_FOUR. In ISCSI_CHAP_STEP_FOUR (i.e., when mutual authentication is required by the initiator), verify the target's response (digest) with the selected algorithm. Clear the selected hash algorithm before every login (remember that in IScsiDxe, every login is a leading login). There is no peer-observable change from this patch, as it only reworks the current MD5 support into the new internal representation. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210629163337.14120-5-lersek@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
* NetworkPkg/IScsiDxe: distinguish "maximum" and "selected" CHAP digest sizesLaszlo Ersek2021-06-302-17/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IScsiDxe uses the ISCSI_CHAP_RSP_LEN macro for expressing the size of the digest (16) that it solely supports at this point (MD5). ISCSI_CHAP_RSP_LEN is used for both (a) *allocating* digest-related buffers (binary buffers and hex encodings alike), and (b) *processing* binary digest buffers (comparing them, filling them, reading them). In preparation for adding other hash algorithms, split purpose (a) from purpose (b). For purpose (a) -- buffer allocation --, introduce ISCSI_CHAP_MAX_DIGEST_SIZE. For purpose (b) -- processing --, rely on MD5_DIGEST_SIZE from <BaseCryptLib.h>. Distinguishing these purposes is justified because purpose (b) -- processing -- must depend on the hashing algorithm negotiated between initiator and target, while for purpose (a) -- allocation --, using the maximum supported digest size is suitable. For now, because only MD5 is supported, introduce ISCSI_CHAP_MAX_DIGEST_SIZE *as* MD5_DIGEST_SIZE. Note that the argument for using the digest size as the size of the outgoing challenge (in case mutual authentication is desired by the initiator) remains in place. Because of this, the above two purposes are distinguished for the "ISCSI_CHAP_AUTH_DATA.OutChallenge" field as well. This patch is functionally a no-op, just yet. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Message-Id: <20210629163337.14120-4-lersek@redhat.com>
* NetworkPkg/IScsiDxe: add horizontal whitespace to IScsiCHAP filesLaszlo Ersek2021-06-302-18/+18
| | | | | | | | | | | | | | | | | In the next patches, we'll need more room for various macro and parameter names. For maintaining the current visual alignments, insert some horizontal whitespace in preparation. "git show -b" produces no output for this patch; the patch introduces no functional changes. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Message-Id: <20210629163337.14120-3-lersek@redhat.com>
* NetworkPkg/IScsiDxe: re-set session-level authentication state before loginLaszlo Ersek2021-06-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC 7143 explains that a single iSCSI session may use multiple TCP connections. The first connection established is called the leading connection. The login performed on the leading connection is called the leading login. Before the session is considered full-featured, the leading login must succeed. Further (non-leading) connections can be associated with the session later. (It's unclear to me from RFC 7143 whether the non-leading connections require individual (non-leading) logins as well, but that particular question is irrelevant from the perspective of this patch; see below.) The data model in IScsiDxe exhibits some confusion, regarding connection / session association: - On one hand, the "ISCSI_SESSION.Conns" field is a *set* (it has type LIST_ENTRY), and accordingly, connections can be added to, and removed from, a session, with the IScsiAttatchConnection() and IScsiDetatchConnection() functions. - On the other hand, ISCSI_MAX_CONNS_PER_SESSION has value 1, therefore no session will ever use more than 1 connection at a time (refer to instances of "Session->MaxConnections" in "NetworkPkg/IScsiDxe/IScsiProto.c"). This one-to-many confusion between ISCSI_SESSION and ISCSI_CONNECTION is very visible in the CHAP logic, where the progress of the authentication is maintained *per connection*, in the "ISCSI_CONNECTION.AuthStep" field (with values such as ISCSI_AUTH_INITIAL, ISCSI_CHAP_STEP_ONE, etc), but the *data* for the authentication are maintained *per session*, in the "AuthType" and "AuthData" fields of ISCSI_SESSION. Clearly, this makes no sense if multiple connections are eligible for logging in. Knowing that IScsiDxe uses only one connection per session (put differently: knowing that any connection is a leading connection, and any login is a leading login), there is no functionality bug. But the data model is still broken: "AuthType", "AuthData", and "AuthStep" should be maintained at the *same* level -- be it "session-level" or "(leading) connection-level". Fixing this data model bug is more than what I'm signing up for. However, I do need to add one function, in preparation for multi-hash support: whenever a new login is attempted (put differently: whenever the leading login is re-attempted), which always happens with a fresh connection, the session-level authentication data needs to be rewound to a sane initial state. Introduce the IScsiSessionResetAuthData() function. Call it from the central -- session-level -- IScsiSessionLogin() function, just before the latter calls the -- connection-level -- IScsiConnLogin() function. Right now, do nothing in IScsiSessionResetAuthData(); so functionally speaking, the patch is a no-op. Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3355 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210629163337.14120-2-lersek@redhat.com>
* UefiPayloadPkg/PayloadLoader: Remove assertionRay Ni2021-06-302-2/+0
| | | | | | | | | | | | | | For R_386_RELATIVE and R_X86_64_RELATIVE, today's logic assumes that the content pointed by the Rela->r_offset is 0 but it's not always TRUE. We observed that linker may set the content to Rela->r_addend. The patch removes the assertion. There is no functionality impact for this patch. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com>
* UefiPayloadPkg/PayloadLoader: Fix bug in locating relocation sectionRay Ni2021-06-302-14/+30
| | | | | | | | | | | | | | | | | | | | | Per ELF spec, the DT_REL/DT_RELA tag in dynamic section stores the virtual address of the relocation section. But today's code logic treats it as the section offset and finds the relocation section whose offset equals to DT_REL/DT_RELA. The logic can work when the section offset equals to the section virtual address. But when the ELF is generated from the link script that reserves a sizeof(pe_header) in the file beginning, the section offset doesn't equal to section virtual address. Such logic can not find the relocation section. The patch fixes this bug. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com>
* IntelFsp2Pkg: Add Config Editor tool supportLoo, Tung Lun2021-06-307-293/+7337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3396 This is a GUI interface that can be used by users who would like to change configuration settings directly from the interface without having to modify the source. This tool depends on Python GUI tool kit Tkinter. It runs on both Windows and Linux. The user needs to load the YAML file along with DLT file for a specific board into the ConfigEditor, change the desired configuration values. Finally, generate a new configuration delta file or a config binary blob for the newly changed values to take effect. These will be the inputs to the merge tool or the stitch tool so that new config changes can be merged and stitched into the final configuration blob. This tool also supports binary update directly and display FSP information. It is also backward compatible for BSF file format. Running Configuration Editor: python ConfigEditor.py Co-authored-by: Maurice Ma <maurice.ma@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* MdePkg : Add IPMI Macro and Structure Defintions to resolve build errorsmanickavasakam karpagavinayagam2021-06-302-0/+22
| | | | | | | | | | | | | | | | | Build error reported for missing structures IPMI_SET_BOOT_OPTIONS_RESPONSE, EFI_IPMI_MSG_GET_BMC_EXEC_RSP, macro EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE when using edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg Rename EFI_IPMI_MSG_GET_BMC_EXEC_RSPB, EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT IPMI_BMC_IN_FORCED_UPDATE_MODE Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com> Reviewed-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* OvmfPkg/XenPlatformPei: Relocate shared_info page mappingAnthony PERARD2021-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | Unfortunately, Xen isn't ready to deal with mapping at the top of the physical address space, so we relocate the mapping after the LAPIC location. See this thread about the issue with the mapping: - https://lore.kernel.org/xen-devel/f8c4151a-6dac-d87c-ef46-eb35ada07bd9@suse.com/ The PhysicalAddressIdentityMapping() call isn't going to do anything anymore since everything under 4GB is already mapped, but there is no need to remove the call. Cc: Jan Beulich <JBeulich@suse.com> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20210628132337.46345-1-anthony.perard@citrix.com> Acked-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: replace "CC:" with "Cc:", to pacify PatchCheck.py]
* OvmfPkg/X86QemuLoadImageLib: State fw_cfg dependency in file headerDov Murik2021-06-292-0/+6
| | | | | | | | | | | | | | | | Make it clear that X86QemuLoadImageLib relies on fw_cfg; prepare the ground to add a warning about the incompatibility with boot verification process. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457 Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210628105110.379951-6-dovmurik@linux.ibm.com>
* OvmfPkg/GenericQemuLoadImageLib: Read cmdline from QemuKernelLoaderFsDov Murik2021-06-292-15/+139
| | | | | | | | | | | | | | | | | | Remove the QemuFwCfgLib interface used to read the QEMU cmdline (-append argument) and the initrd size. Instead, use the synthetic filesystem QemuKernelLoaderFs which has three files: "kernel", "initrd", and "cmdline". Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457 Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Message-Id: <20210628105110.379951-5-dovmurik@linux.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* Revert "OvmfPkg/QemuKernelLoaderFsDxe: don't expose kernel command line"Dov Murik2021-06-291-3/+8
| | | | | | | | | | | | | | | | | | | | | | This reverts commit efc52d67e1573ce174d301b52fa1577d552c8441. Manually fixed conflicts in: OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c Note that besides re-exposing the kernel command line as a file in the synthetic filesystem, we also revert back to AllocatePool instead of AllocatePages. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3457 Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210628105110.379951-4-dovmurik@linux.ibm.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/X86QemuLoadImageLib: plug cmdline blob leak on successDov Murik2021-06-291-2/+4
| | | | | | | | | | | | | | | | | | | When QemuLoadKernelImage() ends successfully, the command-line blob is not freed, even though it is not used elsewhere (its content is already copied to KernelLoadedImage->LoadOptions). The memory leak bug was introduced in commit 7c47d89003a6 ("OvmfPkg: implement QEMU loader library for X86 with legacy fallback", 2020-03-05). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com> Reported-by: Laszlo Ersek <lersek@redhat.com> Fixes: 7c47d89003a6f8f7f6f0ce8ca7d3e87c630d14cc Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Message-Id: <20210628105110.379951-3-dovmurik@linux.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/GenericQemuLoadImageLib: plug cmdline blob leak on successDov Murik2021-06-291-2/+4
| | | | | | | | | | | | | | | | | | | When QemuLoadKernelImage() ends successfully, the command-line blob is not freed, even though it is not used elsewhere (its content is already copied to KernelLoadedImage->LoadOptions). The memory leak bug was introduced in commit ddd2be6b0026 ("OvmfPkg: provide a generic implementation of QemuLoadImageLib", 2020-03-05). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com> Reported-by: Laszlo Ersek <lersek@redhat.com> Fixes: ddd2be6b0026abcd0f819b3915fc80c3de81dd62 Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Message-Id: <20210628105110.379951-2-dovmurik@linux.ibm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: MmConfiguration: Added definition of MM Configuration PPIKun Qin2021-06-292-0/+65
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440 MM Configuration PPI was defined in PI Specification since v1.5. This change added definition of such PPI and related GUIDs into MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: MmConfiguration: Move definition of EFI_MM_RESERVED_MMRAM_REGIONKun Qin2021-06-292-16/+16
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440 The definition of EFI_MM_RESERVED_MMRAM_REGION, according to PI Spec 1.5 is also referenced in EFI_PEI_MM_CONFIGURATION_PPI. Defining this structure as is will enforce any potential usage of MM Configuration PPI interface to include <Protocol/MmConfiguration.h>. This change moves this structure definition to PiMultiPhase.h, which is already included by Protocol/MmConfiguration.h through PiMmCis.h. It also paves way for introducing Ppi/MmConfiguration.h with proper dependency. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools GenFw: Add support for RISCV GOT/PLT relocationsSunil V L2021-06-291-6/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 relocations generated by PIE enabled compiler. This also needed changes to R_RISCV_32 and R_RISCV_64 relocations as explained in https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710 Testing: 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. 2) Debian 10.2.0 and booted QEMU virt model. 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Tested-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
* BaseTools: Reset ERRORLEVEL in toolsetup.bat after edk2basetools checkRebecca Cran2021-06-251-0/+2
| | | | | | | | | | | | | | When using the in-source BaseTools, edksetup.bat will exit with an ERRORLEVEL of 1 because the line in toolsetup.bat "%PYTHON_COMMAND% -c "import edk2basetools" >NUL 2>NUL" fails. Ensure ERRORLEVEL is set to 0 when edksetup.bat or toolsetup.bat is successfully run. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: Fix spelling of "overwrite" and "overwriting" in toolset.batRebecca Cran2021-06-251-3/+3
| | | | | | | | | The words "overwrite" and "overwriting" are one word and shouldn't have hyphens. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: Remove check for Split.exe in toolset.batRebecca Cran2021-06-251-1/+0
| | | | | | | | | | Split is now a Python tool, so BaseTools\Bin\Win32\Split.exe no longer exists. Remove the check for it from toolsetup.bat to prevent the erroneous claim that the binary C tools are missing. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiPayloadPkg: consume the BootManagerMenuFile HOBduntan2021-06-243-2/+57
| | | | | | | | | | | Consume the BootManagerMenuFile HOB in PlatformBootManagerLib This Lib is in UefiPayloadPkg Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: DunTan <dun.tan@intel.com>
* UefiPayloadPkg: Add new structure for BootManagerMenuFile HOBduntan2021-06-242-0/+30
| | | | | | | | | | Add new structure for BootManagerMenuFile HOB in UefiPayloadPkg Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: DunTan <dun.tan@intel.com>
* UefiPayloadPkg: Add PcdResetOnMemoryTypeInformationChange in UefiPayloadPkgZhiguang Liu2021-06-241-0/+1
| | | | | | | | | | This PCD will be consumed by Universal Payload Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Add PcdInstallAcpiSdtProtocol feature in UefiPayloadPkgZhiguang Liu2021-06-241-0/+2
| | | | | | | | | | To install ACPI SDT protocol, define PcdInstallAcpiSdtProtocol as TRUE. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Add macro to enable and disable some driversZhiguang Liu2021-06-242-1/+14
| | | | | | | | | | | Add macro EMU_VARIABLE_ENABLE and DISABLE_RESET_SYSTEM to include or exclude some drivers from Payload Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Remove assert when reserve MMIO/IO resource for devicesZhiguang Liu2021-06-241-9/+11
| | | | | | | | | | | Some boot loader may already reserve MMIO/IO resource for IOAPIC and HPET, so remove the assert when reserve MMIO/IO resource for IOAPIC and HPET Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Include UniversalPayLoad modules in UefiPayloadPkg.dscZhiguang Liu2021-06-242-5/+20
| | | | | | | | | | Add a new macro "UNIVERSAL_PAYLOAD" to build Universal Payload. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Fix up UPL Pcd databaseZhiguang Liu2021-06-246-7/+119
| | | | | | | | | | | | | | | Edk2 bootloader will pass the pei pcd database, and UPL also contain a PCD database. Dxe PCD driver has the assumption that the two PCD database can be catenated and the local token number should be successive。 This patch will manually fix up the UPL PCD database to meet that assumption. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Get and enter DxeCore for Universal PayloadZhiguang Liu2021-06-245-4/+104
| | | | | | | | | | | | | From gUniversalPayloadExtraDataGuid Guid Hob, get the Dxe FV information, and get the Dxe Core from the FV. Also, make sure if there are muliple FV hob, the FV hob pointing to this FV will be the first in the hob list. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Create separate Payload Entry for UniversalPayloadZhiguang Liu2021-06-242-0/+402
| | | | | | | | | | | | | | This patch create the UniversalPayload Entry based on the UefiPayload Entry. It implements the logic to find a proper memory range to create the new Hob and migrate the Hobs from Bootloader. To make the change history clear, the logic to get the DxeCore will be in the next patch. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Update the function definition of HobConstructorZhiguang Liu2021-06-243-25/+22
| | | | | | | | | | | Update the function defination of HobConstructor to align the Phit Hob structure. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Add a separate PlatformHookLib for Universal PayloadZhiguang Liu2021-06-242-0/+123
| | | | | | | | | | | Add a new separate PlatformHookLib for Universal Payload to consume Guid Hob gUniversalPayloadSerialPortInfoGuid to get serial port information Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdeModulePkg: Add new structure for the Universal Payload Serial Port InfoZhiguang Liu2021-06-242-0/+33
| | | | | | | | | | | | Add Universal Payload Serial Port Info definition header file according to Universal Payload's documentation as below: https://universalpayload.github.io/documentation/ Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Add HobLib for UniversalPayloadZhiguang Liu2021-06-2411-6/+838
| | | | | | | | | | | | | | | | | | | | | | | | | For payload entry, use PayloadEntryHobLib as HobLib and payload entry should initialize hob base. For DxeCore, use new added DxeHobLib as HobLib, and DxeCore will initialize hob base. For Dxe Driver, use new added DxeHobLib as HobLib, and use DxeHobListLib to initialize hob base. Adding a new library DxeHobLib + DxeHobListLib instead of using the DxeHobLib.inf in MdePkg is because the constructor needed be separated from DxeHobLib. If not, when building UefiPayloadPkg, the dependency chain is as below: DebugLib -> SerialPortLib -> PlatformHookLib -> HobLib -> DebugLib Each library has a constructor, and this becomes a constructor circle. To break the circle, separate the constructor from the HobLib as a new DxeHobListLib, which won't depend on DebugLib. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* OvmfPkg/Bhyve: clean up TPM_ENABLE remnantsRebecca Cran2021-06-242-79/+0
| | | | | | | | | | | | | TPM support hasn't been tested and any lines in the .dsc and .fdf files that appear to show support are bogus. Remove them. This fixes https://bugzilla.tianocore.org/show_bug.cgi?id=3354 . Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Message-Id: <20210612204340.52290-1-rebecca@bsdio.com> Reviewed-by: Peter Grehan <grehan@freebsd.org> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* CryptoPkg/BaseCryptLib: Enabled CryptSha512 for Smm/Runtime driversxueshengfeng2021-06-242-5/+5
| | | | | | | | | | | | | | | | | | | | | Intel Platform utility Syscfg/sysfwupdt will trigger SMI to enter BIOS interface. then BIOS invoke EncodePassword in SMM mode to check password. it's need sha384(in CryptSha512.c) in SMM mode. the origin SmmCryptLib.lib size is 1389KB, after changed, the size is 1391KB. the origin RuntimeCryptLib.lib size is 911KB, after changed,the size is 913KB. in SmmCryptLib.inf and RuntimeCryptLib.inf, change CryptSha512NULL.c to CryptSha512.c. https://bugzilla.tianocore.org/show_bug.cgi?id=3423 Signed-off-by: xueshengfeng <xueshengfeng@byosoft.com.cn> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* Azurepipeline: SpellCheck: Enforce Node dependency to use version 14.xKun Qin2021-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445 Per update from Cspell tool, the minimal requirement of Cspell 5.x regarding Node is 12 and above. This has caused multple Cspell failures during CI build validation: "Failed to process "**.c" TypeError: text.matchAll(...) is not a function or its return value is not iterable" This change updates the lowest required node version to 14.x to support Cspell functionalities. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* CryptoPkg: BaseCryptLib: Update Salt length requirement for RSA-PSS scheme.Agrawal, Sachin2021-06-239-13/+21
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3455 Enforce salt length to be equal to digest length for RSA-PSS encoding scheme. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* UefiPayloadPkg/UefiPayloadEntry: Remove 4GB memory WAGuo Dong2021-06-221-5/+0
| | | | | | | | Previous it would hang in CpuDxe if DXE drivers are dispatched above 4GB. Now remove the work around since the fixed in CpuDxe are merged. Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* UefiPayloadPkg/UefiPayloadEntry: Improve bootloader memrange parsingPatrick Rudolph2021-06-222-3/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently several DXE crash due to invalid memory resource settings. The PciHostBridgeDxe which expects the MMCONF and PCI Aperature to be EfiMemoryMappedIO, but currently those regions are (partly) mapped as EfiReservedMemoryType. coreboot and slimbootloader provide an e820 compatible memory map, which doesn't work well with EDK2 as the e820 spec is missing MMIO regions. In e820 'reserved' could either mean "DRAM used by boot firmware" or "MMIO in use and not detectable by OS". Guess Top of lower usable DRAM (TOLUD) by walking the bootloader provided memory ranges. Memory types of RAM, ACPI and ACPI NVS below 4 GiB are used to increment TOLUD and reserved memory ranges touching TOLUD at the base are also assumed to be reserved DRAM, which increment TOLUD. Then mark everything reserved below TOLUD as EfiReservedMemoryType and everything reserved above TOLUD as EfiMemoryMappedIO. This fixes assertions seen in PciHostBridgeDxe. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* ArmVirtPkg: Enable PCIe support for KvmtoolSami Mujawar2021-06-222-3/+43
| | | | | | | | | | PCIe support has been added to the Kvmtool virtual machine manager. Therefore, enable PCIe support for Kvmtool firmware. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
* ArmVirtPkg: Add PCIe host bridge utility lib for ArmVirtPkgSami Mujawar2021-06-222-0/+257
| | | | | | | | | | | | | PCIe support has been added to Kvmtool Virtual Machine Manager. The PCI host bridge utility lib is used to retrieve information about the Root Bridges in a platform. Therefore, add an instance of PciHostBridgeUtilityLib as this is required to enable PCIe support for Kvmtool firmware. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>
* MdeModulePkg/BdsDxe: Update BdsEntry to use Variable PolicyKen Lautner2021-06-223-7/+17
| | | | | | | | | | | | | | Changed BdsEntry.c to use Variable Policy instead of Variable Lock as Variable Lock will be Deprecated eventually Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Kenneth Lautner <kenlautner3@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg/CpuCommonFeaturesLib: Correct the CPU location checkDaoxiang Li2021-06-213-7/+7
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424 Processor location information check needs to updated When Core 0 is disabled. In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in comments to match the correct MSR name. Signed-off-by: Daoxiang Li <daoxiang.li@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.hRebecca Cran2021-06-187-131/+148
| | | | | | | | | | | Many of the cache definitions in ArmLibPrivate.h are being used outside of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them public, and remove the include of ArmLibPrivate.h from files in Universal/Smbios. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 18:08:11 +0000