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* ArmVirtPkg: Reverse inclusion order of MdeLibs.inc and ArmVirt.dsc.incArd Biesheuvel2024-05-243-6/+6
| | | | | | | | | | | | | | | | MdeLibs.inc sets default library class resolutions which are much more general than the ones that might be specified in ArmVirt.dsc.inc. So the latter should be included *after* MdeLibs.inc to ensure that its definitions take precedence. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmVirtPkg: Use dynamic PCD to set the SMCCC conduitArd Biesheuvel2024-05-246-0/+26
| | | | | | | | | | | | | | | | | | | | On ARM systems, whether SMC or HVC instructions need to be used to issue monitor calls is typically dependent on the exception level, but there are also cases where EL1 might use SMC instructions, so there is no hard and fast rule. For ArmVirtQemu, this does depend strictly on the exception level, so set the default to HVC (for EL1 execution) and override it to SMC when booted at EL2. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmVirtPkg/ArmVirtQemu: Permit the use of dynamic PCDs in PEIArd Biesheuvel2024-05-242-6/+2
| | | | | | | | | | | | | | | | Currently, only TPM2 builds enable the PCD PEIM, which is a prerequisite for being able to use dynamic PCDs already at the PEI stage. This facility will be used for other reasons too so move those pieces out of code block that are conditional on TPM2_ENABLE Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseRngLib AARCH64: Remove overzealous ASSERT()Ard Biesheuvel2024-05-241-1/+0
| | | | | | | | | | | | | | | | | | | | | | BaseRngLib on AARCH64 will discover whether or not RNDR instructions are supported, by inspecting the ISAR0 identification register, and setting a global boolean accordingly. This boolean is used in subsequent execution to decide whether or not to issue the instruction. The same discovery code also ASSERT()s that RNDR instructions are implemented, which is unnecessary, and breaks execution on systems that incorporate the library but don't implement the instruction (or fail to expose it to the exception level that the firmware executes at). So drop the ASSERT(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* ArmVirtPkg: Move PcdMonitorConduitHvcFlickdm2024-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This moves the PcdMonitorConduitHvc from PcdsFeatureFlag.Common to PcdsFixedAtBuild.Common This is a follow on to the previous commit: ArmPkg: Allow SMC/HVC monitor conduit to be specified at runtime ArmVirtQemu may execute at EL2, in which case monitor calls are generally made using SMC instructions instead of HVC instructions. Whether or not this is the case can only be decided at runtime, and so the associated PCD needs to be settable at runtime, if the platform definition chooses so. This implies a boolean PCD, given that a feature PCD is build-time configurable only. Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Allow SMC/HVC monitor conduit to be specified at runtimeArd Biesheuvel2024-05-242-6/+6
| | | | | | | | | | | | | | | | | | ArmVirtQemu may execute at EL2, in which case monitor calls are generally made using SMC instructions instead of HVC instructions. Whether or not this is the case can only be decided at runtime, and so the associated PCD needs to be settable at runtime, if the platform definition chooses so. This implies a boolean PCD, given that a feature PCD is build-time configurable only. Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* NetworkPkg: Update the PxeBcDhcp6GoogleTest due to underlying changesDoug Flick2024-05-243-6/+100
| | | | | | | | | | | | | This patch updates the PxeBcDhcp6GoogleTest due to the changes in the underlying code. The changes are as follows: - Random now comes from the RngLib Protocol - The TCP ISN is now generated by the hash function Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
* MdePkg: Add MockHash2 Protocol for testingDoug Flick2024-05-242-0/+94
| | | | | | | | | | | | This commit adds a new MockHash2 protocol to the MdePkg. This allows the unit tests to pick up the new protocol and use it for testing. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Adds Protocol for MockRngDoug Flick2024-05-242-0/+69
| | | | | | | | | | | | This patch adds a protocol for MockRng. This protocol is used to mock the Rng protocol for testing purposes. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MockUefiBootServicesTableLibDoug Flick2024-05-244-0/+180
| | | | | | | | | | | This commit adds a mock library for UefiBootServicesTableLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* NetworkPkg TcpDxe: SECURITY PATCH CVE-2023-45236Doug Flick2024-05-248-49/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4541 REF: https://www.rfc-editor.org/rfc/rfc1948.txt REF: https://www.rfc-editor.org/rfc/rfc6528.txt REF: https://www.rfc-editor.org/rfc/rfc9293.txt Bug Overview: PixieFail Bug #8 CVE-2023-45236 CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:C/C:L/I:N/A:N CWE-200 Exposure of Sensitive Information to an Unauthorized Actor Updates TCP ISN generation to use a cryptographic hash of the connection's identifying parameters and a secret key. This prevents an attacker from guessing the ISN used for some other connection. This is follows the guidance in RFC 1948, RFC 6528, and RFC 9293. RFC: 9293 Section 3.4.1. Initial Sequence Number Selection A TCP implementation MUST use the above type of "clock" for clock- driven selection of initial sequence numbers (MUST-8), and SHOULD generate its initial sequence numbers with the expression: ISN = M + F(localip, localport, remoteip, remoteport, secretkey) where M is the 4 microsecond timer, and F() is a pseudorandom function (PRF) of the connection's identifying parameters ("localip, localport, remoteip, remoteport") and a secret key ("secretkey") (SHLD-1). F() MUST NOT be computable from the outside (MUST-9), or an attacker could still guess at sequence numbers from the ISN used for some other connection. The PRF could be implemented as a cryptographic hash of the concatenation of the TCP connection parameters and some secret data. For discussion of the selection of a specific hash algorithm and management of the secret key data, please see Section 3 of [42]. For each connection there is a send sequence number and a receive sequence number. The initial send sequence number (ISS) is chosen by the data sending TCP peer, and the initial receive sequence number (IRS) is learned during the connection-establishing procedure. For a connection to be established or initialized, the two TCP peers must synchronize on each other's initial sequence numbers. This is done in an exchange of connection-establishing segments carrying a control bit called "SYN" (for synchronize) and the initial sequence numbers. As a shorthand, segments carrying the SYN bit are also called "SYNs". Hence, the solution requires a suitable mechanism for picking an initial sequence number and a slightly involved handshake to exchange the ISNs. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
* NetworkPkg: SECURITY PATCH CVE-2023-45237Doug Flick2024-05-2427-83/+410
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4542 Bug Overview: PixieFail Bug #9 CVE-2023-45237 CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:L/I:N/A:N CWE-338 Use of Cryptographically Weak Pseudo-Random Number Generator (PRNG) Use of a Weak PseudoRandom Number Generator Change Overview: Updates all Instances of NET_RANDOM (NetRandomInitSeed ()) to either > > EFI_STATUS > EFIAPI > PseudoRandomU32 ( > OUT UINT32 *Output > ); > or (depending on the use case) > > EFI_STATUS > EFIAPI > PseudoRandom ( > OUT VOID *Output, > IN UINTN OutputLength > ); > This is because the use of Example: The following code snippet PseudoRandomU32 () function is used: > > UINT32 Random; > > Status = PseudoRandomU32 (&Random); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "%a failed to generate random number: %r\n", __func__, Status)); > return Status; > } > This also introduces a new PCD to enable/disable the use of the secure implementation of algorithms for PseudoRandom () and instead depend on the default implementation. This may be required for some platforms where the UEFI Spec defined algorithms are not available. > > PcdEnforceSecureRngAlgorithms > If the platform does not have any one of the UEFI defined secure RNG algorithms then the driver will assert. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
* SecurityPkg RngDxe: Remove incorrect limitation on GetRngFlickdm2024-05-241-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Removed from gEfiRngAlgorithmRaw an incorrect assumption that Raw cannot return less than 256 bits. The DRNG Algorithms should always use a 256 bit seed as per nist standards however a caller is free to request less than 256 bits. > > // > // When a DRBG is used on the output of a entropy source, > // its security level must be at least 256 bits according to UEFI Spec. > // > if (RNGValueLength < 32) { > return EFI_INVALID_PARAMETER; > } > AARCH64 platforms do not have this limitation and this brings both implementations into alignment with each other and the spec. Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Jiewe Yao <Jiewen.yao@intel.com>
* ArmVirtPkg: Add Hash2DxeCrypto to ArmVirtPkgFlickdm2024-05-243-0/+15
| | | | | | | | | | | | | This patch adds Hash2DxeCrypto to ArmVirtPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmVirtPkg PlatformCI: Support virtio-rng-pciFlickdm2024-05-241-0/+2
| | | | | | | | | | | | | This patch adds "virtio-rng-pci" to the PlatformBuildLib.py This adds Rng services to the guest VM Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Add Hash2DxeCrypto to OvmfPkgDoug Flick2024-05-248-3/+40
| | | | | | | | | | | | | | This patch adds Hash2DxeCrypto to OvmfPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg PlatformCI: Support virtio-rng-pciFlickdm2024-05-241-0/+2
| | | | | | | | | | | | | | This patch adds "virtio-rng-pci" to the PlatformBuildLib.py This adds Rng services to the guest VM Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* EmulatorPkg: Add Hash2DxeCrypto to EmulatorPkgDoug Flick2024-05-242-2/+12
| | | | | | | | | | | This patch adds Hash2DxeCrypto to EmulatorPkg. The Hash2DxeCrypto is used to provide the hashing protocol services. Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* EmulatorPkg: Add RngDxe to EmulatorPkgFlickdm2024-05-242-2/+11
| | | | | | | | | | | This patch adds RngDxe to EmulatorPkg. The RngDxe is used to provide random number generation services to the UEFI firmware. Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* CodeQL: Update from 2.16.1 to 2.17.3Michael Kubacki2024-05-213-9/+9
| | | | | | | | | | | | | | | | | | | | This fixes an issue where the CodeQL queries currently fetched in the pipeline are incompatible with the current executable used. Update to pick up functional and security fixes. See the following comparison for detailed differences: https://github.com/github/codeql-cli-binaries/compare/v2.16.1...v2.17.3 Cc: Bob Feng <bob.c.feng@intel.com> Cc: Joey Vagedes <joey.vagedes@gmail.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Rebecca Cran <rebecca@bsdio.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg: Potential UINT32 overflow in S3 ResumeCountShanmugavel Pakkirisamy2024-05-171-4/+8
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4677 Attacker able to modify physical memory and ResumeCount. System will crash/DoS when ResumeCount reaches its MAX_UINT32. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Pakkirisamy ShanmugavelX <shanmugavelx.pakkirisamy@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2024-05-152-0/+2
| | | | | | | | | | | | | Declare InternalAssertJumpBuffer as EXTERN Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Shun Cheng Liu <adam.liu@tw.synaptics.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg: Add MmUnblockMemoryLib to MdeLibs.dscRay Ni2024-05-101-1/+2
| | | | | | | | | | | | | | | | | | MdeLibs.dsc.inc included some default libraries provided by MdePkg. Platform can include MdeLibs.dsc.inc file to avoid some potential incompatible changes to platform dsc file in future. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* DynamicTablesPkg: Adds integer to the AML package nodeAbdul Lateef Attar2024-05-102-1/+107
| | | | | | | | | | | Adds an AmlAddIntegerToNamedPackage() API to generate AML code, which adds an integer value to the package node. Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: Updated SpcrTable structure for Revision_4praveensankarn2024-05-091-0/+32
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4656 In SPCR table, 4 structure members have been added newly as per SPCR table Revision 4, which has to be added in MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h. Signed-off-by: Praveen Sankar N <praveensankarn@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Felix Polyudov <Felixp@ami.com> Cc: Srinivasan Mani <srinivasanm@ami.com> Cc: Sundaresan S <sundaresans@ami.com> Cc: Rabisha R <rabishar@ami.com>
* OvmfPkg: Use newly defined Unaccepted Memory TypeSachin Ganesh2024-05-085-14/+14
| | | | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg: Update Delayed Dispatch PPI as per PI 1.8 SpecSachin Ganesh2024-05-081-1/+23
| | | | | | | | | | | Added WaitOnEvent() function to EFI_DELAYTED_DISPATCH_PPI. Modified DispatchRegister() parameter list. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Use newly defined Unaccepted Memory TypeSachin Ganesh2024-05-084-69/+24
| | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Define Unaccepted Memory TypeSachin Ganesh2024-05-082-18/+7
| | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new Resource Attributes defined in PI 1.8 SpecSachin Ganesh2024-05-081-0/+2
| | | | | | | | | | | Defined Encrypted and Special Purpose resource attributes as defined in PI 1.8 Specification Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add definition for NVMe Over Fabric Device PathSachin Ganesh2024-05-081-0/+22
| | | | | | | | | | | | In accordance with UEFI 2.10 Specification: Adding definition for NVMe Over Fabric (NVMe-oF) Device Path of Messaging Sub-Type. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg/Library: Support to get processor extended infoJiaxin Wu2024-05-082-4/+4
| | | | | | | | | | | | | | Intel has some features need to use processor extended information under CPU feature InitializeFunc(), so add code to support it: This patch is to add CPU_V2_EXTENDED_TOPOLOGY to get processor extended info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Adding SpiHc DriversBrit Chesley2024-05-081-0/+2
| | | | | | | | | | | | | | Including the SpiHc drivers in MdeModulePkg.dsc Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: SpiHc: SpiHc DriversBrit Chesley2024-05-087-0/+514
| | | | | | | | | | | | | | Added SpiHc DXE and SMM drivers. This code receives bus transactions from the SpiBus layer and passes them onto the SpiHcPlatformLib Platform Initialization Spec 1.7 volume 5 section 18.1.7 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdeModulePkg:BaseSpiHcPlatformLib: Adding NULL lib instanceBrit Chesley2024-05-086-0/+344
| | | | | | | | | | | | | | | | | | Adding NULL SpiHcPlatformLib instance. This library is responsible for handling the low level details of the SPI host controller. Since this is platform specific this library will be dependent on OEM SPI implementation. The SPI host controller layer will utilize this library for SPI bus transactions. Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Adding SpiBus DriversBrit Chesley2024-05-081-0/+2
| | | | | | | | | | | | | | | | Including the SpiBus drivers in MdeModulePkg.dsc Platform Initialization spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Bus/Spi/SpiBus: Adding SpiBus DriversBrit Chesley2024-05-087-0/+1052
| | | | | | | | | | | | | | | | | Added SpiBus DXE and SMM drivers. This code translates SPI requests from the application layer into SPI Bus transactions on the SPI host controller. The code is responsible for checking if the transaction is valid, then setting up the SPI clock and chip select properly before passing the bus transaction to the host controller. Platform Initialization Spec 1.7 volume 5 section 18.1.6 Bugzilla #4753 Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdePkg/SpiConfiguration: Correct the definition spellingAbner Chang2024-05-081-2/+2
| | | | | | | Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove SmBases relocation logicJiaxin Wu2024-05-0811-856/+40
| | | | | | | | | | | | | | | | | | | | | | This patch is to remove legacy SmBase relocation in PiSmmCpuDxeSmm Driver. The responsibility for SmBase relocation has been transferred to the SmmRelocationInit interface, which now handles the following tasks: 1. Relocates the SmBase for each processor. 2. Generates the gSmmBaseHobGuid HOB. As a result of this change, the PiSmmCpuDxeSmm driver's role in SMM environment setup is simplified to: 1. Utilize the gSmmBaseHobGuid to determine the SmBase. 2. Perform the ExecuteFirstSmiInit() to do early SMM initialization. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiPayloadPkg/UefiPayloadPkg.dsc: Include SmmRelocationLibJiaxin Wu2024-05-081-0/+2
| | | | | | | | | | | | | This patch just includes SmmRelocationLib in UefiPayloadPkg. Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* OvmfPkg/PlatformPei: Relocate SmBases in PEI phaseJiaxin Wu2024-05-084-1/+92
| | | | | | | | | | | | | | This patch is to consume SmmRelocationInit for SmBase Relocation. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/SmmCpuFeaturesLib: Check Smbase Relocation is done or notJiaxin Wu2024-05-081-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | Based on gSmmBaseHobGuid: If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. So, this patch check smbase relocation is done or not in SmmCpuFeaturesInitializeProcessor(). With SmmRelocationLib, gSmmBaseHobGuid will be always created. Here this patch just makes the function/logic correct. The SMM Relocation logic can be totally cleaned from the SmmCpuFeaturesLib. But it will happen in the future patch set, this patch does not target to the cleanup work. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg: Refine SmmAccess implementationJiaxin Wu2024-05-088-151/+87
| | | | | | | | | | | | | | | | | | | | This patch refines the SmmAccess implementation: 1. SmramMap will be retrieved from the gEfiSmmSmramMemoryGuid instead of original from the TSEG Memory Base register. 2. Remove the gEfiAcpiVariableGuid creation, thus the DESCRIPTOR_INDEX definition can be also cleaned. 3. The gEfiAcpiVariableGuid HOB is moved to the OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/PlatformInitLib: Create gEfiSmmSmramMemoryGuidJiaxin Wu2024-05-082-40/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the PiSmmCpuDxeSmm driver, SMRAM allocation for SMI handlers and processor Save State areas was traditionally performed using the Smst->AllocatePages() function during the DXE phase. The introduction of SmmRelocationLib changes this process by moving the allocation to the PEI phase, where Smst->AllocatePages() is not accessible. Instead, the allocation is now handled by partitioning the SMRAM based on the information provided by a GUID HOB (identified by gEfiSmmSMramMemoryGuid). This patch is to ensure that OVMF produces the gEfiSmmSMramMemoryGuid HOB, allowing SmmRelocationLib to reserve the necessary memory for SMBASE relocation. More info for the change: 1. The EFI_SMM_SMRAM_MEMORY_GUID HOB, as defined in the PI specification, vol.3, section 5, which is used to describe the SMRAM memory regions supported by the platform. This HOB should be produced during the memory detection phase to align with the PI spec. 2. In addition to the memory reserved for ACPI S3 resume, an increasing number of features require reserving SMRAM for specific purposes, such as SmmRelocation. Other advanced features in Intel platforms also necessitate this. The implementation of these features varies and is entirely dependent on the platform. This is why an increasing number of platforms are adopting the EFI_SMM_SMRAM_MEMORY_GUID HOB for SMRAM description. 3. It is crucial that the SMRAM information remains consistent when retrieved from the platform, whether through the SMM ACCESS PPI/Protocol or the EFI_SMM_SMRAM_MEMORY_GUID HOB. Inconsistencies can lead to unexpected issues, most commonly memory region conflicts. 4. The SMM ACCESS PPI/Protocol can be naturally implemented for general use. The common approach is to utilize the EFI_SMM_SMRAM_MEMORY_GUID HOB. For reference, see the existing implementation in the EDK2 repository at edk2/UefiPayloadPkg/SmmAccessDxe/SmmAccessDxe.inf and edk2-platforms/Silicon/Intel/IntelSiliconPkg/Feature/ SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf. Next patch will refine the OVMF SMM Access to consume the EFI_SMM_SMRAM_MEMORY_GUID HOB. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/SmmRelocationLib: Add library instance for OVMFJiaxin Wu2024-05-0814-0/+1299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are below 2 differences between AMD & OVMF according existing implementation: 1.The mode of the CPU check is different between the AMD & OVMF. OVMF: CpuSaveState->x86.SMMRevId & 0Xffff AMD: LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA 2.Existing SmBase configuration is different between the AMD & OVMF. OVMF: if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) { CpuSaveState->x86.SMBASE = mSmBaseForAllCpus[CpuIndex]; } else { CpuSaveState->x64.SMBASE = mSmBaseForAllCpus[CpuIndex]; } AMD: AmdCpuState->x64.SMBASE = mSmBaseForAllCpus[CpuIndex]; This patch provides the SmmRelocationLib library instance for OVMF to handle the logic difference, and it won't change the existing implementation code logic. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add library instance for AMDJiaxin Wu2024-05-083-0/+186
| | | | | | | | | | | | | | | | | | Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary CpuIndexJiaxin Wu2024-05-085-23/+3
| | | | | | | | | | | This patch is to remove unnecessary CpuIndex. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary global variableJiaxin Wu2024-05-081-56/+32
| | | | | | | | | | | | | | This patch aims on mProcessorInfo global variable, which can be defined as local variable in SmmRelocateBases(). With this patch, no need to allocate the memory for all CPUs to store the Processor Info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Avoid unnecessary memory allocationJiaxin Wu2024-05-081-111/+90
| | | | | | | | | | | | | | | | | Since SMM relocation is performed serially for each CPU, there is no need to allocate buffers for all CPUs to store the SmBase address in mSmBase and the Rebased flag in mRebased. A defined global variable is sufficient. This patch focuses on the mSmBase and mRebased global variables to prevent unnecessary memory allocation for these variables. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Rename global variablesJiaxin Wu2024-05-084-35/+35
| | | | | | | | | | | | | This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 03:30:36 +0000