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* BaseTools GNUmakefile: Remove HOST_ARCH in every tool MakefileLiming Gao2018-02-0618-36/+18
| | | | | | | HOST_ARCH has been moved into the common header.makefile Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* BaseTools GNUmakefile: Move HOST_ARCH detection into common makefileLiming Gao2018-02-061-2/+26
| | | | | | | | With this change, enter single tool directory, make can pass. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* PcAtChipsetPkg: Add PeiAcpiTimerLib to save Frequency in HOBLiming Gao2018-02-067-8/+212
| | | | | | | | | | | | | | | In V2: 1) Update PeiAcpiTimerLib base name to PeiAcpiTimerLib 2) Update PeiAcpiTimerLib to add the missing constructor to enable ACPI IO space 3) Update DxeAcpiTimerLib to cache frequency in constructor. PeiAcpiTimerLib caches PerformanceCounterFrequency in HOB, then Pei and Dxe AcpiTimerLib can share the same PerformanceCounterFrequency. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* SecurityPkg: Support PP version lower than 1.3Zhang, Chao B2018-02-062-8/+30
| | | | | | | | | | | | TCG PP 1.2 & PP 1.3 spec defined different Opcodes. Update code to support both. Cc: Long Qin <qin.long@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Long Qin <qin.long@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
* CorebootPayloadPkg/FbGop: Produces correct PixelsPerScanLineBenjamin You2018-02-051-1/+1
| | | | | | | | | | | | | | | | According to UEFI Spec, EFI_GRAPHICS_OUTPUT_PROTOCOL.Mode->Info-> PixelsPerScanLine may contain padding pixel elements outside the area covered by HorizontalResolution for performance reasons or due to hardware restrictions. CorebootPayloadPkg's FbGop driver doesn't follow this requirement, and produces PixelsPerScanLine simply as HorizontalResolution. This needs to be fixed to reflect the real length of a framebuffer scanline. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/PXE: Add warning message for PXE if failed to read system GUID ↵Fu Siyuan2018-02-051-1/+4
| | | | | | | | | | | | from SMBIOS. Current PXE driver uses zero GUID if failed to get the system GUID from smbios table, and some OS PXE boot may fail in such case. This patch is to add a warning message to inform user that smbios table is missed on the platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
* NetworkPkg: Add warning message for PXE if failed to read system GUID from ↵Fu Siyuan2018-02-052-0/+4
| | | | | | | | | | | | SMBIOS. Current PXE driver uses zero GUID if failed to get the system GUID from smbios table, and some OS PXE boot may fail in such case. This patch is to add a warning message to inform user that smbios table is missed on the platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
* SecurityPkg: Add UNI string for 2 PCDsZhang, Chao B2018-02-051-1/+10
| | | | | | | | | Add prompt & help string for PcdTpm2CurrentIrqNum, PcdTpm2PossibleIrqNumBuf Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* BaseTools: Update Expression.py for VOID* to support L'a' and 'a'Feng, YunhuaX2018-02-042-3/+20
| | | | | | | | | | | | | | | | | | | Original VOID* type support L"string" and "string" format, now we also add support for single quote string that without null terminator. Type VOID* support L'a' and 'a', the value transfer to c style value. L'a' --> {0x61, 0x00} L'ab' --> {0x61, 0x00, 0x62, 0x00} 'a' --> {0x61} 'ab' --> {0x61, 0x62} when the value is L'' or '' that not include any character, tool will report error. Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* BaseTools: StructurePcd array Value support flexible formatFeng, YunhuaX2018-02-041-2/+33
| | | | | | | | | | | | | | | | | if StructurePcd set item value is array, support flexible format like as: gEfiStructuredPcdPkgTokenSpaceGuid.Test.Array | {flexible format} {flexible format} = {L"ABC"} | {L'ABC'} | {"ABC"} | {UINT8(0x10)} | {UINT16(0x10)} | {UINT32(0x10)} | {UINT64(0x10)} | {DEVICE_PATH("PciRoot(0)/Pci(0,0)")} | {GUID(gPcdPkgTokenSpaceGuid)} | {L"ABC", L'ABC', UINT8(0x10)....} Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* MdeModulePkg/SmmCore: Fix hang due to already-freed memory deferenceRuiyu Ni2018-02-031-5/+32
| | | | | | | | | | | | | | | | SmiHandlerUnRegister() validates the DispatchHandle by checking whether the first 32bit matches to a certain signature (SMI_HANDLER_SIGNATURE). But if a caller calls *UnRegister() twice and the memory freed by first call still contains the signature, the second call may hang. The patch fixes this issue by locating the DispatchHandle in all SMI handlers, instead of checking the signature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messagesHao Wu2018-02-021-5/+14
| | | | | | | | | | Refine the debug messages during the verification of microcode to make them more clear. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* BaseTools: Fix make PcdValueCommon.c failure on GCCFeng, YunhuaX2018-02-021-2/+1
| | | | | | | | | | | | | | | | error message: PcdValueCommon.c: In function '__PcdGetPtr': PcdValueCommon.c:315:11: error: variable 'Byte' set but not used [-Werror=unused-but-set-variable] UINT8 Byte; ^ cc1: all warnings being treated as errors Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* MdeModulePkg/Core: fix feature conflict between NX and heap guardJian J Wang2018-02-023-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Considering following scenario (both NX memory protection and heap guard are enabled): 1. Allocate 3 pages. The attributes of adjacent memory pages will be |NOT-PRESENT| present | present | present |NOT-PRESENT| 2. Free the middle page. The attributes of adjacent memory pages should be |NOT-PRESENT| present |NOT-PRESENT| present |NOT-PRESENT| But the NX feature will overwrite the attributes of middle page. So it looks still like below, which is wrong. |NOT-PRESENT| present | PRESENT | present |NOT-PRESENT| The solution is checking the first and/or last page of a memory block to be marked as NX, and skipping them if they are Guard pages. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/Core: fix feature conflict between NX and NULL detectionJian J Wang2018-02-021-4/+18
| | | | | | | | | | | | | | | | If enabled, NX memory protection feature will mark all free memory as NX (non-executable), including page 0. This will overwrite the attributes of page 0 if NULL pointer detection feature is also enabled and then compromise the functionality of it. The solution is skipping the NX attributes setting to page 0 if NULL pointer detection feature is enabled. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg/Core: fix guard page missing issueJian J Wang2018-02-022-12/+11
| | | | | | | | | | | | | | | | | | This issue is a regression one caused by a patch at 425d25699be83c35e12df8470b827d7fbcef3bce That fix didn't take the 0 page to free into account, which still needs to call UnsetGuardPage() even no memory needs to free. The fix is just moving the calling of UnsetGuardPage() to the place right after calling AdjustMemoryF(). Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelFrameworkModule/ThunkKb: ReadKeyStrokeEx always return key stateRuiyu Ni2018-02-012-4/+15
| | | | | | | | | | | | | | Today's implementation only return key state when there is a key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* IntelFrameworkModule/Ps2Kb: ReadKeyStrokeEx always return key stateRuiyu Ni2018-02-013-24/+54
| | | | | | | | | | | | | | Today's implementation only return key state when there is a key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/Ps2Kb: ReadKeyStrokeEx always return key stateRuiyu Ni2018-02-013-24/+54
| | | | | | | | | | | | | | Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/UsbKb: ReadKeyStrokeEx always return key stateRuiyu Ni2018-02-013-48/+77
| | | | | | | | | | | | | | Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/ConSplitter: ReadKeyStrokeEx always return key stateRuiyu Ni2018-02-012-25/+151
| | | | | | | | | | | | | | Today's implementation only return key state when there is key. But when user doesn't press any key, the key state cannot be returned. The patch changes the ReadKeyStrokeEx() to always return the key state even there is no key pressed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/SimpleTextInEx.h: Fix comments alignmentRuiyu Ni2018-02-011-8/+5
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* BaseTools CommonLib: Remove the unnecessary print message in PcdValueCommonLiming Gao2018-02-011-10/+0
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* UefiCpuPkg: Remove the unused file ResetVec.asm16Liming Gao2018-02-011-106/+0
| | | | | | | | ResetVec.nasmb is used. ResetVec.asm16 can be retired. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg SafeIntLib: Update API definition to use the same output nameLiming Gao2018-02-011-6/+6
| | | | | | | | | | In SafeUintnToChar8(), update its output parameter name. Update pui8Result --> Result to match its library implementation Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* BaseTools: Structure Pcd in CommandLine.Feng, Bob C2018-02-017-98/+233
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Support multiple .h fileFeng, Bob C2018-02-014-7/+9
| | | | | | | | | for structure Pcd declaration in DEC file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTool: Enhance error handling.BobCF2018-02-011-49/+67
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTool: Add comments in PcdValueInit.c.Feng, Bob C2018-02-011-4/+6
| | | | | | | | | Add Comments for __FLEXIBLE_SIZE () statement. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: eliminate conditional jump in IA32 SmmStartup()Laszlo Ersek2018-01-311-4/+3
| | | | | | | | | | | | | | | | | | | | | | SMM emulation under both KVM and QEMU (TCG) crashes the guest when the "jz" branch, added in commit d4d87596c11d ("UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's supported", 2018-01-18), is taken. Rework the propagation of CPUID.80000001H:EDX.NX [bit 20] to IA32_EFER.NXE [bit 11] so that no code is executed conditionally. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Ref: http://mid.mail-archive.com/d6fff558-6c4f-9ca6-74a7-e7cd9d007276@redhat.com Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> [lersek@redhat.com: XD -> NX code comment updates from Ray] Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> [lersek@redhat.com: mark QEMU/TCG as well in the commit message]
* UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup()Laszlo Ersek2018-01-311-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmmStartup() executes in SMM, which is very similar to real mode. Add "BITS 16" before it and "BITS 32" after it (just before the @32bit label). Remove the manual 0x66 operand-size override prefixes, for selecting 32-bit operands -- the sizes of our operands trigger NASM to insert the prefixes automatically in almost every spot. The one place where we have to add it back manually is the LGDT instruction. (The 0x67 address-size override prefix is also auto-generated.) This patch causes NASM to generate byte-identical object code (determined by disassembling both the pre-patch and post-patch versions, and comparing the listings), except: > @@ -158,7 +158,7 @@ > 00000142 6689D3 mov ebx,edx > 00000145 66B800000000 mov eax,0x0 > 0000014B 0F22D8 mov cr3,eax > -0000014E 67662E0F0155F6 o32 lgdt [cs:ebp-0xa] > +0000014E 2E66670F0155F6 o32 lgdt [cs:ebp-0xa] > 00000155 66B800000000 mov eax,0x0 > 0000015B 0F22E0 mov cr4,eax > 0000015E 66B9800000C0 mov ecx,0xc0000080 The only difference is the prefix list order, it changes from: - 0x67, 0x66, 0x2E to - 0x2E, 0x66, 0x67 (0x2E is "CS segment override"). Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()Laszlo Ersek2018-01-311-4/+4
| | | | | | | | | | | | | | | | | | | | The gSmmCr3, gSmmCr4, gSmmCr0 and gSmmJmpAddr global variables are used for patching assembly instructions, thus we can't yet remove the DB encodings for those instructions. At least we should add the intended meanings in comments. This patch only changes comments. Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> [lersek@redhat.com: adapt commit msg to ongoing PatchAssembly discussion]
* BaseTools: Update BPDG to support L'' and '' format as VPD Pcd ValueYonghong Zhu2018-01-312-17/+21
| | | | | | | | | Current Pcd value support flexible format, this patch add support for BPDG Tool to support L'' and '' format. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Fix the bug to align VPD PCD based on value typeYonghong Zhu2018-01-311-2/+12
| | | | | | | | | | | Spec required for VOID* VPD Pcd, Ascii string use byte alignment, byte array use 8-byte alignment, unicode string use 2-byte alignment. while when the VPD pcd offset use *, the offset generated in the .map file not follow this rule. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg PiSmmCore: Set ForwardLink to NULL in RemoveOldEntry()Star Zeng2018-01-311-1/+3
| | | | | | | | | | | | | | | | | "Entry->Link.ForwardLink = NULL;" is present in RemoveMemoryMapEntry() for DxeCore, that is correct. "Entry->Link.ForwardLink = NULL;" is absent in RemoveOldEntry() for PiSmmCore, that is incorrect. Without this fix, when FromStack in Entry is TRUE, the "InsertTailList (&mMapStack[mMapDepth].Link, &Entry->Link);" in following calling to CoreFreeMemoryMapStack() will fail as the entry at mMapStack[mMapDepth] actually has been removed from the list. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg ACPI: Correct processor struct of PPTTMing Huang2018-01-311-1/+1
| | | | | | | | | | | The Type field of EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR should be UINT8 as ACPI version 6.2 specification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Enhance parse performance by optimize ValueExpressionExYunhua Feng2018-01-305-178/+183
| | | | | | | | | | | | Optimize ValueExpressionEx function to enhance meta-data file parse performance. Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: allow HC capabilities to be overriddenArd Biesheuvel2018-01-305-47/+157
| | | | | | | | | | | | Invoke the newly introduced SD/MMC override protocol to override the capabilities register after reading it from the device registers, and to call the pre/post host init and reset hooks at the appropriate times. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg: introduce SD/MMC override protocolArd Biesheuvel2018-01-302-0/+100
| | | | | | | | | | | | | | | | | | Many ARM based SoCs have integrated SDHCI controllers, and often, these implementations deviate in subtle ways from the pertinent specifications. On the one hand, these deviations are quite easy to work around, but on the other hand, having a collection of SoC specific workarounds in the generic driver stack is undesirable. So let's introduce an optional SD/MMC override protocol that we can invoke at the appropriate moments in the device initialization. That way, the workaround itself remains platform specific, but we can still use the generic driver stack on such platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com> ​Reviewed-by: Star Zeng <star.zeng@intel.com>
* CorebootPayloadPkg: Use correct BytesPerScanLineArthur Heymans2018-01-301-1/+1
| | | | | | | | | | | | | Fetch BytesPerScanLine from coreboot table to reflect how the actual framebuffer is set up instead of guessing it from the horizontal resolution. This fixes a garbled display when HorizontalResolution * (BitsPerPixel / 8) and pFbInfo->BytesPerScanLine don't match. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Benjamin You <benjamin.you@intel.com>
* BaseTools: Fix indentation in CParser.py fileGary Lin2018-01-302-18/+4
| | | | | | | | | | | Mixing usage of spaces and tabs may confuse the python compiler/interpreter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gary Lin <glin@suse.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
* SecurityPkg: Disable TPM interrupt in DECZhang, Chao B2018-01-301-2/+2
| | | | | | | | | | | Disable TPM interrupt support in DEC by default to keep compatibility Cc: Yao Jiewen <jiewen.yao@intel.com> Cc: Long Qin <qin.long@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
* SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt supportZhang, Chao B2018-01-295-21/+388
| | | | | | | | | | | 1. Expose _CRS, _SRS, _PRS control method to support TPM interrupt 2. Provide 2 PCDs to configure _CRS and _PRS returned data Cc: Yao Jiewen <jiewen.yao@intel.com> Cc: Ronald Aigner <Ronald.Aigner@microsoft.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
* ShellPkg/Level2Command: Use UnicodeCollation in StrinCmpRuiyu Ni2018-01-295-45/+49
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
* ShellPkg/CommandLib: Locate proper UnicodeCollation instanceRuiyu Ni2018-01-292-12/+67
| | | | | | | | | | | | | Original code locates the first UnicodeCollation instance in DXE Core protocol database. It's not correct considering multiple UnicodeCollation instances exist in system. The patch changes logic to find the one that matches the current system language. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com.
* UefiCpuPkg/CpuDxe: remove all code to flush TLB for APsJian J Wang2018-01-291-80/+5
| | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver and let AP flush TLB after woken up. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: force flushing TLB for AP in mwait loop modeJian J Wang2018-01-291-0/+7
| | | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver. Since TLB is always flushed in HLT loop mode, we just need to enforce a TLB flush for mwait loop mode. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: fix AP init issue in 64-bit PEIJian J Wang2018-01-291-4/+5
| | | | | | | | | | | | | | | | | | | | This issue is introduced by a patch at f32bfe6d061420a15bac6083063d227c567e6388 The above patch miss the case of 64-bit PEI, which will link X64/MpFuncs.nasm instead of Ia32/MpFuncs.nasm. For X64/MpFuncs.nasm, ExchangeInfo->ModeHighMemory should be always initialized no matter if separate wakeup buffer is allocated or not. Ia32/MpFuncs.nasm will not need ModeHighMemory during AP init. So the changes made in this patch should not affect the functionality of it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* BeagleBoardPkg: reroute Firmware Vendor Pcd to MdeModulePkgLeif Lindholm2018-01-261-1/+1
| | | | | | | | | | | | Commit f9669f09fb53 ("ArmPlatformPkg: retire obsolete PCDs") got rid of the unfortunate ARM-specific variant of PcdFirmwareVendor. However, BeagleBoard was still using it, so the change broke the build. Fix this by moving BeagleBoard to use the MdeModulePkg one instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* UefiCpuPkg/MpInitLib: Make sure AP uses correct StartupApSignalStar Zeng2018-01-261-0/+9
| | | | | | | | | | | | | | | | Every processor's StartupApSignal is initialized in MpInitLibInitialize() before calling CollectProcessorCount(). When SortApicId() is called from CollectProcessorCount(), AP Index is re-assigned by APIC ID. But SortApicId() forgets to set the correct StartupApSignal when sorting the AP. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 18:41:30 +0000