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* NetworkPkg: Add Wi-Fi Wpa3 support in WifiConnectManagerHeng Luo2022-07-016-33/+119
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3961 Add below Wpa3 support: WPA3-Personal: Ieee80211AkmSuiteSAE = 8 WPA3-Enterprise: Ieee80211AkmSuite8021XSuiteB = 11 Ieee80211AkmSuite8021XSuiteB192 = 12 Wi-Fi CERTIFIED Enhanced Open: Ieee80211AkmSuiteOWE = 18 Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com>
* ArmPkg/Drivers: ArmGicIsInterruptEnabled returns incorrect valueRobbie King2022-07-011-4/+3
| | | | | | | | | | | | | | | | The issue appears to have been introduced by: 41fb5d46 : ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3 The changes to ArmGicIsInterruptEnabled() introduced the error where the Boolean result is assigned to Interrupts, but then the bit position check is performed again (against the computed Boolean result instead of the interrupt mask) during the return statement. Fix removes erroneous test and relies on boolean test made at return. Signed-off-by: Robbie King <robbiek@xsightlabs.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/Acpi62: Add bit definitions to NFIT Platform Capabilities StructureMiki Shindo2022-07-013-0/+12
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3915 This commit adds each capability bit definition for NFIT Platform Capabilities Structure. The type has been added since ACPI Specification Version 6.2A. Signed-off-by: Miki Shindo <miki.shindo@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* OvmfPkg/PlatformCI: add IntelTdxBuild.pyMin Xu2022-07-012-0/+48
| | | | | | | | | | | | | | Add build test for OvmfPkg/IntelTdx Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Min Xu <min.m.xu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* pip-requirements.txt: Update basetools version to 0.1.24Bob Feng2022-06-301-1/+1
| | | | | | | | | | | | | | | | Upgrade the edk2-basetools version from 0.1.17 to 0.1.24 features and bug fixes: 1. Add FMMT Python Tool 2. Remove RVCT support 3. Fix dependency issue in PcdValueInit 4. Output the intermediate library instance when error occurs 5. Ecc: Fix grammar in Ecc error message 6. Fix the GenMake bug for .cpp source file Signed-off-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
* UefiPayloadPkg: Align Attribute value with UPL specGua Guo2022-06-301-0/+1
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3963 Based on UPL spec 2.12.2. Universal Payload Information Section, it defines item "Attribute" on UPLD_INFO_HEADER for Debug build should be "1", and Release build should be "0". Currently, The value of item "Attribute" is always "0" Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* MdePkg/Acpi62: Add type 7 NFIT Platform Capabilities Structure supportMiki Shindo2022-06-293-0/+39
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3915 This commit adds a definition type 7 Platform Capabilities Structure and the struct definition for NFIT Table Structure Types. The type has been added since ACPI Specification Version 6.2A. Signed-off-by: Miki Shindo <miki.shindo@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: Fix the GenMake bug for .cpp source fileFeng, Bob C2022-06-281-1/+2
| | | | | | | | | | | | | Build-rules.txt lists .cc and .cpp as supported file extensions. BaseTools commit 05217d210e introduce a regression issue that ignore the .cc and .cpp file type. This patch is to fix this bug. Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Yuwei Chen<yuwei.chen@intel.com>
* MdeModulePkg/XhciDxe: Add access xHCI Extended Capabilities PointerIan Chiu2022-06-274-16/+296
| | | | | | | | | | | | | | | | | | | | | | | Add support process Port Speed field value of PORTSC according to Supported Protocol Capability (define in xHCI spec 1.1) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914 The value of Port Speed field in PORTSC bit[10:13] (xHCI spec 1.1 section 5.4.8) should be change to use this value to query thru Protocol Speed ID (PSI) (xHCI spec 1.1 section 7.2.1) in xHCI Supported Protocol Capability and return the value according the Protocol Speed ID (PSIV) Dword. With this mechanism may able to detect more kind of Protocol Speed in USB3 and also compatiable with three kind of speed of USB2. Cc: Jenny Huang <jenny.huang@intel.com> Cc: More Shih <more.shih@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ian Chiu <Ian.chiu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* BaseTools/Ecc: Fix grammar in Ecc error messageRebecca Cran2022-06-271-2/+2
| | | | | | Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* Ovmf: Include HardwareInfoLib library classes for IntelTdxNicolas Ojeda Leon2022-06-241-0/+2
| | | | | | | | | | | Include HardwareInfoLib classes in the IntelTdxX64.dsc for this platform to use it during build given that PciHostBridgeUtilityLib depends on it. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* ArmVirtPkg: Include DxeHardwareInfoLib library class in dscNicolas Ojeda Leon2022-06-242-1/+1
| | | | | | | | | | | Include DxeHardwareInfoLib class in the common ArmVirt.dsc.inc so that ArmVirt* platforms use it during build given that PciHostBridgeUtilityLib depends on it. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* UefiPayloadPkg: Backward support with python 3.6KasimX Liu2022-06-241-8/+25
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3960 Currently, UniversalPayloadBuild.py don't have support python3.6, we use python3.6 will encounter f"" failure use the change to fix it to support python3.6/3.7/3.8. Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
* UefiCpuPkg: CpuDxe: Set RW and P Attributes on Split PagesRay Ni2022-06-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A memory range can be submitted for attribute changes which is large enough to not require a page split during the attribute update. Consider the following scenario: 1. An attribute update removed the RW attribute on a range large enough to not require a page split. 2. Later, an attributes update is called to re-add the RW attribute for a subsection of that larger page which requires a split 3. The attribute update logic performs a page split, so now the parent and child pages have matching attributes 4. Then, the attribute update logic changes the child page to have the RW attribute. 5. The child page would then correctly have the RW attribute added but the parent page would still have the RW attribute removed which will cause an improper access violation. The page being split should have loose attributes to accommodate the above case. The split page should always have the attributes set so the lowest level page frame determines the access rights as detailed in 4.10.2.2 of the Intel 64 and IA-32 Architectures Software Developer Manual. Setting the User/Supervisor attribute shouldn't be necessary. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Taylor Beebe <t@taylorbeebe.com>
* ArmPlatformPkg: Add PCD for serial debug port interruptThomas Abraham2022-06-221-0/+1
| | | | | | | | | | | | For Arm platforms that support more that one serial port, one of the serial port can be used for connecting debuggers such as WinDbg. There are PCDs that allow the base address and clock rate to be specified for this debug serial port but not its interrupt number. So add a PCD to specify the interrupt number assigned to the serial debug port controller. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/PciHostBridgeUtilityLib: Initialize RootBridges apertures with specNicolas Ojeda Leon2022-06-222-5/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consume the host-provided specification of PCI host bridges if available. Using the DxeHardwareInfoLib, populate a list of hardware descriptors based on the content of the "hardware-info" fw-cfg file, if provided. In the affirmative case, use the resources and attributes specified by the hypervisor for each Host Bridge to create the RootBridge elements. In Ovmf platforms, the host can provide the specification of non-discoverable hardware resources like PCI host bridges. If the proper fw-cfg file is found, parse the contents provided by the host into a linked list by using the Hardware Info library. Then, using the list of PCI host bridges' descriptions, populate the PCI_ROOT_BRIDGES array with the resources and attributes specified by the host. If the file is not provided or no Host Bridge is found in it, fold back to the legacy method based on pre-defined apertures and rules. In some use cases, the host requires additional control over the hardware resources' configurations in the guest for performance and discoverability reasons. For instance, to disclose information about the PCI hierarchy to the guest so that this can profit from optimized accesses. In this case, the host can decide to describe multiple PCI Host Bridges and provide a specific set of resources (e.g. MMIO apertures) so that the guest uses the values provided. Using the provided values may entitle the guest to added performance, for example by using specific MMIO mappings that can enable peer-to-peer communication across the PCI hierarchy or by allocating memory closer to a device for faster DMA transactions. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* Ovmf/PlatformPei: Use host-provided GPA end if availableNicolas Ojeda Leon2022-06-222-7/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the "hardware-info" item from fw-cfg to extract specifications of PCI host bridges and analyze the 64-bit apertures of them to find out the highest 64-bit MMIO address required which determines the address space required by the guest, and, consequently, the FirstNonAddress used to calculate size of physical addresses. Using the static PeiHardwareInfoLib, read the fw-cfg file of hardware information to extract, one by one, all the host bridges. Find the last 64-bit MMIO address of each host bridge, using the HardwareInfoPciHostBridgeLib API, and compare it to an accumulate value to discover the highest address used, which corresponds to the highest value that must be included in the guest's physical address space. Given that platforms with multiple host bridges may provide the PCI apertures' addresses, the memory detection logic must take into account that, if the host provided the MMIO windows that can and must be used, the guest needs to take those values. Therefore, if the MMIO windows are found in the host-provided fw-cfg file, skip all the logic calculating the physical address size and just use the value provided. Since each PCI host bridge corresponds to an element in the information provided by the host, each of these must be analyzed looking for the highest address used. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* Ovmf/HardwareInfoLib: Add Dxe lib to dynamically parse heterogenous dataNicolas Ojeda Leon2022-06-2211-0/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the Hardware Info library, create the DxeHardwareInfoLib which implements the whole API capable of parsing heterogeneous hardware information. The list-like API grants callers a flexible and common pattern to retrieve the data. Moreover, the initial source is a BLOB which generalizes the host-to-guest transmission mechanism. The Hardware Info library main objective is to provide a way to describe non-discoverable hardware so that the host can share the available resources with the guest in Ovmf platforms. This change features and embraces the main idea behind the library by providing an API that parses a BLOB into a linked list to retrieve hardware data from any source. Additionally, list-like APIs are provided so that the hardware info list can be traversed conveniently. Similarly, the capability is provided to filter results by specific hardware types. However, heterogeneous elements can be added to the list, increasing the flexibility. This way, a single source, for example a fw-cfg file, can be used to describe several instances of multiple types of hardware. This part of the Hardware Info library makes use of dynamic memory and is intended for stages in which memory services are available. A motivation example is the PciHostBridgeLib. This library, part of the PCI driver populates the list of PCI root bridges during DXE stage for future steps to discover the resources under them. The hardware info library can be used to obtain the detailed description of available host bridges, for instance in the form of a fw-cfg file, and parse that information into a dynmaic list that allows, first to verify consistency of the data, and second discover the resources availabe for each root bridge. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* Ovmf/HardwareInfoLib: Create Pei lib to parse directly from fw-cfgNicolas Ojeda Leon2022-06-2214-0/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the HardwareInfoLib API and create the PeiHardwareInfoLib which implements it, specifically for Pei usage, supporting only static accesses to parse data directly from a fw-cfg file. All list-like APIs are implemented as unsupported and only a fw-cfg wrapper to read hardware info elements is provided. The Hardware Info library is intended to describe non-discoverable hardware information and share that from the host to the guest in Ovmf platforms. The QEMU fw-cfg extension for this library provides a first variation to parse hardware info by reading it directly from a fw-cfg file. This library offers a wrapper function to the plain QmeuFwCfgReadBytes which, specifically, parses header-data pairs out of the binary values in the file. For this purpose, the approach is incremental, reading the file block by block and outputting the values only for a specific known hardware type (e.g. PCI host bridges). One element is returned in each call until the end of the file is reached. Considering fw-cfg as the first means to transport hardware info from the host to the guest, this wrapping library offers the possibility to statically, and in steps, read a specific type of hardware info elements out of the file. This method reads one hardware element of a specific type at a time, without the need to pre-allocate memory and read the whole file or dynamically allocate memory for each new element found. As a usage example, the static approach followed by this library enables early UEFI stages to use and read hardware information supplied by the host. For instance, in early times of the PEI stage, hardware information can be parsed out from a fw-cfg file prescinding from memory services, that may not yet be available, and avoiding dynamic memory allocations. Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* OvmfPkg/Library: Create base HardwareInfoLib for PCI Host BridgesNicolas Ojeda Leon2022-06-223-0/+823
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create the Hardware Info library base together with the specifics to describe PCI Host Bridges. The Hardware Info library is intended to be used for disclosing non-discoverable hardware information from the host to the guest in Ovmf platforms. Core functionality will provide the possibility to parse information from a generic BLOB into runtime structures. The library is conceived in a generic way so that further hardware elements can also be described using it. For such purpose the length of the BLOB is not restricted but instead regarded as a sequence of header-info elements that allow the parsing during runtime. The first type of hardware defined will be PCI host bridges, providing the possibility to define multiple and specify the resources each of them can use. This enables the guest firmware to configure PCI resources properly. Having the size of each individual element favors the reuse of a single interface to convey descriptions of an arbitrary number of heterogenous hardware elements. Furthermore, flexible access mechanisms coupled with the size will grant the possibility of interpreting them in a single run. Define the base types of the generic Hardware Info library to parse heterogeneous data. Also provide the specific changes to support PCI host bridges as the first hardware type supported by the library. Additionally, define the HOST_BRIDGE_INFO structure to describe PCI host bridges along with the functionality to parse such information into proper structures used by the PCI driver in a centralized manner and taking care of versioning. As an example and motivation, the library will be used to define multiple PCI host bridges for complex platforms that require it. The first means of transportation that will be used is going to be fw-cfg, over which a stream of bytes will be transferred and later parsed by the hardware info library. Accordingly, the PCI driver will make use of these host bridges definitions to populate the list of Root Bridges and proceed with the configuration and discovery of underlying hardware components. As mentioned before, the binary data to be parsed by the Hardware Info library should be organized as a sequence of Header-element pairs in which the header describes the type and size of the associated element that comes right after it. As an illustration, to provide inforation of 3 host bridges the data, conceptually, would look like this: Header PCI Host Bridge (type and size) # 1 PCI Host Bridge info # 1 Header PCI Host Bridge (type and size) # 2 PCI Host Bridge info # 2 Header PCI Host Bridge (type and size) # 3 PCI Host Bridge info # 3 Cc: Alexander Graf <graf@amazon.de> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Nicolas Ojeda Leon <ncoleon@amazon.com>
* OvmfPkg: reduce the number of dsc include files for tpm libsGerd Hoffmann2022-06-228-41/+18
| | | | | | | | We can have multiple [LibraryClasses] sections, so we can place all TPM-related library configuration to a single include file. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg: Remove overly verbose DEBUG lines in LcdGraphicsBltRebecca Cran2022-06-221-12/+0
| | | | | | | | | | | The DEBUG output in LcdGraphicsBlt is overly verbose, and makes using the console difficult, for example when using the UiApp. Since the extra output should no longer be needed, delete the DEBUG lines. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE registerLuo, Heng2022-06-221-2/+8
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni <ray.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiPayloadPkg: UniversalPayloadBuild.py to support --pcd featureGua Guo2022-06-211-0/+8
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3955 Currently, UPL freezed all PCD and only known UPL hob can hook DXE Drivers behavior, add optional feature on UniversalPayloadBuild.py to have another way to hook PCD value. Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: : Ray Ni <ray.ni@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* UefiPayloadPkg: Always split page table entry to 4K if it covers stack.Liu, Zhiguang2022-06-201-10/+2
| | | | | | | | | | | | | | | | | | | | | | | We observed page fault in the following situation: 1.PayloadEntry uses 2M entry in page table to cover DXE stack range. 2.In DXE phase, image protection code needs to mark some sub-range in this 2M entry as readonly. So the the 2M page table entry is split to 512 4K entries, and some of the entries are marked as readonly. (the entries covering stack still remain R/W) 3.Page fault exception happens when trying to access stack. Always split the page table entry to 4K if it covers stack to avoid this issue. More discussion about this issue can be seen at below link https://edk2.groups.io/g/devel/topic/91446026 Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Increase the PcdMaximumUnicodeStringLengthXie, Yuanhao2022-06-171-0/+1
| | | | | | | | | | | | | | The maximum Unicode string could be as large as 1800000 in certain platforms when HII code builds the configuration strings. This causes assertion in PrintLib. The patch increases the PcdMaximumUnicodeStringLength to 1800000 to avoid the assertion. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com>
* BaseTools: output the intermediate library instance when error occursNi, Ray2022-06-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a module "Module" depends on a library instance "Lib1" which depends on "Lib2" which depends on "Lib3" ... depends on "LibN", but "LibN" doesn't support the type (e.g.: SEC) of the "Module", the following error messages are printed by build tool: <DSC path>(...): error 1001: Module by library instance [<LibN path>] consumed by [<Module path>] But it's unclear to user how LibN is consumed by the Module. With the patch, following errors are printed: <DSC path>(...): error 1001: Module by library instance [<LibN path>] consumed by library instance [<Lib N-1 path>] which is consumed by module[<Module path>] It doesn't print all the intermediate library instances between the Module and LibN but at least the path of Lib N-1 can help users to help how to fix the build errors. I hope this patch can be a trigger point that a better solution could be developed by tool experts to print all the library instances between the Module and LibN. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.fen@intel.com>
* SecurityPkg/HashLibTdx: Return EFI_UNSUPPORTED if it is not Tdx guestMin M Xu2022-06-161-1/+7
| | | | | | | | | | | HashLibTdx is designed for the Tdx guest. So if is not a Tdx guest, return EFI_UNSUPPORTED in RegisterHashInterfaceLib. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Use PcdOvmfWorkAreaBase instead of PcdSevEsWorkAreaBaseMin M Xu2022-06-162-3/+3
| | | | | | | | | | | | | It is an typo error that HobList pointer should be stored at PcdOvmfWorkAreaBase, not PcdSevEsWorkAreaBase. Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* DxeMain: Fix the bug that StackGuard is not enabledRay Ni2022-06-141-0/+8
| | | | | | | | | | | | Commit e7abb94d1 removed InitializeCpuExceptionHandlersEx and updated DxeMain to call InitializeCpuExceptionHandlers for exception setup. But the old behavior that calls *Ex() sets up the stack guard as well. To match the old behavior, the patch calls InitializeSeparateExceptionStacks. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn>
* ArmPkg/ArmExceptionLib: Follow new CpuExceptionHandlerLib APIsRay Ni2022-06-141-47/+11
| | | | | | | | | | | | | | | | | CpuExceptionHandlerLib has been refactored with following changes: 1. Removed InitializeCpuInterruptHandlers in 2a09527ebcb459b40 2. Removed InitializeCpuExceptionHandlersEx and added InitializeSeparateExceptionStacks in e7abb94d1fb8a0e7 The patch updates ARM version of CpuExceptionHandlerLib to follow the API changes. The functionality to ARM platforms should be none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseLib: Add CRC16-ANSI and CRC32c implementationsPedro Falcato2022-06-132-1/+178
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3871 Add the CRC16-ANSI and CRC32C implementations previously found at Features/Ext4Pkg/Ext4Dxe/Crc{16,32c}.c to BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove "assert" from SmmCpuRendevousLibNull.cZhihao Li2022-06-131-1/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3931 Some drivers will break down when they use SmmWaitForAllProcessor() which from SmmCpuRendezvousLibNull.c. Removing the code "ASSERT(False)" will make consumer work normally if they keep default setting for sync mode. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhihao Li <zhihao.li@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* Revert "OvmfPkg/Sec: fix stack switch"Gerd Hoffmann2022-06-102-7/+3
| | | | | | | | | This reverts commit ff36b2550f94dc5fac838cf298ae5a23cfddf204. Has no effect because GCC_IA32_CC_FLAGS and GCC_X64_CC_FLAGS are unused. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitializeRay Ni2022-06-101-24/+29
| | | | | | | | | | | | | | | | | The AP vector consists of 2 parts: 1. the initial 16-bit code that should be under 1MB and page aligned. 2. the 32-bit/64-bit code that can be anywhere in the memory with any alignment. The need of part #2 is because the memory under 1MB is temporary "stolen" for use and will "give" back after all AP wake up. The range of memory is not marked as code page in page table. CPU may trigger exception as soon as NX is enabled. The part #2 memory allocation can be done in the MpInitLibInitialize. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Only allocate below 1MB memory for 16bit codeRay Ni2022-06-103-56/+46
| | | | | | | | | | | | | | | | | | | Today's implementation allocates below 1MB memory for the 16bit, 32bit and 64bit code. But it's not necessary since now the 32bit and 64bit code run at high memory no matter in PEI and DXE phase. The patch simplifies the logic to remove the code that handles the case when WakeupBufferHigh is 0. It also reduce the memory foot print under 1MB by allocating memory for 16bit code only. MP_CPU_EXCHANGE_INFO is still under 1MB which is immediate after the 16bit code. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Put SEV logic in separate fileRay Ni2022-06-106-172/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | The patch does several simplifications: 1. Treat SwitchToRealProc as part of RendezvousFunnelProc. So the common logic in MpLib.c doesn't need to be aware of SwitchToRealProc. As a result, SwitchToRealSize/Offset are removed from MP_ASSEMBLY_ADDRESS_MAP. 2. Move SwitchToRealProc to AmdSev.nasm. All other assembly code in AmdSev.nasm is called through OneTimeCall. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Michael Roth <michael.roth@amd.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* MpInitLib: remove unneeded global ASM_PFXRay Ni2022-06-102-15/+3
| | | | | | | | | global in NASM file is used for symbols that are referenced in C files. Remove unneeded global keyword in NASM file. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MpInitLib: Allocate code buffer for PEI phaseRay Ni2022-06-104-8/+13
| | | | | | | | | | Today's implementation assumes PEI phase runs at 32bit so the execution-disable feature is not applicable. It's not always TRUE. The patch allocates 32bit&64bit code buffer for PEI phase as well. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuException: Add InitializeSeparateExceptionStacksRay Ni2022-06-109-184/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today InitializeCpuExceptionHandlersEx is called from three modules: 1. DxeCore (links to DxeCpuExceptionHandlerLib) DxeCore expects it initializes the IDT entries as well as assigning separate stacks for #DF and #PF. 2. CpuMpPei (links to PeiCpuExceptionHandlerLib) and CpuDxe (links to DxeCpuExceptionHandlerLib) It's called for each thread for only assigning separate stacks for #DF and #PF. The IDT entries initialization is skipped because caller sets InitData->X64.InitDefaultHandlers to FALSE. Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib also implement such API and the behavior of the API is simply to initialize IDT entries only. Because it mixes the IDT entries initialization and separate stacks assignment for certain exception handlers together, in order to know whether the function call only initializes IDT entries, or assigns stacks, we need to check: 1. value of InitData->X64.InitDefaultHandlers 2. library instance This patch cleans up the code to separate the stack assignment to a new API: InitializeSeparateExceptionStacks(). Only when caller calls the new API, the separate stacks are assigned. With this change, the SecPei and Smm instance can return unsupported which gives caller a very clear status. The old API InitializeCpuExceptionHandlersEx() is removed in this patch. Because no platform module is consuming the old API, the impact is none. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com>
* CpuException: Remove InitializeCpuInterruptHandlersRay Ni2022-06-108-262/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | InitializeCpuExceptionHandlers() expects caller allocates IDT while InitializeCpuInterruptHandlers() allocates 256 IDT entries itself. InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated by caller. If caller allocates 10 entries, the API just fills 10 IDT entries. The inconsistency between the two APIs makes code hard to unerstand and hard to share. Because there is only one caller (CpuDxe) for InitializeCpuInterruptHandler(), this patch updates CpuDxe driver to allocates 256 IDT entries then call InitializeCpuExceptionHandlers(). This is also a backward compatible change. With this change, InitializeCpuInterruptHandlers() is removed completely. And InitializeCpuExceptionHandlers() fills max 32 entries for PEI and SMM instance, max 256 entries for DXE instance. Such behavior matches to the original one. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Avoid allocating page but using global variablesRay Ni2022-06-101-19/+5
| | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Init global variables in-placeRay Ni2022-06-102-13/+12
| | | | | | | | | Additionally removed two useless global variables: "SPIN_LOCK mDisplayMessageSpinLock" from SMM instance. "UINTN mEnabledInterruptNum" from DXE instance. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* CpuException: Avoid allocating code pages for DXE instanceRay Ni2022-06-104-28/+9
| | | | | | | | | | | | | | | | | | | | | | | | Today the DXE instance allocates code page and then copies the IDT vectors to the allocated code page. Then it fixes up the vector number in the IDT vector. But if we update the NASM file to generate 256 IDT vectors, there is no need to do the copy and fix-up. A side effect is 4096 bytes (HOOKAFTER_STUB_SIZE * 256) is used for 256 IDT vectors while 32 IDT vectors only require 512 bytes without this change, in following library instances: 1. 32bit SecPeiCpuExceptionHandlerLib and PeiCpuExceptionHandlerLib 2. 64bit PeiCpuExceptionHandlerLib But considering the code logic simplification, 3.5K extra space is not a big deal. If 3.5K is too much, we can enhance the code further to generate 32 vectors for above mentioned library instances. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Acked-by: Eric Dong <eric.dong@intel.com>
* OvmfPkg/Sec: fix stack switchGerd Hoffmann2022-06-082-3/+7
| | | | | | | | | | | | | | | | | | | | The ebp/rbp register can either be used for the frame pointer or as general purpose register. With gcc (and clang) this depends on the -f(no-)omit-frame-pointer switch. This patch updates tools_def.template to explicitly set the compiler option and also add a define to allow conditionally compile code. The new define is used to fix stack switching in TemporaryRamMigration. The ebp/rbp must not be touched when the compiler can use it as general purpose register. With version 12 gcc starts actually using the register, so changing it leads to firmware crashes in some configurations. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3934 Reported-by: Jiri Slaby <jirislaby@kernel.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Delete SecMeasurementLibTdxMin M Xu2022-06-074-420/+0
| | | | | | | | | | The feature of SecMeasurementLibTdx is replaced by SecTpmMeasurementLibTdx (which is in SecurityPkg). So SecMeasurementLibTdx is deleted. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* OvmfPkg: Implement MeasureHobList/MeasureFvImageMin M Xu2022-06-075-3/+224
| | | | | | | | | | | | | | | | | | | | | MeasureHobList and MeasureFvImage once were implemented in SecMeasurementTdxLib. The intention of this patch-set is to refactor SecMeasurementTdxLib to be an instance of TpmMeasurementLib. So these 2 functions (MeasureHobList/MeasureFvImage) are moved to PeilessStartupLib. This is because: 1. RTMR based trusted boot is implemented in Config-B (See below link) 2. PeilessStartupLib is designed for PEI-less boot and it is the right place to do the measurement for Hoblist and Config-FV. Config-B: https://edk2.groups.io/g/devel/message/76367 Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* Security: Add SecTpmMeasurementLibTdxMin M Xu2022-06-073-0/+212
| | | | | | | | | | | | | | | | SecTpmMeasurementLitTdx is an instance of TpmMeasurementLib. It is designed to used in a Td guest. This lib measures and logs data, and extendx the measurement result into a specific RTMR. SecTpmMeasurementLibTdx is a refactored lib of OvmfPkg/Library/SecMeasurementLibTdx and it just copies GetMappedRtmrIndex/TdxMeasureAndLogData from that lib. At the end of this patch-set SecMeasurementLibTdx will be deleted. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package pathKun Qin2022-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942 `IgnoreFiles` tag is specified in the CI YAML files in each individual packages. The current logic for UncrustifyCheck script bases specified file paths from workspace, which requires the package name to be included in each entry. This change updates the ignore checking logic to be based on current package path in order to reduce redundancy. It also keeps the consistency of `IgnoreFiles` field other pytools such as SpellCheck and EccCheck. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* BaseTools: Fix dependency issue in PcdValueInitJake Garver2022-06-061-1/+2
| | | | | | | | | The generated Makefile was missing a dependency. This resulted in a build-time race condition if the recursive make is multi-threaded and shares job control. Signed-off-by: Jake Garver <jake@nvidia.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 17:40:16 +0000