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* OvmfPkg/RiscVVirt: Add Stack HOBedk2-stable202302Sunil V L2023-03-011-3/+6
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4350 Currently, stack HOB is not created for the stack memory. This causes stack memory to be treated as free memory and any memory allocation which happens at this address causes random memory corruption. Fix this by creating the stack HOB which marks the memory as BS data. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reported-by: Andrei Warkentin <andrei.warkentin@intel.com> Tested-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* UefiPayloadPkg: remove the change that get platform specific logicMarsX Lin2023-02-234-114/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4241 Since UefiPayloadPkg had supported multiple firmware volume, remove the platform specific logic via protocol Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* OvmfPkg/RiscVVirt: Fix SCT memory allocation test case failureSunil V L2023-02-231-2/+3
| | | | | | | | | | | | | | | Fix the UEFI memory range calculation by including the correct stack memory range. Without this fix, SCT hangs in MemoryAllocation test cases which call AllocateAddress(). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* BaseTools/tools_def.template: Update -march parameter for RISC-VSunil V L2023-02-231-1/+1
| | | | | | | | | | | | | | | | | | Replace rv64imafdc with rv64gc so that it works for gcc 12. "g" means imafd in gcc < 12 and imafd_zifencei_zicsr in gcc >= 12. So, replacing rv64imafdc with rv64gc will work for both gcc <12 and gcc >=12. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: Update WindowsVsToolChain pluginJoey Vagedes2023-02-162-6/+14
| | | | | | | | | | | | | | | This patch updates edk2-pytool-library dependency to v0.14.0, which has an interface change to FindWithVsWhere. The BaseTools plugin uses this function, so it is being updated to account for the interface change. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@microsoft.com> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* Maintainers.txt: Add entry for OvmfPkg/RiscVVirtSunil V L2023-02-161-0/+5
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/RiscVVirt: Add build files for Qemu Virt platformSunil V L2023-02-165-0/+1266
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/RiscVVirt: Add SEC moduleSunil V L2023-02-167-0/+673
| | | | | | | | | | | | | | | Add the SEC module for RISC-V Qemu virt machine support. It uses the PEI less design. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe moduleSunil V L2023-02-162-0/+605
| | | | | | | | | | | | | | | | Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for IO access. This is copied from ArmPciCpuIo2Dxe driver. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib librarySunil V L2023-02-162-0/+70
| | | | | | | | | | | | | | | Qemu NOR flash driver needs this library. Add this library for RISC-V leveraged from SbsaQemu. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/RiscVVirt: Add ResetSystemLib librarySunil V L2023-02-162-0/+166
| | | | | | | | | | | | | | | RISC-V Qemu virt uses SBI calls to implement the reset. Add the base class library. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib librarySunil V L2023-02-162-0/+88
| | | | | | | | | | | | | | | Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine since it follows PEIless design. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg/RiscVVirt: Add PlatformBootManagerLib librarySunil V L2023-02-164-0/+1275
| | | | | | | | | | | | | | | | RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt leveraging the one from Arm. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
* ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxeSunil V L2023-02-166-8/+8
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the new location. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkgSunil V L2023-02-164-11/+8
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V fileSunil V L2023-02-161-0/+1
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add CpuDxeRiscV64 moduleSunil V L2023-02-166-0/+660
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe and added the RISCV_EFI_BOOT_PROTOCOL support. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* UefiCpuPkg: Add CpuTimerDxeRiscV64 moduleSunil V L2023-02-166-0/+549
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg: Add BaseRiscV64CpuTimerLib librarySunil V L2023-02-164-0/+247
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add the RISC-V instance of the TimerLib. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLibSunil V L2023-02-166-0/+412
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add Cpu Exception Handler library for RISC-V. This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitionsSunil V L2023-02-162-0/+41
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@intel.com>
* MdePkg: Add BaseRiscVSbiLib Library for RISC-VSunil V L2023-02-166-0/+460
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseLib: RISC-V: Add few more helper functionsSunil V L2023-02-166-4/+179
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Register: Add register definition header files for RISC-VSunil V L2023-02-162-0/+144
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Added Call for AfterReadyToBoot EventRobert Phelps2023-02-152-0/+15
| | | | | | | | | | | In the function EfiSignalEventReadyToBoot, Code was added to also create, signal, and close the AfterReadyToBoot event. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Robert Phelps <robert@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add After Ready To Boot Event Definition from UEFI 2.9Robert Phelps2023-02-152-0/+8
| | | | | | | | | | Add After Ready To Boot Event Definitions Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Robert Phelps <robert@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Library: PcdAcpiS3Enable set FALSE cause Assertlijun10x2023-02-151-24/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms don't support S3 with PcdAcpiS3Enable set as False. Debug mode bios will ASSERT at this time as Follows. ASSERT_RETURN_ERROR (Status = Out of Resources) DXE_ASSERT!: Edk2\MdePkg\Library\BaseS3PciSegmentLib\S3PciSegmentLib.c (61): !(((INTN)(RETURN_STATUS)(Status)) < 0) Steps to reproduce the issue: 1.Set PcdAcpiS3Enable to FALSE. 2.Build the bios in debug mode. 3.Power on and Check the serial log. Note: Prerequisite is that S3PciSegmentLib is Called and the caller's code is run. Root Cause: S3PciSegmentLib call S3BootScriptLib controlled by PcdAcpiS3Enable. If PcdAcpiS3Enable set as false, S3BootScriptLib will return error status(Out of Resources). S3PciSegmentLib will ASSERT if S3BootScriptLib return error. Solution: Make S3BootScriptLib return success if PcdAcpiS3Enable was disabled, which behave as a null S3BootScriptLib instance which just return success for no action is required to do. Signed-off-by: JunX1 Li <junx1.li@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Sunny Wang <sunny.wang@arm.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Cc: G Edhaya Chandran <edhaya.chandran@arm.com> Cc: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Variable: Attribute combination should return EFI_UNSUPPORTEDStuart Yoder2023-02-151-1/+5
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4341 Commit 21320ef66989 broke some tests in the AuthVar_Conf test in edk2-test. There are 2 testcases that invoke SetVariable with the following attribute value: (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS) EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and the UEFI spec says this should return EFI_UNSUPPORTED. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Sunny Wang <Sunny.Wang@arm.com> Signed-off-by: Stuart Yoder <stuart.yoder@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
* MdeModulePkg/EsrtFmpDxe: Support multiple devices with 0 HardwareInstancedevel@edk2.groups.io2023-02-151-9/+13
| | | | | | | | | | | | | | Skip error check if HardwareInstance is 0 as this either means that FmpVersion < 3 and not supported or, "A zero means the FMP provider is not able to determine a unique hardware instance number or a hardware instance number is not needed." per UEFI specification. As the FmpInstances are merged and HardwareInstance is not used remove error check in this case. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdeModulePkg/Pci: Display more information of PCIe devicesAbner Chang2023-02-151-2/+5
| | | | | | | | | | | | | | | | In V4: Update the copyright to 2023. In V3: Add AMD copyright. In V2: Remove the signed-off-by: Abner Chang Display PCIe Vendor ID and Device ID in DEBUG message. Signed-off-by: Jiangang He <jiangang.he@amd.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
* OvmfPkg/AmdSevDxe: Close mAcceptAllMemoryEventDionna Glaze2023-02-151-0/+1
| | | | | | | | | | | | | | | | This event should only trigger once. It should be idempotent, but the allocation of the memory map itself is observable and can cause ExitBootServices to fail with a modified map key. Cc: Thomas Lendacky <Thomas.Lendacky@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Michael Roth <michael.roth@amd.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Fix SevMemoryAcceptance memory attributesDionna Glaze2023-02-151-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hard-coded attributes for the re-added memory space should instead forward the replaced descriptor's capabilities. Tested on Linux with efi=debug. Prior to this change, an 8GiB VM running a kernel without unaccepted memory support shows this entry efi: mem94: [Conventional| | |CC| | | | | | | | | | | ] range=[0x0000000100000000-0x000000023fffffff] (5120MB) This does not have the cache capabilities one would expect for system memory, UC|WC|WT|WB. After this change, the same entry becomes efi: mem94: [Conventional| | |CC| | | | | | | |WB|WT|WC|UC] range=[0x0000000100000000-0x000000023fffffff] (5120MB) This has all the expected attributes. Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com> [ardb: drop the EFI_MEMORY_CPU_CRYPTO flag - it isn't used anywhere else in EDK2 or Linux so it doesn't actually do anything, and it is unclear whether it is intended for use by the guest in the first place] Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* .devcontainer/devcontainer.json: Add devcontainer fileMichael Kubacki2023-02-142-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tianocore maintains container images in the tianocore/containers repo and stores container images within the GitHub container registry. https://github.com/tianocore/containers This change adds a devcontainer.json file to the edk2 repo. This file's metadata and settings to configurate a development container for a given well-defined tool and runtime stack. More information about the devcontainer.json file is available here: https://containers.dev/implementors/json_reference/ This file is recognized by popular tools such as GitHub Codespaces and VS Code. In VS Code in particular, it makes it much easier for a user to be aware a dev container exists (via UI notifications) and to load the container. A minimal number of VS Code extensions are specified that are useful for edk2 development or to assist in complying with CI checks in place in edk2. Cc: Andrew Fish <afish@apple.com> Cc: Chris Fernald <chris.fernald@outlook.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Oliver Steffen <osteffen@redhat.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* .mergify/config.yml: Remove rebase_fallback attribute (deprecated)Michael Kubacki2023-02-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR builds and CI are currently broken due to a mergify brownout today because edk2 uses the `rebase_fallback` attribute of the `queue` action. Message from Mergify/Summary: ``` The configuration uses the deprecated rebase_fallback attribute of the queue action. A brownout is planned on February 13th, 2023. This option will be removed on March 13th, 2023. For more information: https://docs.mergify.com/actions/queue/ ``` Therefore, this change removes the attribute per the guidance in the following changelog message to retain existing behavior. https://changelog.mergify.com/changelog/rebasefallback-is-deprecated ``` The option rebase_fallback is now deprecated and should not be used anymore. Mergify will always report errors in the future if a rebase merge is impossible. ``` Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Sean Brogan <sean.brogan@microsoft.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: Add NVMe boot partition header definitionWeipu Zhu2023-02-101-0/+13
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4304 Add NVMe boot partition header definition to NVMe.h according to NVMe spec 2.0. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Weipu Zhu <weipu.zhu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add RPMB related commands and DCB definition for NVMeWeipu Zhu2023-02-101-1/+45
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4303 Add RPMB(Replay Protected Memory Block) access commands, result and DCB(Device Configuration Block) definition for NVMe according to the NVMe spec 2.0. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Weipu Zhu <weipu.zhu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
* RedfishPkg/RedfishRestExDxe: Two PCDs for controlling the requestsAbner Chang2023-02-094-62/+116
| | | | | | | | | | | | Since BIOS should work with different BMC implementation chunked requests as well as Expect header should be optional. - One PCD is used to enable/disable Expect header. - Another PCD is used to enable/disable chunked requests. Reviewed-by: Abner Chang <abner.chang@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Nickle Wang <nicklew@nvidia.com> Signed-off-by: Igor Kulchytskyy <igork@ami.com>
* StandaloneMmPkg/StandaloneMmMemLib: Change max address computationGirish Mahadevan2023-02-091-14/+1
| | | | | | | | | | Currently the standalonemmlibinternal assumes the max physical bits to be 36 which is causing issues on v8 architectures. Instead use the MAX_ALLOC_ADDRESS macro to determine the maximum allowed address rather than recomputing it locally. Signed-off-by: Girish Mahadevan <gmahadevan@nvidia.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Update build.sh to allow building OVMF then running QEMURebecca Cran2023-02-091-8/+5
| | | | | | | | Allow users to build OVMF then run QEMU by moving the build block above the run block and removing the exit line. Signed-off-by: Rebecca Cran <rebecca@quicinc.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* EmulatorPkg/PeiTimerLib: Bug fix in NanoSecondDelayDeric Cole2023-02-092-3/+3
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4339 Thunk->Sleep is expecting nanoseconds, no need to multiply by 100. Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Deric Cole <deric.cole@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* .pytool/Plugin/EccCheck: Add PACKAGES_PATH supportMarvin Ha?user2023-02-081-1/+8
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4326 EccBuild currently assumes all packages reside in WORKSPACE. However, this is obviously not the case for many setups. Most notably, Ext4Pkg is located in edk2-platforms/Features and thus cannot be in WORKSPACE in any reasonable setup. Use Edk2Path to locate the package in WORKSPACE and PACKAGES_PATH. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Marvin H?user <mhaeuser@posteo.de> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg:IORT header update for IORT Rev E.e specSwatisri Kantamsetti2023-02-071-0/+4
| | | | | | | | | | | | | | The IO Remapping Table, Platform Design Document, Revision E.e, Sept 2022 (https://developer.arm.com/documentation/den0049/ee) added flags in SMMUv3 node for validity of ID mappings for MSIs related to control interrupts. Therefore, update the IORT header file to: - increment IORT table revision to 6 - add support for DeviceId valid flag Signed-off-by: Swatisri Kantamsetti <swatisrik@nvidia.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: EfiUnacceptedMemoryType is not allowed in AllocatePoolMin M Xu2023-02-071-1/+1
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4315 MemoryType of EfiUnacceptedMemoryType should not be allocated in AllocatePool. Instead it should return EFI_INVALID_PARAMETER. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Reported-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Min Xu <min.m.xu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Disambiguate the meaning of PcdDxeIplSwitchToLongModeZhiguang Liu2023-02-071-3/+1
| | | | | | | | | | | | | | | | | Literally, the meaning of PcdDxeIplSwitchToLongMode is clear, indicating whether need switch to long mode when loading DxeCore. However, the comments in dec are confusing for the case where PEI core and DXE core are both in 64-bit. This patch makes it clear. PcdDxeIplSwitchToLongMode is true only when PEI core is 32-bit, and switch to long mode to load 64-bit DXE core. In other cases, this PCD is false. This also aligns with current usage in OvmfPkg. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Ray Ni <ray.ni@intel.com>
* BaseTools: remove useless dependency on libuuidThierry LARONDE2023-02-072-10/+1
| | | | | Signed-off-by: Thierry LARONDE <tlaronde@polynum.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* RedfishPkg: fix multiple SMBIOS type 42 version issueNickle Wang2023-02-061-0/+8
| | | | | | | | | | | | | | RedfishHostInterfaceDxe does not close protocol notify event in event callback function. This could cause multiple version of type 42 records issue if the protocol is installed more than once. Close the event in callback function so we only create one type 42 record. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* ArmPkg/ArmScmiDxe: Fix the calculation of RequiredArraySizeSudeep Holla2023-02-061-23/+16
| | | | | | | | | | | | | | | | | | | | | | As per the SCMI specification, section CLOCK_DESCRIBE_RATES mentions that the value of num_rates_flags[11:0] in the response must be 3 if the return format is the triplet. Due to the buggy firmware, this was not noticed for long time. The firmware is now fixed resulting in ClockDescribeRates() to fail with "Buffer Too Small" error as the RequiredArraySize gets miscalculated as 72 instead of 24. Fix the issue by reusing the logic for both the return format which must work if num_rates_flags has correct value as expected from the specification. Cc: Girish Pathak <girish.pathak@arm.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Tested-by: Pierre Gondois <pierre.gondois@arm.com> Reported-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com>
* OvmfPkg/IntelTdx: Update READMEMin M Xu2023-02-041-12/+7
| | | | | | | | | | | | | | | | | TDVF's README is updated based on the latest feature. - RTMR based measurement is supported in OvmfPkgX64 (Config-A) - Features of Config-B have all been implemented, such as removing unnecessary attack surfaces. Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* SecurityPkg/TdTcg2Dxe: td-guest shall halt when CcMeasurement install failMin M Xu2023-02-041-0/+6
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4335 CcMeasurement protocol is installed when it is supported in a td-guest. If the installation of the protocol failed, the guest shall go into CpuDeadLoop. Because the measurement feature is crucial to a td-guest and it shall stop running immediately at this situation. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* SecurityPkg: don't require PK to be self-signed by defaultJan Bobek2023-02-041-1/+1
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2506 Change the default value of PcdRequireSelfSignedPk to FALSE in accordance with UEFI spec, which states that PK need not be self-signed when enrolling in setup mode. Note that this relaxes the legacy behavior, which required the PK to be self-signed in this case. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Jan Bobek <jbobek@nvidia.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 18:06:16 +0000