| Commit message (Collapse) | Author | Age | Files | Lines |
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Add a internal header file for StandaloneMmMemLib.
Move some common reference and declaration into
StandaloneMmMemLibInternal.h.
Signed-off-by: Dun Tan <dun.tan@intel.com>
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Remove unneeded check MmIsBufferOutsideMmValid() when
StandaloneMmCore checks if the BS data memory described
by a memory allocation HOB needs to be migrated to Mmram.
Currently, the API MmIsBufferOutsideMmValid() return TRUE
when input memory range belongs to non-Mmram memory. Now
the API will be changed in following 5 commits to return
TRUE when a memory range belongs to non-Mmram memroy and
the memory is inside a range described by resource HOB.
This may cause PF when some SMI handler access the memory
from a memory allocation HOB that is not migrated.
To solve this issue, we can directly remove the check
MmIsBufferOutsideMmValid() and always migrate the BS data
memory described by a memory allocation HOB to Mmram.
Signed-off-by: Dun Tan <dun.tan@intel.com>
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Clang compile will optimize undefined behavior (UB)
like a pointer with NULL + size, so it is better to
check the pointer before using it.
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4867
Added MM_STANDALONE support in Driver and BaseCryptLibOnProtocolPpi.
Signed-off-by: Kanagavel S <kanagavels@ami.com>
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Openssl 3.0.15 has a larger memory footprint.
Updating from EDK 2022.2 (openssl 1.1.j) to 2024.2 (openssl 3.0.15)
causes our EFI provisioning application[1] to fail due to an out of
memory condition.
On inspection, at the time of that fault, 2022.2 had an additional 900
pages. This is why this patch proposes the increase of the ScratchMemory
buffer by that same ammount.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/jejb/efitools.git
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
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Change subhook url from https://github.com/Zeex/subhook to
https://github.com/tianocore/edk2-subhook because old url is
no longer available.
Also align .gitmodules file to use consistent LF line endings.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4838
Updated the missed architectures in PeiCryptLib.inf file.
Signed-off-by: Kanagavel S <kanagavels@ami.com>
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Per AMD64 Architecture Programmer's Manual Volume 2: System
Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64
architecture does not use the legacy SMM state-save area format
(Table 10-2) for 32-bit SMRAM save state map. Clean up codes for the
invalid save state map.
Signed-off-by: Phil Noh <Phil.Noh@amd.com>
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Includes changes across the repo for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <tabeebe@microsoft.com>
Co-authored-by: kenlautner <85201046+kenlautner@users.noreply.github.com>
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4858
Ph52a PCIE to SATA card inserted on Intel MTL/ARL causes system hanged.
Root cause of this issue is because Ph52a's driver only uses DevicePath
protocol alone and EDK2 driver only uses PciIo protocol alone. Both
drivers start and try to manage SATA controller.
Signed-off-by: Paul Chang <paulchang@ami.com>
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There are couples of gUniversalPayloadAcpiTableGuid in
payload , only build one
gUniversalPayloadAcpiTableGuid hob and acpi memory hob.
when the reserved memory address matched the rsdp.
Signed-off-by: Linus Liu <linus.liu@intel.com>
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Per other platform request , need to add SMBIOS device node into FDT.
In the current phase(1) , only supporting SM3EntryPoint structure.
Signed-off-by: Linus Liu <linus.liu@intel.com>
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Per Spec updated , update DMA Reg property filed
with each root bridge bus base and its bus limit.
Signed-off-by: Linus Liu <linus.liu@intel.com>
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4-level paging supports translating 48-bit linear addresses to 52-bit
physical addresses. Since linear addresses are sign-extended,
the linear-address space of 4-level paging is: [0, 2^47-1] and
[0xffff8000_00000000, 0xffffffff_ffffffff]. So only [0, 2^47-1]
linear-address range maps to the identical physical-address range
when 5-Level paging is disabled.
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
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Makes changes to comply with alerts raised by CodeQL.
The issues here fall into the following category:
1. comparison-with-wider-type
Signed-off-by: Eeshan Londhe <eeshanlondhe@microsoft.com>
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Clang build for ArmVirtPkg/ArmVirtKvmTool.dsc fails with the below
warning:
| ld.lld: error: duplicate symbol: PciExpressRegisterForRuntimeAccess
| ld.lld: error: duplicate symbol: GetPciExpressBaseAddress
| ld.lld: error: duplicate symbol: PciExpressRead8
| ld.lld: error: duplicate symbol: PciExpressWrite8
| ld.lld: error: duplicate symbol: PciExpressOr8
| ld.lld: error: duplicate symbol: PciExpressAnd8
| ld.lld: error: duplicate symbol: PciExpressAndThenOr8
| ld.lld: error: duplicate symbol: PciExpressBitFieldRead8
| ld.lld: error: duplicate symbol: PciExpressBitFieldWrite8
| ld.lld: error: duplicate symbol: PciExpressBitFieldOr8
| ld.lld: error: duplicate symbol: PciExpressBitFieldAnd8
| ld.lld: error: duplicate symbol: PciExpressBitFieldAndThenOr8
| ld.lld: error: duplicate symbol: PciExpressRead16
| ld.lld: error: duplicate symbol: PciExpressWrite16
| ld.lld: error: duplicate symbol: PciExpressOr16
| ld.lld: error: duplicate symbol: PciExpressAnd16
| ld.lld: error: duplicate symbol: PciExpressAndThenOr16
| ld.lld: error: duplicate symbol: PciExpressBitFieldRead16
| ld.lld: error: duplicate symbol: PciExpressBitFieldWrite16
| ld.lld: error: duplicate symbol: PciExpressBitFieldOr16
| >>> defined in MdePkg/Library/BasePciExpressLib/BasePciExpressLib/OUTPUT/BasePciExpressLib.lib(PciExpressLib.obj)
| >>> defined in OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib/OUTPUT/BaseCachingPciExpressLib.lib(PciExpressLib.obj)
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| ld.lld: error: too many errors emitted, stopping now (use --error-limit=0 to see all errors)
| clang: error: linker command failed with exit code 1 (use -v to see invocation)
OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf is
getting linked as NULL library in these pacakges:
1. UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
2. MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
3. MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
which results in duplicate symbols shown in the warning above as
MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf is not properly replaced
by OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
as PciExpressLib library.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Signed-off-by: TsunFeng <v-tshuang@microsoft.com>
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As discussed with the stewards, I have decided to resume my role as a
maintainer in the Tianocore project (if they will have me, of course)
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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Check if input buffer range unblockable:
1.The input buffer range to block should be totally covered
by one or multi memory allocation HOB
2.All the memory allocation HOB that overlap with the input
buffer range should be EfiRuntimeServicesData, EfiACPIMemoryNVS
or EfiReservedMemoryType.
Signed-off-by: Dun Tan <dun.tan@intel.com>
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storage data format
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4857
NVS needs to support both authenticated and non-authenticated
header for NV region. PcdNvStoreDefaultValueBuffer can have
variables with data format of the type Authenticated variable storage
and this change provides the support to differentiate between
the normal variable storage and authenticated variable storage
for the hii database to consume and update the setup variables
accordingly
Signed-off-by: nikhil p sheshagiri <nikhil.p.sheshagiri@intel.com>
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BFV is outside the MMRAM. Currently, StandaloneMmIplPei uses the API
MmUnblockMemoryRequest() to unblock the access for the BFV. However,
the BFV's memory might be gone after ExitBootService event. If any
access to the memory, unexpected error would happen.
To fix the above issue, StandaloneMmCore should shadow standalone BFV
into MMRAM before processing it, then free the shadowed BFV after MM
driver dispatch is done.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
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Without this change, when building OvmfPkg with -D SMM_REQUIRE using
the XCODE5 toolchain we get:
error: equality comparison with extraneous parentheses
which stops the build.
Signed-off-by: Mike Beaton <mjsbeaton@gmail.com>
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In current implementation of MmCommunication, caller (StandaloneMmIplPei
or MmCommunicationDxe) sets the IsCommBufferValid to TRUE and triggers
synchronous MMI, then caller resets IsCommBufferValid to FLASE after MMI
exits.
If asynchronous MMI happens before caller resets the IsCommBufferValid
to FALSE, StandaloneMmCore will mistakenly thought there is still a
synchronous MMI and then update incorrect values into ReturnStatus and
ReturnBufferSize.
To fix the above issue, StandaloneMmCore should reset IsCommBufferValid
to FALSE before MMI exits.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Includes changes across the module for the following CodeQL rules:
- cpp/comparison-with-wider-type
- cpp/overflow-buffer
- cpp/redundant-null-check-param
- cpp/uselesstest
Co-authored-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
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Signed-off-by: Ashraf Ali <ashraf.ali.s@intel.com>
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Return from `FspsWrapperInitDispatchMode()` if a buffer allocation
fails instead of attempting to dereference the pointer.
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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Signed-off-by: v-sbolisetti <v-sbolisetti@microsoft.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4490
Added PPI support in UFS PEI driver to link the platform specific code
as same as UFS DXE driver.
Signed-off-by: Kanagavel S <kanagavels@ami.com>
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Some serial device may not support SetControl. Ignore the error from
SetControl if EFI_UNSUPPORTED is return.
Signed-off-by: Hua Ma <hua.ma@intel.com>
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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1559
Initializes the variable to prevent an uninitialized variable
warning in Visual Studio with C4701 enabled.
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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On AARCH64, there is no ordering guarantee between configuration
space (ECAM) writes and memory space reads (MMIO). ARM AMBA CHI
only guarantees ordering for reads and writes within a single address
region, however, on some systems MMIO and ECAM may be split into
separateaddress regions.
A problem may arise when an ECAM write is issued a completion before a
subsequent MMIO read is issued and receives a completion.
For example, a typical PCI software flow is the following:
1. ECAM write to device command register to enable memory space
2. MMIO read from device memory space for which access was enabled
in step 1.
There is no guarantee that step 2. will not begin before the completion
of step 1.
on systems where ECAM/MMIO are specified as separate address regions,
even
if both spaces have the memory attributes device-nGnRnE.
- Add a barrier after the final PCI Configuration space write
in RootBridgeIoPciAccess. Configuration space reads should not have
side-efects.
- When configuration space is strongly ordered, this ensures
that program execution cannot continue until the completion
is received for the previous Cfg-Write, which may have side-effects.
- Risk of reading a "write-only" register and causing a CA which leaves
the device unresponsive. The expectation based on the PCI Base Spec
v6.1 section 7.4 is that all PCI Spec-defined registers will be readable,
however, there may exist design-specific registers that fall into
this category.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
Co-authored-by: Ard Biesheuvel <ardb@kernel.org>
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To simplify automatic formatting of new code, this feature lets a
local developer specify the `UNCRUSTIFY_IN_PLACE=TRUE` parameter on
the command line to automatically format files.
This is particularly useful when a large amount of new code needs
to be formatted in batch.
See the readme for more details.
Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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Clang build breaks with the following error:
| DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c:1441:20:
| error: result of comparison of constant 256 with expression of type 'UINT8'
| (aka 'unsigned char') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
| 1441 | (AccessSize > 256)) ||
| | ~~~~~~~~~~ ^ ~~~
| 1 error generated.
AccessSize is UINT8 and the maximum value for UINT8 is 255, so the
comparision is unnecessary. Drop the check to fix the build.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Although EmbeddedPkg normally provides components to other
packages, it is less surprising if its own build defines
MDEPKG_NDEBUG when consuming packages normally would.
Signed-off-by: Mike Beaton <mjsbeaton@gmail.com>
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Remove small amount of MDEPKG_NDEBUG dependent code which
is no longer needed, given update of 'null' debug macros
in ae83c6b7fd83a5906e016a32027c1bcd792a624e to explicitly
mark debug-only code as discarded.
Additionally, correctly mark as STATIC the two arrays
within the updated code block.
Signed-off-by: Mike Beaton <mjsbeaton@gmail.com>
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GenFw relies on static ELF relocation tables emitted by the linker (via
the --emit-relocs command line switch). These are different from the
dynamic relocations that a dynamic loader uses: static relocations are
emitted by the compiler/assembler, and consumed by the linker to
construct the executable. Only when the load address is a priori unknown
are dynamic relocations emitted, by the linker, in a format that the
dynamic loader can consume.
This distinction is relevant because only dynamic relocations cover the
GOT, and so GOT based indirections are better avoided. Unfortunately,
there are cases where the toolchain insists on emitting GOT based symbol
references, and so we have to deal with them in one of 2 ways:
- replace GOT based symbol references with direct references, so that
the GOT entries themselves are no longer used, and can be ignored when
generating the PE/COFF relocation tables (AARCH64 and RISCV64 take
this approach);
- infer the locations of the GOT slots from the references appearing in
the code, and emit PE/COFF relocations for them so that their contents
will be fixed up appropriately.
The latter is the approach taken by GenFw for x86_64, which is the only
feasible approach for its ISA, given that GOT slots can be used as
memory operands in many different types of instructions, not all of
which can be converted straight-forwardly.
E.g.,
movq foo@GOTPCREL(%rip), %rax
can always be converted into
leaq foo(%rip), %rax
whereas
cmpq foo@GOTPCREL(%rip), %rax
can only be converted under the 32-bit position dependent code model,
into
cmpq $foo, %rax
and so the GOT references cannot be elided when generating position
independent code, which is what GenFw requires.
To remove the need for the linker to guess where the instructions start,
the ELF psABI for x86_64 specifies a couple of relaxable alternatives
for GOTPCREL, which are used to annotate particular classes of GOT
referencing instructions that may be relaxed to their non-GOT
counterparts.
There is no specification for what --emit-relocs is supposed to produce,
or whether or not its output is supposed to reflect such relaxations.
ld.bfd and LLD behave differently in this regard, and the latter may
emit R_X86_64_REX_GOTPCRELX relocations for MOV instructions that it
already has relaxed into LEA instructions. This means the displacement
in the instruction no longer refers to the GOT slot, but directly to the
object itself, and emitting a relocation is not only unnecessary, but
also harmful as the PE/COFF loader will corrupt the object when it
applies the relocations at startup.
Under the position independent code model, the only relaxation that the
linker could have applied for a R_X86_64_REX_GOTPCRELX relocation is MOV
to LEA, so detect whether the instruction is already LEA, and ignore the
relocation if that is the case.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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[Issue Description]
CXL_ERROR_PCIE_DEV_ID in Cper.h was renamed to EFI_CXL_ERROR_PCIE_DEV_ID,
but EFI_CXL_COMPONENT_EVENT_LOG still uses previous name.
[Resolution]
Modify EFI_CXL_COMPONENT_EVENT_LOG to use EFI_CXL_ERROR_PCIE_DEV_ID
Signed-off-by: Sienski Piotr <piotr.sienski@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4861
Added PROCESSOR_FAMILY_NAME support in ShellPkg.
Signed-off-by: Revathy <revathyv@ami.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4861
Added PROCESSOR_FAMILY_NAME support in MdePkg.
Signed-off-by: Revathy <revathyv@ami.com>
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Copy the provided configuration data for
PM1 event block.
Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Library/CompilerIntrinsicsLib was moved from ArmPkg to MdePkg.
Since MdePkg is passing EccCheck without needing to ignore
CompilerIntrinsicsLib, just remove it from ArmPkg.ci.yaml.
This fixes the error during "stuart_ci_build":
ERROR - EccCheck.IgnoreInf ->
Build/.pytool/Plugin/EccCheck/ArmPkg/Library/CompilerIntrinsicsLib
not found in filesystem. Invalid ignore files
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
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Update WSMT table with generic creator id.
Cc: Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Class specific types for interface and endpoint are generic
- Definitions are in IndustryStandard/Usb.h
- Remove type redefinitions
- Update references to the descriptor types
Signed-off-by: Oleg Ilyasov <olegi@ami.com>
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